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12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/mm.h>
15#include <linux/sched.h>
16#include <linux/pci.h>
17#include <linux/ioport.h>
18#include <linux/timex.h>
19#include <linux/init.h>
20
21#include <asm/ptrace.h>
22#include <asm/dma.h>
23#include <asm/irq.h>
24#include <asm/mmu_context.h>
25#include <asm/io.h>
26#include <asm/core_cia.h>
27#include <asm/tlbflush.h>
28
29#include "proto.h"
30#include "irq_impl.h"
31#include "pci_impl.h"
32#include "machvec_impl.h"
33
34
35static void __init
36ruffian_init_irq(void)
37{
38
39 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
40 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb();
41
42 outb(0x11,0xA0);
43 outb(0x08,0xA1);
44 outb(0x02,0xA1);
45 outb(0x01,0xA1);
46 outb(0xFF,0xA1);
47
48 outb(0x11,0x20);
49 outb(0x00,0x21);
50 outb(0x04,0x21);
51 outb(0x01,0x21);
52 outb(0xFF,0x21);
53
54
55 outb(0x20,0xA0);
56 outb(0x20,0x20);
57
58 init_i8259a_irqs();
59
60
61
62 init_pyxis_irqs(0x16f0000);
63
64 common_init_isa_dma();
65}
66
67#define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ)
68
69static void __init
70ruffian_init_rtc(void)
71{
72
73
74
75
76 outb(0x34, 0x43);
77 outb(RUFFIAN_LATCH & 0xff, 0x40);
78 outb(RUFFIAN_LATCH >> 8, 0x40);
79
80 outb(0xb6, 0x43);
81 outb(0x31, 0x42);
82 outb(0x13, 0x42);
83
84 if (request_irq(0, rtc_timer_interrupt, 0, "timer", NULL))
85 pr_err("Failed to request irq 0 (timer)\n");
86}
87
88static void
89ruffian_kill_arch (int mode)
90{
91 cia_kill_arch(mode);
92#if 0
93
94
95 *(vuip) PYXIS_RESET = 0x0000dead;
96 mb();
97#endif
98}
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121static int
122ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
123{
124 static char irq_tab[11][5] = {
125
126 {-1, -1, -1, -1, -1},
127 {-1, -1, -1, -1, -1},
128 {44, 44, 44, 44, 44},
129 {-1, -1, -1, -1, -1},
130 {43, 43, 42, 41, 40},
131
132 {19, 19, 18, 17, 16},
133 {31, 31, 30, 29, 28},
134 {27, 27, 26, 25, 24},
135 {39, 39, 38, 37, 36},
136 {35, 35, 34, 33, 32},
137 {20, 20, 20, 20, 20},
138 };
139 const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
140 return COMMON_TABLE_LOOKUP;
141}
142
143static u8
144ruffian_swizzle(struct pci_dev *dev, u8 *pinp)
145{
146 int slot, pin = *pinp;
147
148 if (dev->bus->number == 0) {
149 slot = PCI_SLOT(dev->devfn);
150 }
151
152 else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
153 slot = PCI_SLOT(dev->devfn) + 10;
154 }
155 else
156 {
157
158 do {
159 if (PCI_SLOT(dev->bus->self->devfn) == 13) {
160 slot = PCI_SLOT(dev->devfn) + 10;
161 break;
162 }
163 pin = pci_swizzle_interrupt_pin(dev, pin);
164
165
166 dev = dev->bus->self;
167
168 slot = PCI_SLOT(dev->devfn);
169 } while (dev->bus->self);
170 }
171 *pinp = pin;
172 return slot;
173}
174
175#ifdef BUILDING_FOR_MILO
176
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180
181static unsigned long __init
182ruffian_get_bank_size(unsigned long offset)
183{
184 unsigned long bank_addr, bank, ret = 0;
185
186
187
188 bank_addr = (unsigned long)PYXIS_MCR + offset;
189 bank = *(vulp)bank_addr;
190
191
192 if (bank & 0x01) {
193 static unsigned long size[] __initdata = {
194 0x40000000UL,
195 0x20000000UL,
196 0x10000000UL,
197 0x08000000UL,
198 0x04000000UL,
199 0x02000000UL,
200 0x01000000UL,
201 0x00800000UL,
202 0x80000000UL,
203 };
204
205 bank = (bank & 0x1e) >> 1;
206 if (bank < ARRAY_SIZE(size))
207 ret = size[bank];
208 }
209
210 return ret;
211}
212#endif
213
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217
218struct alpha_machine_vector ruffian_mv __initmv = {
219 .vector_name = "Ruffian",
220 DO_EV5_MMU,
221 DO_DEFAULT_RTC,
222 DO_PYXIS_IO,
223 .machine_check = cia_machine_check,
224 .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
225 .min_io_address = DEFAULT_IO_BASE,
226 .min_mem_address = DEFAULT_MEM_BASE,
227 .pci_dac_offset = PYXIS_DAC_OFFSET,
228
229 .nr_irqs = 48,
230 .device_interrupt = pyxis_device_interrupt,
231
232 .init_arch = pyxis_init_arch,
233 .init_irq = ruffian_init_irq,
234 .init_rtc = ruffian_init_rtc,
235 .init_pci = cia_init_pci,
236 .kill_arch = ruffian_kill_arch,
237 .pci_map_irq = ruffian_map_irq,
238 .pci_swizzle = ruffian_swizzle,
239};
240ALIAS_MV(ruffian)
241