1
2
3
4
5
6config ARC
7 def_bool y
8 select ARC_TIMERS
9 select ARCH_HAS_DEBUG_VM_PGTABLE
10 select ARCH_HAS_DMA_PREP_COHERENT
11 select ARCH_HAS_PTE_SPECIAL
12 select ARCH_HAS_SETUP_DMA_OPS
13 select ARCH_HAS_SYNC_DMA_FOR_CPU
14 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
16 select ARCH_32BIT_OFF_T
17 select BUILDTIME_TABLE_SORT
18 select CLONE_BACKWARDS
19 select COMMON_CLK
20 select DMA_DIRECT_REMAP
21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
22 select GENERIC_CLOCKEVENTS
23 select GENERIC_FIND_FIRST_BIT
24
25 select GENERIC_IRQ_SHOW
26 select GENERIC_PCI_IOMAP
27 select GENERIC_PENDING_IRQ if SMP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_KGDB
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_COPY_THREAD_TLS
33 select HAVE_DEBUG_STACKOVERFLOW
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_FUTEX_CMPXCHG if FUTEX
36 select HAVE_IOREMAP_PROT
37 select HAVE_KERNEL_GZIP
38 select HAVE_KERNEL_LZMA
39 select HAVE_KPROBES
40 select HAVE_KRETPROBES
41 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_OPROFILE
43 select HAVE_PERF_EVENTS
44 select HANDLE_DOMAIN_IRQ
45 select IRQ_DOMAIN
46 select MODULES_USE_ELF_RELA
47 select OF
48 select OF_EARLY_FLATTREE
49 select PCI_SYSCALL if PCI
50 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
51 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
52
53config ARCH_HAS_CACHE_LINE_SIZE
54 def_bool y
55
56config TRACE_IRQFLAGS_SUPPORT
57 def_bool y
58
59config LOCKDEP_SUPPORT
60 def_bool y
61
62config SCHED_OMIT_FRAME_POINTER
63 def_bool y
64
65config GENERIC_CSUM
66 def_bool y
67
68config ARCH_DISCONTIGMEM_ENABLE
69 def_bool n
70
71config ARCH_FLATMEM_ENABLE
72 def_bool y
73
74config MMU
75 def_bool y
76
77config NO_IOPORT_MAP
78 def_bool y
79
80config GENERIC_CALIBRATE_DELAY
81 def_bool y
82
83config GENERIC_HWEIGHT
84 def_bool y
85
86config STACKTRACE_SUPPORT
87 def_bool y
88 select STACKTRACE
89
90config HAVE_ARCH_TRANSPARENT_HUGEPAGE
91 def_bool y
92 depends on ARC_MMU_V4
93
94menu "ARC Architecture Configuration"
95
96menu "ARC Platform/SoC/Board"
97
98source "arch/arc/plat-tb10x/Kconfig"
99source "arch/arc/plat-axs10x/Kconfig"
100
101source "arch/arc/plat-eznps/Kconfig"
102source "arch/arc/plat-hsdk/Kconfig"
103
104endmenu
105
106choice
107 prompt "ARC Instruction Set"
108 default ISA_ARCV2
109
110config ISA_ARCOMPACT
111 bool "ARCompact ISA"
112 select CPU_NO_EFFICIENT_FFS
113 help
114 The original ARC ISA of ARC600/700 cores
115
116config ISA_ARCV2
117 bool "ARC ISA v2"
118 select ARC_TIMERS_64BIT
119 help
120 ISA for the Next Generation ARC-HS cores
121
122endchoice
123
124menu "ARC CPU Configuration"
125
126choice
127 prompt "ARC Core"
128 default ARC_CPU_770 if ISA_ARCOMPACT
129 default ARC_CPU_HS if ISA_ARCV2
130
131if ISA_ARCOMPACT
132
133config ARC_CPU_750D
134 bool "ARC750D"
135 select ARC_CANT_LLSC
136 help
137 Support for ARC750 core
138
139config ARC_CPU_770
140 bool "ARC770"
141 select ARC_HAS_SWAPE
142 help
143 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
144 This core has a bunch of cool new features:
145 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
146 Shared Address Spaces (for sharing TLB entries in MMU)
147 -Caches: New Prog Model, Region Flush
148 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
149
150endif
151
152config ARC_CPU_HS
153 bool "ARC-HS"
154 depends on ISA_ARCV2
155 help
156 Support for ARC HS38x Cores based on ARCv2 ISA
157 The notable features are:
158 - SMP configurations of up to 4 cores with coherency
159 - Optional L2 Cache and IO-Coherency
160 - Revised Interrupt Architecture (multiple priorites, reg banks,
161 auto stack switch, auto regfile save/restore)
162 - MMUv4 (PIPT dcache, Huge Pages)
163 - Instructions for
164 * 64bit load/store: LDD, STD
165 * Hardware assisted divide/remainder: DIV, REM
166 * Function prologue/epilogue: ENTER_S, LEAVE_S
167 * IRQ enable/disable: CLRI, SETI
168 * pop count: FFS, FLS
169 * SETcc, BMSKN, XBFU...
170
171endchoice
172
173config ARC_TUNE_MCPU
174 string "Override default -mcpu compiler flag"
175 default ""
176 help
177 Override default -mcpu=xxx compiler flag (which is set depending on
178 the ISA version) with the specified value.
179 NOTE: If specified flag isn't supported by current compiler the
180 ISA default value will be used as a fallback.
181
182config CPU_BIG_ENDIAN
183 bool "Enable Big Endian Mode"
184 help
185 Build kernel for Big Endian Mode of ARC CPU
186
187config SMP
188 bool "Symmetric Multi-Processing"
189 select ARC_MCIP if ISA_ARCV2
190 help
191 This enables support for systems with more than one CPU.
192
193if SMP
194
195config NR_CPUS
196 int "Maximum number of CPUs (2-4096)"
197 range 2 4096
198 default "4"
199
200config ARC_SMP_HALT_ON_RESET
201 bool "Enable Halt-on-reset boot mode"
202 help
203 In SMP configuration cores can be configured as Halt-on-reset
204 or they could all start at same time. For Halt-on-reset, non
205 masters are parked until Master kicks them so they can start off
206 at designated entry point. For other case, all jump to common
207 entry point and spin wait for Master's signal.
208
209endif
210
211config ARC_MCIP
212 bool "ARConnect Multicore IP (MCIP) Support "
213 depends on ISA_ARCV2
214 default y if SMP
215 help
216 This IP block enables SMP in ARC-HS38 cores.
217 It provides for cross-core interrupts, multi-core debug
218 hardware semaphores, shared memory,....
219
220menuconfig ARC_CACHE
221 bool "Enable Cache Support"
222 default y
223
224if ARC_CACHE
225
226config ARC_CACHE_LINE_SHIFT
227 int "Cache Line Length (as power of 2)"
228 range 5 7
229 default "6"
230 help
231 Starting with ARC700 4.9, Cache line length is configurable,
232 This option specifies "N", with Line-len = 2 power N
233 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
234 Linux only supports same line lengths for I and D caches.
235
236config ARC_HAS_ICACHE
237 bool "Use Instruction Cache"
238 default y
239
240config ARC_HAS_DCACHE
241 bool "Use Data Cache"
242 default y
243
244config ARC_CACHE_PAGES
245 bool "Per Page Cache Control"
246 default y
247 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
248 help
249 This can be used to over-ride the global I/D Cache Enable on a
250 per-page basis (but only for pages accessed via MMU such as
251 Kernel Virtual address or User Virtual Address)
252 TLB entries have a per-page Cache Enable Bit.
253 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
254 Global DISABLE + Per Page ENABLE won't work
255
256config ARC_CACHE_VIPT_ALIASING
257 bool "Support VIPT Aliasing D$"
258 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
259
260endif
261
262config ARC_HAS_ICCM
263 bool "Use ICCM"
264 help
265 Single Cycle RAMS to store Fast Path Code
266
267config ARC_ICCM_SZ
268 int "ICCM Size in KB"
269 default "64"
270 depends on ARC_HAS_ICCM
271
272config ARC_HAS_DCCM
273 bool "Use DCCM"
274 help
275 Single Cycle RAMS to store Fast Path Data
276
277config ARC_DCCM_SZ
278 int "DCCM Size in KB"
279 default "64"
280 depends on ARC_HAS_DCCM
281
282config ARC_DCCM_BASE
283 hex "DCCM map address"
284 default "0xA0000000"
285 depends on ARC_HAS_DCCM
286
287choice
288 prompt "MMU Version"
289 default ARC_MMU_V3 if ARC_CPU_770
290 default ARC_MMU_V2 if ARC_CPU_750D
291 default ARC_MMU_V4 if ARC_CPU_HS
292
293if ISA_ARCOMPACT
294
295config ARC_MMU_V1
296 bool "MMU v1"
297 help
298 Orig ARC700 MMU
299
300config ARC_MMU_V2
301 bool "MMU v2"
302 help
303 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
304 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
305
306config ARC_MMU_V3
307 bool "MMU v3"
308 depends on ARC_CPU_770
309 help
310 Introduced with ARC700 4.10: New Features
311 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
312 Shared Address Spaces (SASID)
313
314endif
315
316config ARC_MMU_V4
317 bool "MMU v4"
318 depends on ISA_ARCV2
319
320endchoice
321
322
323choice
324 prompt "MMU Page Size"
325 default ARC_PAGE_SIZE_8K
326
327config ARC_PAGE_SIZE_8K
328 bool "8KB"
329 help
330 Choose between 8k vs 16k
331
332config ARC_PAGE_SIZE_16K
333 bool "16KB"
334 depends on ARC_MMU_V3 || ARC_MMU_V4
335
336config ARC_PAGE_SIZE_4K
337 bool "4KB"
338 depends on ARC_MMU_V3 || ARC_MMU_V4
339
340endchoice
341
342choice
343 prompt "MMU Super Page Size"
344 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
345 default ARC_HUGEPAGE_2M
346
347config ARC_HUGEPAGE_2M
348 bool "2MB"
349
350config ARC_HUGEPAGE_16M
351 bool "16MB"
352
353endchoice
354
355config NODES_SHIFT
356 int "Maximum NUMA Nodes (as a power of 2)"
357 default "0" if !DISCONTIGMEM
358 default "1" if DISCONTIGMEM
359 depends on NEED_MULTIPLE_NODES
360 help
361 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
362 zones.
363
364config ARC_COMPACT_IRQ_LEVELS
365 depends on ISA_ARCOMPACT
366 bool "Setup Timer IRQ as high Priority"
367
368 depends on !SMP
369
370config ARC_FPU_SAVE_RESTORE
371 bool "Enable FPU state persistence across context switch"
372 help
373 ARCompact FPU has internal registers to assist with Double precision
374 Floating Point operations. There are control and stauts registers
375 for floating point exceptions and rounding modes. These are
376 preserved across task context switch when enabled.
377
378config ARC_CANT_LLSC
379 def_bool n
380
381config ARC_HAS_LLSC
382 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
383 default y
384 depends on !ARC_CANT_LLSC
385
386config ARC_HAS_SWAPE
387 bool "Insn: SWAPE (endian-swap)"
388 default y
389
390if ISA_ARCV2
391
392config ARC_USE_UNALIGNED_MEM_ACCESS
393 bool "Enable unaligned access in HW"
394 default y
395 select HAVE_EFFICIENT_UNALIGNED_ACCESS
396 help
397 The ARC HS architecture supports unaligned memory access
398 which is disabled by default. Enable unaligned access in
399 hardware and use software to use it
400
401config ARC_HAS_LL64
402 bool "Insn: 64bit LDD/STD"
403 help
404 Enable gcc to generate 64-bit load/store instructions
405 ISA mandates even/odd registers to allow encoding of two
406 dest operands with 2 possible source operands.
407 default y
408
409config ARC_HAS_DIV_REM
410 bool "Insn: div, divu, rem, remu"
411 default y
412
413config ARC_HAS_ACCL_REGS
414 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
415 default y
416 help
417 Depending on the configuration, CPU can contain accumulator reg-pair
418 (also referred to as r58:r59). These can also be used by gcc as GPR so
419 kernel needs to save/restore per process
420
421config ARC_DSP_HANDLED
422 def_bool n
423
424config ARC_DSP_SAVE_RESTORE_REGS
425 def_bool n
426
427choice
428 prompt "DSP support"
429 default ARC_DSP_NONE
430 help
431 Depending on the configuration, CPU can contain DSP registers
432 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
433 Bellow is options describing how to handle these registers in
434 interrupt entry / exit and in context switch.
435
436config ARC_DSP_NONE
437 bool "No DSP extension presence in HW"
438 help
439 No DSP extension presence in HW
440
441config ARC_DSP_KERNEL
442 bool "DSP extension in HW, no support for userspace"
443 select ARC_HAS_ACCL_REGS
444 select ARC_DSP_HANDLED
445 help
446 DSP extension presence in HW, no support for DSP-enabled userspace
447 applications. We don't save / restore DSP registers and only do
448 some minimal preparations so userspace won't be able to break kernel
449
450config ARC_DSP_USERSPACE
451 bool "Support DSP for userspace apps"
452 select ARC_HAS_ACCL_REGS
453 select ARC_DSP_HANDLED
454 select ARC_DSP_SAVE_RESTORE_REGS
455 help
456 DSP extension presence in HW, support save / restore DSP registers to
457 run DSP-enabled userspace applications
458
459config ARC_DSP_AGU_USERSPACE
460 bool "Support DSP with AGU for userspace apps"
461 select ARC_HAS_ACCL_REGS
462 select ARC_DSP_HANDLED
463 select ARC_DSP_SAVE_RESTORE_REGS
464 help
465 DSP and AGU extensions presence in HW, support save / restore DSP
466 and AGU registers to run DSP-enabled userspace applications
467endchoice
468
469config ARC_IRQ_NO_AUTOSAVE
470 bool "Disable hardware autosave regfile on interrupts"
471 default n
472 help
473 On HS cores, taken interrupt auto saves the regfile on stack.
474 This is programmable and can be optionally disabled in which case
475 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
476
477config ARC_LPB_DISABLE
478 bool "Disable loop buffer (LPB)"
479 help
480 On HS cores, loop buffer (LPB) is programmable in runtime and can
481 be optionally disabled.
482
483endif
484
485endmenu
486
487config LINUX_LINK_BASE
488 hex "Kernel link address"
489 default "0x80000000"
490 help
491 ARC700 divides the 32 bit phy address space into two equal halves
492 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
493 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
494 Typically Linux kernel is linked at the start of untransalted addr,
495 hence the default value of 0x8zs.
496 However some customers have peripherals mapped at this addr, so
497 Linux needs to be scooted a bit.
498 If you don't know what the above means, leave this setting alone.
499 This needs to match memory start address specified in Device Tree
500
501config LINUX_RAM_BASE
502 hex "RAM base address"
503 default LINUX_LINK_BASE
504 help
505 By default Linux is linked at base of RAM. However in some special
506 cases (such as HSDK), Linux can't be linked at start of DDR, hence
507 this option.
508
509config HIGHMEM
510 bool "High Memory Support"
511 select ARCH_DISCONTIGMEM_ENABLE
512 help
513 With ARC 2G:2G address split, only upper 2G is directly addressable by
514 kernel. Enable this to potentially allow access to rest of 2G and PAE
515 in future
516
517config ARC_HAS_PAE40
518 bool "Support for the 40-bit Physical Address Extension"
519 depends on ISA_ARCV2
520 select HIGHMEM
521 select PHYS_ADDR_T_64BIT
522 help
523 Enable access to physical memory beyond 4G, only supported on
524 ARC cores with 40 bit Physical Addressing support
525
526config ARC_KVADDR_SIZE
527 int "Kernel Virtual Address Space size (MB)"
528 range 0 512
529 default "256"
530 help
531 The kernel address space is carved out of 256MB of translated address
532 space for catering to vmalloc, modules, pkmap, fixmap. This however may
533 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
534 this to be stretched to 512 MB (by extending into the reserved
535 kernel-user gutter)
536
537config ARC_CURR_IN_REG
538 bool "Dedicate Register r25 for current_task pointer"
539 default y
540 help
541 This reserved Register R25 to point to Current Task in
542 kernel mode. This saves memory access for each such access
543
544
545config ARC_EMUL_UNALIGNED
546 bool "Emulate unaligned memory access (userspace only)"
547 select SYSCTL_ARCH_UNALIGN_NO_WARN
548 select SYSCTL_ARCH_UNALIGN_ALLOW
549 depends on ISA_ARCOMPACT
550 help
551 This enables misaligned 16 & 32 bit memory access from user space.
552 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
553 potential bugs in code
554
555config HZ
556 int "Timer Frequency"
557 default 100
558
559config ARC_METAWARE_HLINK
560 bool "Support for Metaware debugger assisted Host access"
561 help
562 This options allows a Linux userland apps to directly access
563 host file system (open/creat/read/write etc) with help from
564 Metaware Debugger. This can come in handy for Linux-host communication
565 when there is no real usable peripheral such as EMAC.
566
567menuconfig ARC_DBG
568 bool "ARC debugging"
569 default y
570
571if ARC_DBG
572
573config ARC_DW2_UNWIND
574 bool "Enable DWARF specific kernel stack unwind"
575 default y
576 select KALLSYMS
577 help
578 Compiles the kernel with DWARF unwind information and can be used
579 to get stack backtraces.
580
581 If you say Y here the resulting kernel image will be slightly larger
582 but not slower, and it will give very useful debugging information.
583 If you don't debug the kernel, you can say N, but we may not be able
584 to solve problems without frame unwind information
585
586config ARC_DBG_TLB_PARANOIA
587 bool "Paranoia Checks in Low Level TLB Handlers"
588
589config ARC_DBG_JUMP_LABEL
590 bool "Paranoid checks in Static Keys (jump labels) code"
591 depends on JUMP_LABEL
592 default y if STATIC_KEYS_SELFTEST
593 help
594 Enable paranoid checks and self-test of both ARC-specific and generic
595 part of static keys (jump labels) related code.
596endif
597
598config ARC_BUILTIN_DTB_NAME
599 string "Built in DTB"
600 help
601 Set the name of the DTB to embed in the vmlinux binary
602 Leaving it blank selects the minimal "skeleton" dtb
603
604endmenu
605
606config FORCE_MAX_ZONEORDER
607 int "Maximum zone order"
608 default "12" if ARC_HUGEPAGE_16M
609 default "11"
610
611source "kernel/power/Kconfig"
612
