LXR linux/arch/powerpc/kvm/book3s

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 *
   4 * Copyright SUSE Linux Products GmbH 2010
   5 *
   6 * Authors: Alexander Graf <agraf@suse.de>
   7 */
   8
   9/* Real mode helpers */
  10
  11#include <asm/asm-compat.h>
  12#include <asm/feature-fixups.h>
  13
  14#if defined(CONFIG_PPC_BOOK3S_64)
  15
  16#define GET_SHADOW_VCPU(reg)    \
  17        mr      reg, r13
  18
  19#elif defined(CONFIG_PPC_BOOK3S_32)
  20
  21#define GET_SHADOW_VCPU(reg)                            \
  22        tophys(reg, r2);                        \
  23        lwz     reg, (THREAD + THREAD_KVM_SVCPU)(reg);  \
  24        tophys(reg, reg)
  25
  26#endif
  27
  28/* Disable for nested KVM */
  29#define USE_QUICK_LAST_INST
  30
  31
  32/* Get helper functions for subarch specific functionality */
  33
  34#if defined(CONFIG_PPC_BOOK3S_64)
  35#include "book3s_64_slb.S"
  36#elif defined(CONFIG_PPC_BOOK3S_32)
  37#include "book3s_32_sr.S"
  38#endif
  39
  40/******************************************************************************
  41 *                                                                            *
  42 *                               Entry code                                   *
  43 *                                                                            *
  44 *****************************************************************************/
  45
  46.global kvmppc_handler_trampoline_enter
  47kvmppc_handler_trampoline_enter:
  48
  49        /* Required state:
  50         *
  51         * MSR = ~IR|DR
  52         * R1 = host R1
  53         * R2 = host R2
  54         * R4 = guest shadow MSR
  55         * R5 = normal host MSR
  56         * R6 = current host MSR (EE, IR, DR off)
  57         * LR = highmem guest exit code
  58         * all other volatile GPRS = free
  59         * SVCPU[CR] = guest CR
  60         * SVCPU[XER] = guest XER
  61         * SVCPU[CTR] = guest CTR
  62         * SVCPU[LR] = guest LR
  63         */
  64
  65        /* r3 = shadow vcpu */
  66        GET_SHADOW_VCPU(r3)
  67
  68        /* Save guest exit handler address and MSR */
  69        mflr    r0
  70        PPC_STL r0, HSTATE_VMHANDLER(r3)
  71        PPC_STL r5, HSTATE_HOST_MSR(r3)
  72
  73        /* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
  74        PPC_STL r1, HSTATE_HOST_R1(r3)
  75        PPC_STL r2, HSTATE_HOST_R2(r3)
  76
  77        /* Activate guest mode, so faults get handled by KVM */
  78        li      r11, KVM_GUEST_MODE_GUEST
  79        stb     r11, HSTATE_IN_GUEST(r3)
  80
  81        /* Switch to guest segment. This is subarch specific. */
  82        LOAD_GUEST_SEGMENTS
  83
  84#ifdef CONFIG_PPC_BOOK3S_64
  85BEGIN_FTR_SECTION
  86        /* Save host FSCR */
  87        mfspr   r8, SPRN_FSCR
  88        std     r8, HSTATE_HOST_FSCR(r13)
  89        /* Set FSCR during guest execution */
  90        ld      r9, SVCPU_SHADOW_FSCR(r13)
  91        mtspr   SPRN_FSCR, r9
  92END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
  93
  94        /* Some guests may need to have dcbz set to 32 byte length.
  95         *
  96         * Usually we ensure that by patching the guest's instructions
  97         * to trap on dcbz and emulate it in the hypervisor.
  98         *
  99         * If we can, we should tell the CPU to use 32 byte dcbz though,
 100         * because that's a lot faster.
 101         */
 102        lbz     r0, HSTATE_RESTORE_HID5(r3)
 103        cmpwi   r0, 0
 104        beq     no_dcbz32_on
 105
 106        mfspr   r0,SPRN_HID5
 107        ori     r0, r0, 0x80            /* XXX HID5_dcbz32 = 0x80 */
 108        mtspr   SPRN_HID5,r0
 109no_dcbz32_on:
 110
 111#endif /* CONFIG_PPC_BOOK3S_64 */
 112
 113        /* Enter guest */
 114
 115        PPC_LL  r8, SVCPU_CTR(r3)
 116        PPC_LL  r9, SVCPU_LR(r3)
 117        lwz     r10, SVCPU_CR(r3)
 118        PPC_LL  r11, SVCPU_XER(r3)
 119
 120        mtctr   r8
 121        mtlr    r9
 122        mtcr    r10
 123        mtxer   r11
 124
 125        /* Move SRR0 and SRR1 into the respective regs */
 126        PPC_LL  r9, SVCPU_PC(r3)
 127        /* First clear RI in our current MSR value */
 128        li      r0, MSR_RI
 129        andc    r6, r6, r0
 130
 131        PPC_LL  r0, SVCPU_R0(r3)
 132        PPC_LL  r1, SVCPU_R1(r3)
 133        PPC_LL  r2, SVCPU_R2(r3)
 134        PPC_LL  r5, SVCPU_R5(r3)
 135        PPC_LL  r7, SVCPU_R7(r3)
 136        PPC_LL  r8, SVCPU_R8(r3)
 137        PPC_LL  r10, SVCPU_R10(r3)
 138        PPC_LL  r11, SVCPU_R11(r3)
 139        PPC_LL  r12, SVCPU_R12(r3)
 140        PPC_LL  r13, SVCPU_R13(r3)
 141
 142        MTMSR_EERI(r6)
 143        mtsrr0  r9
 144        mtsrr1  r4
 145
 146        PPC_LL  r4, SVCPU_R4(r3)
 147        PPC_LL  r6, SVCPU_R6(r3)
 148        PPC_LL  r9, SVCPU_R9(r3)
 149        PPC_LL  r3, (SVCPU_R3)(r3)
 150
 151        RFI_TO_GUEST
 152kvmppc_handler_trampoline_enter_end:
 153
 154
 155
 156/******************************************************************************
 157 *                                                                            *
 158 *                               Exit code                                    *
 159 *                                                                            *
 160 *****************************************************************************/
 161
 162.global kvmppc_interrupt_pr
 163kvmppc_interrupt_pr:
 164        /* 64-bit entry. Register usage at this point:
 165         *
 166         * SPRG_SCRATCH0   = guest R13
 167         * R12             = (guest CR << 32) | exit handler id
 168         * R13             = PACA
 169         * HSTATE.SCRATCH0 = guest R12
 170         */
 171#ifdef CONFIG_PPC64
 172        /* Match 32-bit entry */
 173        rotldi  r12, r12, 32              /* Flip R12 halves for stw */
 174        stw     r12, HSTATE_SCRATCH1(r13) /* CR is now in the low half */
 175        srdi    r12, r12, 32              /* shift trap into low half */
 176#endif
 177
 178.global kvmppc_handler_trampoline_exit
 179kvmppc_handler_trampoline_exit:
 180        /* Register usage at this point:
 181         *
 182         * SPRG_SCRATCH0   = guest R13
 183         * R12             = exit handler id
 184         * R13             = shadow vcpu (32-bit) or PACA (64-bit)
 185         * HSTATE.SCRATCH0 = guest R12
 186         * HSTATE.SCRATCH1 = guest CR
 187         */
 188
 189        /* Save registers */
 190
 191        PPC_STL r0, SVCPU_R0(r13)
 192        PPC_STL r1, SVCPU_R1(r13)
 193        PPC_STL r2, SVCPU_R2(r13)
 194        PPC_STL r3, SVCPU_R3(r13)
 195        PPC_STL r4, SVCPU_R4(r13)
 196        PPC_STL r5, SVCPU_R5(r13)
 197        PPC_STL r6, SVCPU_R6(r13)
 198        PPC_STL r7, SVCPU_R7(r13)
 199        PPC_STL r8, SVCPU_R8(r13)
 200        PPC_STL r9, SVCPU_R9(r13)
 201        PPC_STL r10, SVCPU_R10(r13)
 202        PPC_STL r11, SVCPU_R11(r13)
 203
 204        /* Restore R1/R2 so we can handle faults */
 205        PPC_LL  r1, HSTATE_HOST_R1(r13)
 206        PPC_LL  r2, HSTATE_HOST_R2(r13)
 207
 208        /* Save guest PC and MSR */
 209#ifdef CONFIG_PPC64
 210BEGIN_FTR_SECTION
 211        andi.   r0, r12, 0x2
 212        cmpwi   cr1, r0, 0
 213        beq     1f
 214        mfspr   r3,SPRN_HSRR0
 215        mfspr   r4,SPRN_HSRR1
 216        andi.   r12,r12,0x3ffd
 217        b       2f
 218END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 219#endif
 2201:      mfsrr0  r3
 221        mfsrr1  r4
 2222:
 223        PPC_STL r3, SVCPU_PC(r13)
 224        PPC_STL r4, SVCPU_SHADOW_SRR1(r13)
 225
 226        /* Get scratch'ed off registers */
 227        GET_SCRATCH0(r9)
 228        PPC_LL  r8, HSTATE_SCRATCH0(r13)
 229        lwz     r7, HSTATE_SCRATCH1(r13)
 230
 231        PPC_STL r9, SVCPU_R13(r13)
 232        PPC_STL r8, SVCPU_R12(r13)
 233        stw     r7, SVCPU_CR(r13)
 234
 235        /* Save more register state  */
 236
 237        mfxer   r5
 238        mfdar   r6
 239        mfdsisr r7
 240        mfctr   r8
 241        mflr    r9
 242
 243        PPC_STL r5, SVCPU_XER(r13)
 244        PPC_STL r6, SVCPU_FAULT_DAR(r13)
 245        stw     r7, SVCPU_FAULT_DSISR(r13)
 246        PPC_STL r8, SVCPU_CTR(r13)
 247        PPC_STL r9, SVCPU_LR(r13)
 248
 249        /*
 250         * In order for us to easily get the last instruction,
 251         * we got the #vmexit at, we exploit the fact that the
 252         * virtual layout is still the same here, so we can just
 253         * ld from the guest's PC address
 254         */
 255
 256        /* We only load the last instruction when it's safe */
 257        cmpwi   r12, BOOK3S_INTERRUPT_DATA_STORAGE
 258        beq     ld_last_inst
 259        cmpwi   r12, BOOK3S_INTERRUPT_PROGRAM
 260        beq     ld_last_inst
 261        cmpwi   r12, BOOK3S_INTERRUPT_SYSCALL
 262        beq     ld_last_prev_inst
 263        cmpwi   r12, BOOK3S_INTERRUPT_ALIGNMENT
 264        beq-    ld_last_inst
 265#ifdef CONFIG_PPC64
 266BEGIN_FTR_SECTION
 267        cmpwi   r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
 268        beq-    ld_last_inst
 269END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 270BEGIN_FTR_SECTION
 271        cmpwi   r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
 272        beq-    ld_last_inst
 273END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 274#endif
 275
 276        b       no_ld_last_inst
 277
 278ld_last_prev_inst:
 279        addi    r3, r3, -4
 280
 281ld_last_inst:
 282        /* Save off the guest instruction we're at */
 283
 284        /* In case lwz faults */
 285        li      r0, KVM_INST_FETCH_FAILED
 286
 287#ifdef USE_QUICK_LAST_INST
 288
 289        /* Set guest mode to 'jump over instruction' so if lwz faults
 290         * we'll just continue at the next IP. */
 291        li      r9, KVM_GUEST_MODE_SKIP
 292        stb     r9, HSTATE_IN_GUEST(r13)
 293
 294        /*    1) enable paging for data */
 295        mfmsr   r9
 296        ori     r11, r9, MSR_DR                 /* Enable paging for data */
 297        mtmsr   r11
 298        sync
 299        /*    2) fetch the instruction */
 300        lwz     r0, 0(r3)
 301        /*    3) disable paging again */
 302        mtmsr   r9
 303        sync
 304
 305#endif
 306        stw     r0, SVCPU_LAST_INST(r13)
 307
 308no_ld_last_inst:
 309
 310        /* Unset guest mode */
 311        li      r9, KVM_GUEST_MODE_NONE
 312        stb     r9, HSTATE_IN_GUEST(r13)
 313
 314        /* Switch back to host MMU */
 315        LOAD_HOST_SEGMENTS
 316
 317#ifdef CONFIG_PPC_BOOK3S_64
 318
 319        lbz     r5, HSTATE_RESTORE_HID5(r13)
 320        cmpwi   r5, 0
 321        beq     no_dcbz32_off
 322
 323        li      r4, 0
 324        mfspr   r5,SPRN_HID5
 325        rldimi  r5,r4,6,56
 326        mtspr   SPRN_HID5,r5
 327
 328no_dcbz32_off:
 329
 330BEGIN_FTR_SECTION
 331        /* Save guest FSCR on a FAC_UNAVAIL interrupt */
 332        cmpwi   r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
 333        bne+    no_fscr_save
 334        mfspr   r7, SPRN_FSCR
 335        std     r7, SVCPU_SHADOW_FSCR(r13)
 336no_fscr_save:
 337        /* Restore host FSCR */
 338        ld      r8, HSTATE_HOST_FSCR(r13)
 339        mtspr   SPRN_FSCR, r8
 340END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 341
 342#endif /* CONFIG_PPC_BOOK3S_64 */
 343
 344        /*
 345         * For some interrupts, we need to call the real Linux
 346         * handler, so it can do work for us. This has to happen
 347         * as if the interrupt arrived from the kernel though,
 348         * so let's fake it here where most state is restored.
 349         *
 350         * Having set up SRR0/1 with the address where we want
 351         * to continue with relocation on (potentially in module
 352         * space), we either just go straight there with rfi[d],
 353         * or we jump to an interrupt handler if there is an
 354         * interrupt to be handled first.  In the latter case,
 355         * the rfi[d] at the end of the interrupt handler will
 356         * get us back to where we want to continue.
 357         */
 358
 359        /* Register usage at this point:
 360         *
 361         * R1       = host R1
 362         * R2       = host R2
 363         * R10      = raw exit handler id
 364         * R12      = exit handler id
 365         * R13      = shadow vcpu (32-bit) or PACA (64-bit)
 366         * SVCPU.*  = guest *
 367         *
 368         */
 369
 370        PPC_LL  r6, HSTATE_HOST_MSR(r13)
 371#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 372        /*
 373         * We don't want to change MSR[TS] bits via rfi here.
 374         * The actual TM handling logic will be in host with
 375         * recovered DR/IR bits after HSTATE_VMHANDLER.
 376         * And MSR_TM can be enabled in HOST_MSR so rfid may
 377         * not suppress this change and can lead to exception.
 378         * Manually set MSR to prevent TS state change here.
 379         */
 380        mfmsr   r7
 381        rldicl  r7, r7, 64 - MSR_TS_S_LG, 62
 382        rldimi  r6, r7, MSR_TS_S_LG, 63 - MSR_TS_T_LG
 383#endif
 384        PPC_LL  r8, HSTATE_VMHANDLER(r13)
 385
 386#ifdef CONFIG_PPC64
 387BEGIN_FTR_SECTION
 388        beq     cr1, 1f
 389        mtspr   SPRN_HSRR1, r6
 390        mtspr   SPRN_HSRR0, r8
 391END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 392#endif
 3931:      /* Restore host msr -> SRR1 */
 394        mtsrr1  r6
 395        /* Load highmem handler address */
 396        mtsrr0  r8
 397
 398        /* RFI into the highmem handler, or jump to interrupt handler */
 399        cmpwi   r12, BOOK3S_INTERRUPT_EXTERNAL
 400        beqa    BOOK3S_INTERRUPT_EXTERNAL
 401        cmpwi   r12, BOOK3S_INTERRUPT_DECREMENTER
 402        beqa    BOOK3S_INTERRUPT_DECREMENTER
 403        cmpwi   r12, BOOK3S_INTERRUPT_PERFMON
 404        beqa    BOOK3S_INTERRUPT_PERFMON
 405        cmpwi   r12, BOOK3S_INTERRUPT_DOORBELL
 406        beqa    BOOK3S_INTERRUPT_DOORBELL
 407
 408        RFI_TO_KERNEL
 409kvmppc_handler_trampoline_exit_end:
 410