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18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/slab.h>
22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/clk/ti.h>
28
29#include "clock.h"
30
31#define DRA7_ATL_INSTANCES 4
32
33#define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
34#define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
35#define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
36#define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
37#define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
38#define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
39#define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
40
41#define DRA7_ATL_SWEN BIT(0)
42#define DRA7_ATL_DIVIDER_MASK (0x1f)
43#define DRA7_ATL_PCLKMUX BIT(0)
44struct dra7_atl_clock_info;
45
46struct dra7_atl_desc {
47 struct clk *clk;
48 struct clk_hw hw;
49 struct dra7_atl_clock_info *cinfo;
50 int id;
51
52 bool probed;
53 bool valid;
54 bool enabled;
55 u32 bws;
56 u32 aws;
57 u32 divider;
58};
59
60struct dra7_atl_clock_info {
61 struct device *dev;
62 void __iomem *iobase;
63
64 struct dra7_atl_desc *cdesc;
65};
66
67#define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
68
69static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
70 u32 val)
71{
72 __raw_writel(val, cinfo->iobase + reg);
73}
74
75static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
76{
77 return __raw_readl(cinfo->iobase + reg);
78}
79
80static int atl_clk_enable(struct clk_hw *hw)
81{
82 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
83
84 if (!cdesc->probed)
85 goto out;
86
87 if (unlikely(!cdesc->valid))
88 dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
89 cdesc->id);
90 pm_runtime_get_sync(cdesc->cinfo->dev);
91
92 atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
93 cdesc->divider - 1);
94 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
95
96out:
97 cdesc->enabled = true;
98
99 return 0;
100}
101
102static void atl_clk_disable(struct clk_hw *hw)
103{
104 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
105
106 if (!cdesc->probed)
107 goto out;
108
109 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
110 pm_runtime_put_sync(cdesc->cinfo->dev);
111
112out:
113 cdesc->enabled = false;
114}
115
116static int atl_clk_is_enabled(struct clk_hw *hw)
117{
118 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
119
120 return cdesc->enabled;
121}
122
123static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
124 unsigned long parent_rate)
125{
126 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
127
128 return parent_rate / cdesc->divider;
129}
130
131static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long *parent_rate)
133{
134 unsigned divider;
135
136 divider = (*parent_rate + rate / 2) / rate;
137 if (divider > DRA7_ATL_DIVIDER_MASK + 1)
138 divider = DRA7_ATL_DIVIDER_MASK + 1;
139
140 return *parent_rate / divider;
141}
142
143static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
144 unsigned long parent_rate)
145{
146 struct dra7_atl_desc *cdesc;
147 u32 divider;
148
149 if (!hw || !rate)
150 return -EINVAL;
151
152 cdesc = to_atl_desc(hw);
153 divider = ((parent_rate + rate / 2) / rate) - 1;
154 if (divider > DRA7_ATL_DIVIDER_MASK)
155 divider = DRA7_ATL_DIVIDER_MASK;
156
157 cdesc->divider = divider + 1;
158
159 return 0;
160}
161
162static const struct clk_ops atl_clk_ops = {
163 .enable = atl_clk_enable,
164 .disable = atl_clk_disable,
165 .is_enabled = atl_clk_is_enabled,
166 .recalc_rate = atl_clk_recalc_rate,
167 .round_rate = atl_clk_round_rate,
168 .set_rate = atl_clk_set_rate,
169};
170
171static void __init of_dra7_atl_clock_setup(struct device_node *node)
172{
173 struct dra7_atl_desc *clk_hw = NULL;
174 struct clk_init_data init = { NULL };
175 const char **parent_names = NULL;
176 struct clk *clk;
177
178 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
179 if (!clk_hw) {
180 pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
181 return;
182 }
183
184 clk_hw->hw.init = &init;
185 clk_hw->divider = 1;
186 init.name = node->name;
187 init.ops = &atl_clk_ops;
188 init.flags = CLK_IGNORE_UNUSED;
189 init.num_parents = of_clk_get_parent_count(node);
190
191 if (init.num_parents != 1) {
192 pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
193 node);
194 goto cleanup;
195 }
196
197 parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
198
199 if (!parent_names)
200 goto cleanup;
201
202 parent_names[0] = of_clk_get_parent_name(node, 0);
203
204 init.parent_names = parent_names;
205
206 clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
207
208 if (!IS_ERR(clk)) {
209 of_clk_add_provider(node, of_clk_src_simple_get, clk);
210 kfree(parent_names);
211 return;
212 }
213cleanup:
214 kfree(parent_names);
215 kfree(clk_hw);
216}
217CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
218
219static int of_dra7_atl_clk_probe(struct platform_device *pdev)
220{
221 struct device_node *node = pdev->dev.of_node;
222 struct dra7_atl_clock_info *cinfo;
223 int i;
224 int ret = 0;
225
226 if (!node)
227 return -ENODEV;
228
229 cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
230 if (!cinfo)
231 return -ENOMEM;
232
233 cinfo->iobase = of_iomap(node, 0);
234 cinfo->dev = &pdev->dev;
235 pm_runtime_enable(cinfo->dev);
236
237 pm_runtime_get_sync(cinfo->dev);
238 atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
239
240 for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
241 struct device_node *cfg_node;
242 char prop[5];
243 struct dra7_atl_desc *cdesc;
244 struct of_phandle_args clkspec;
245 struct clk *clk;
246 int rc;
247
248 rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
249 NULL, i, &clkspec);
250
251 if (rc) {
252 pr_err("%s: failed to lookup atl clock %d\n", __func__,
253 i);
254 return -EINVAL;
255 }
256
257 clk = of_clk_get_from_provider(&clkspec);
258 if (IS_ERR(clk)) {
259 pr_err("%s: failed to get atl clock %d from provider\n",
260 __func__, i);
261 return PTR_ERR(clk);
262 }
263
264 cdesc = to_atl_desc(__clk_get_hw(clk));
265 cdesc->cinfo = cinfo;
266 cdesc->id = i;
267
268
269 snprintf(prop, sizeof(prop), "atl%u", i);
270 cfg_node = of_get_child_by_name(node, prop);
271 if (cfg_node) {
272 ret = of_property_read_u32(cfg_node, "bws",
273 &cdesc->bws);
274 ret |= of_property_read_u32(cfg_node, "aws",
275 &cdesc->aws);
276 if (!ret) {
277 cdesc->valid = true;
278 atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
279 cdesc->bws);
280 atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
281 cdesc->aws);
282 }
283 of_node_put(cfg_node);
284 }
285
286 cdesc->probed = true;
287
288
289
290
291 if (cdesc->enabled)
292 atl_clk_enable(__clk_get_hw(clk));
293 }
294 pm_runtime_put_sync(cinfo->dev);
295
296 return ret;
297}
298
299static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
300 { .compatible = "ti,dra7-atl", },
301 {},
302};
303
304static struct platform_driver dra7_atl_clk_driver = {
305 .driver = {
306 .name = "dra7-atl",
307 .suppress_bind_attrs = true,
308 .of_match_table = of_dra7_atl_clk_match_tbl,
309 },
310 .probe = of_dra7_atl_clk_probe,
311};
312builtin_platform_driver(dra7_atl_clk_driver);
313
