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10#include <linux/clocksource.h>
11#include <linux/clockchips.h>
12#include <linux/cpu.h>
13#include <linux/delay.h>
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/sched_clock.h>
17#include <linux/io-64-nonatomic-lo-hi.h>
18#include <linux/interrupt.h>
19#include <linux/of_irq.h>
20#include <asm/smp.h>
21#include <asm/sbi.h>
22
23u64 __iomem *riscv_time_cmp;
24u64 __iomem *riscv_time_val;
25
26static inline void mmio_set_timer(u64 val)
27{
28 void __iomem *r;
29
30 r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
31 writeq_relaxed(val, r);
32}
33
34static int riscv_clock_next_event(unsigned long delta,
35 struct clock_event_device *ce)
36{
37 csr_set(CSR_IE, IE_TIE);
38 if (IS_ENABLED(CONFIG_RISCV_SBI))
39 sbi_set_timer(get_cycles64() + delta);
40 else
41 mmio_set_timer(get_cycles64() + delta);
42 return 0;
43}
44
45static unsigned int riscv_clock_event_irq;
46static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
47 .name = "riscv_timer_clockevent",
48 .features = CLOCK_EVT_FEAT_ONESHOT,
49 .rating = 100,
50 .set_next_event = riscv_clock_next_event,
51};
52
53
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55
56
57
58static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
59{
60 return get_cycles64();
61}
62
63static u64 notrace riscv_sched_clock(void)
64{
65 return get_cycles64();
66}
67
68static struct clocksource riscv_clocksource = {
69 .name = "riscv_clocksource",
70 .rating = 300,
71 .mask = CLOCKSOURCE_MASK(64),
72 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
73 .read = riscv_clocksource_rdtime,
74};
75
76static int riscv_timer_starting_cpu(unsigned int cpu)
77{
78 struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
79
80 ce->cpumask = cpumask_of(cpu);
81 ce->irq = riscv_clock_event_irq;
82 clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
83
84 enable_percpu_irq(riscv_clock_event_irq,
85 irq_get_trigger_type(riscv_clock_event_irq));
86 return 0;
87}
88
89static int riscv_timer_dying_cpu(unsigned int cpu)
90{
91 disable_percpu_irq(riscv_clock_event_irq);
92 return 0;
93}
94
95
96static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
97{
98 struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
99
100 csr_clear(CSR_IE, IE_TIE);
101 evdev->event_handler(evdev);
102
103 return IRQ_HANDLED;
104}
105
106static int __init riscv_timer_init_dt(struct device_node *n)
107{
108 int cpuid, hartid, error;
109 struct device_node *child;
110 struct irq_domain *domain;
111
112 hartid = riscv_of_processor_hartid(n);
113 if (hartid < 0) {
114 pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
115 n, hartid);
116 return hartid;
117 }
118
119 cpuid = riscv_hartid_to_cpuid(hartid);
120 if (cpuid < 0) {
121 pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
122 return cpuid;
123 }
124
125 if (cpuid != smp_processor_id())
126 return 0;
127
128 domain = NULL;
129 child = of_get_compatible_child(n, "riscv,cpu-intc");
130 if (!child) {
131 pr_err("Failed to find INTC node [%pOF]\n", n);
132 return -ENODEV;
133 }
134 domain = irq_find_host(child);
135 of_node_put(child);
136 if (!domain) {
137 pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
138 return -ENODEV;
139 }
140
141 riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
142 if (!riscv_clock_event_irq) {
143 pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
144 return -ENODEV;
145 }
146
147 pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
148 __func__, cpuid, hartid);
149 error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
150 if (error) {
151 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
152 error, cpuid);
153 return error;
154 }
155
156 sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
157
158 error = request_percpu_irq(riscv_clock_event_irq,
159 riscv_timer_interrupt,
160 "riscv-timer", &riscv_clock_event);
161 if (error) {
162 pr_err("registering percpu irq failed [%d]\n", error);
163 return error;
164 }
165
166 error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
167 "clockevents/riscv/timer:starting",
168 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
169 if (error)
170 pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
171 error);
172 return error;
173}
174
175TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
176
