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26#include "amdgpu.h"
27#include "amdgpu_gfx.h"
28#include "amdgpu_rlc.h"
29#include "amdgpu_ras.h"
30
31
32#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
33
34
35
36
37
38int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
39 int pipe, int queue)
40{
41 int bit = 0;
42
43 bit += mec * adev->gfx.mec.num_pipe_per_mec
44 * adev->gfx.mec.num_queue_per_pipe;
45 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
46 bit += queue;
47
48 return bit;
49}
50
51void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
52 int *mec, int *pipe, int *queue)
53{
54 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
56 % adev->gfx.mec.num_pipe_per_mec;
57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
58 / adev->gfx.mec.num_pipe_per_mec;
59
60}
61
62bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
63 int mec, int pipe, int queue)
64{
65 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
66 adev->gfx.mec.queue_bitmap);
67}
68
69int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
70 int me, int pipe, int queue)
71{
72 int bit = 0;
73
74 bit += me * adev->gfx.me.num_pipe_per_me
75 * adev->gfx.me.num_queue_per_pipe;
76 bit += pipe * adev->gfx.me.num_queue_per_pipe;
77 bit += queue;
78
79 return bit;
80}
81
82void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
83 int *me, int *pipe, int *queue)
84{
85 *queue = bit % adev->gfx.me.num_queue_per_pipe;
86 *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
87 % adev->gfx.me.num_pipe_per_me;
88 *me = (bit / adev->gfx.me.num_queue_per_pipe)
89 / adev->gfx.me.num_pipe_per_me;
90}
91
92bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
93 int me, int pipe, int queue)
94{
95 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
96 adev->gfx.me.queue_bitmap);
97}
98
99
100
101
102
103
104
105
106
107
108int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
109{
110 int i;
111
112 i = ffs(adev->gfx.scratch.free_mask);
113 if (i != 0 && i <= adev->gfx.scratch.num_reg) {
114 i--;
115 adev->gfx.scratch.free_mask &= ~(1u << i);
116 *reg = adev->gfx.scratch.reg_base + i;
117 return 0;
118 }
119 return -EINVAL;
120}
121
122
123
124
125
126
127
128
129
130void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
131{
132 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
133}
134
135
136
137
138
139
140
141
142
143
144
145void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
146{
147 unsigned se, sh, cu;
148 const char *p;
149
150 memset(mask, 0, sizeof(*mask) * max_se * max_sh);
151
152 if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
153 return;
154
155 p = amdgpu_disable_cu;
156 for (;;) {
157 char *next;
158 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
159 if (ret < 3) {
160 DRM_ERROR("amdgpu: could not parse disable_cu\n");
161 return;
162 }
163
164 if (se < max_se && sh < max_sh && cu < 16) {
165 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
166 mask[se * max_sh + sh] |= 1u << cu;
167 } else {
168 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
169 se, sh, cu);
170 }
171
172 next = strchr(p, ',');
173 if (!next)
174 break;
175 p = next + 1;
176 }
177}
178
179static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
180{
181 if (amdgpu_compute_multipipe != -1) {
182 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
183 amdgpu_compute_multipipe);
184 return amdgpu_compute_multipipe == 1;
185 }
186
187
188
189 if (adev->asic_type == CHIP_POLARIS11)
190 return false;
191
192 return adev->gfx.mec.num_mec > 1;
193}
194
195bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
196 int queue)
197{
198
199 return (queue == 0);
200
201}
202
203void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
204{
205 int i, queue, pipe, mec;
206 bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
207
208
209 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
210 queue = i % adev->gfx.mec.num_queue_per_pipe;
211 pipe = (i / adev->gfx.mec.num_queue_per_pipe)
212 % adev->gfx.mec.num_pipe_per_mec;
213 mec = (i / adev->gfx.mec.num_queue_per_pipe)
214 / adev->gfx.mec.num_pipe_per_mec;
215
216
217 if (mec >= adev->gfx.mec.num_mec)
218 break;
219
220 if (multipipe_policy) {
221
222 if (mec == 0 && queue < 2)
223 set_bit(i, adev->gfx.mec.queue_bitmap);
224 } else {
225
226 if (mec == 0 && pipe == 0)
227 set_bit(i, adev->gfx.mec.queue_bitmap);
228 }
229 }
230
231
232 adev->gfx.num_compute_rings =
233 bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
234
235
236
237 if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS))
238 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
239}
240
241void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
242{
243 int i, queue, me;
244
245 for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
246 queue = i % adev->gfx.me.num_queue_per_pipe;
247 me = (i / adev->gfx.me.num_queue_per_pipe)
248 / adev->gfx.me.num_pipe_per_me;
249
250 if (me >= adev->gfx.me.num_me)
251 break;
252
253
254 if (me == 0 && queue < 1)
255 set_bit(i, adev->gfx.me.queue_bitmap);
256 }
257
258
259 adev->gfx.num_gfx_rings =
260 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
261}
262
263static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
264 struct amdgpu_ring *ring)
265{
266 int queue_bit;
267 int mec, pipe, queue;
268
269 queue_bit = adev->gfx.mec.num_mec
270 * adev->gfx.mec.num_pipe_per_mec
271 * adev->gfx.mec.num_queue_per_pipe;
272
273 while (queue_bit-- >= 0) {
274 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
275 continue;
276
277 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
278
279
280
281
282
283
284 if ((mec == 1 && pipe > 1) || queue != 0)
285 continue;
286
287 ring->me = mec + 1;
288 ring->pipe = pipe;
289 ring->queue = queue;
290
291 return 0;
292 }
293
294 dev_err(adev->dev, "Failed to find a queue for KIQ\n");
295 return -EINVAL;
296}
297
298int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
299 struct amdgpu_ring *ring,
300 struct amdgpu_irq_src *irq)
301{
302 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
303 int r = 0;
304
305 spin_lock_init(&kiq->ring_lock);
306
307 ring->adev = NULL;
308 ring->ring_obj = NULL;
309 ring->use_doorbell = true;
310 ring->doorbell_index = adev->doorbell_index.kiq;
311
312 r = amdgpu_gfx_kiq_acquire(adev, ring);
313 if (r)
314 return r;
315
316 ring->eop_gpu_addr = kiq->eop_gpu_addr;
317 ring->no_scheduler = true;
318 sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
319 r = amdgpu_ring_init(adev, ring, 1024,
320 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
321 AMDGPU_RING_PRIO_DEFAULT);
322 if (r)
323 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
324
325 return r;
326}
327
328void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
329{
330 amdgpu_ring_fini(ring);
331}
332
333void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
334{
335 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
336
337 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
338}
339
340int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
341 unsigned hpd_size)
342{
343 int r;
344 u32 *hpd;
345 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
346
347 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
348 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
349 &kiq->eop_gpu_addr, (void **)&hpd);
350 if (r) {
351 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
352 return r;
353 }
354
355 memset(hpd, 0, hpd_size);
356
357 r = amdgpu_bo_reserve(kiq->eop_obj, true);
358 if (unlikely(r != 0))
359 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
360 amdgpu_bo_kunmap(kiq->eop_obj);
361 amdgpu_bo_unreserve(kiq->eop_obj);
362
363 return 0;
364}
365
366
367int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
368 unsigned mqd_size)
369{
370 struct amdgpu_ring *ring = NULL;
371 int r, i;
372
373
374 ring = &adev->gfx.kiq.ring;
375 if (!ring->mqd_obj) {
376
377
378
379
380
381 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
382 AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
383 &ring->mqd_gpu_addr, &ring->mqd_ptr);
384 if (r) {
385 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
386 return r;
387 }
388
389
390 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
391 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
392 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
393 }
394
395 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
396
397 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
398 ring = &adev->gfx.gfx_ring[i];
399 if (!ring->mqd_obj) {
400 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
401 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
402 &ring->mqd_gpu_addr, &ring->mqd_ptr);
403 if (r) {
404 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
405 return r;
406 }
407
408
409 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
410 if (!adev->gfx.me.mqd_backup[i])
411 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
412 }
413 }
414 }
415
416
417 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
418 ring = &adev->gfx.compute_ring[i];
419 if (!ring->mqd_obj) {
420 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
421 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
422 &ring->mqd_gpu_addr, &ring->mqd_ptr);
423 if (r) {
424 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
425 return r;
426 }
427
428
429 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
430 if (!adev->gfx.mec.mqd_backup[i])
431 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
432 }
433 }
434
435 return 0;
436}
437
438void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
439{
440 struct amdgpu_ring *ring = NULL;
441 int i;
442
443 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
444 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
445 ring = &adev->gfx.gfx_ring[i];
446 kfree(adev->gfx.me.mqd_backup[i]);
447 amdgpu_bo_free_kernel(&ring->mqd_obj,
448 &ring->mqd_gpu_addr,
449 &ring->mqd_ptr);
450 }
451 }
452
453 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
454 ring = &adev->gfx.compute_ring[i];
455 kfree(adev->gfx.mec.mqd_backup[i]);
456 amdgpu_bo_free_kernel(&ring->mqd_obj,
457 &ring->mqd_gpu_addr,
458 &ring->mqd_ptr);
459 }
460
461 ring = &adev->gfx.kiq.ring;
462 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
463 amdgpu_bo_free_kernel(&ring->mqd_obj,
464 &ring->mqd_gpu_addr,
465 &ring->mqd_ptr);
466}
467
468int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
469{
470 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
471 struct amdgpu_ring *kiq_ring = &kiq->ring;
472 int i;
473
474 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
475 return -EINVAL;
476
477 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
478 adev->gfx.num_compute_rings))
479 return -ENOMEM;
480
481 for (i = 0; i < adev->gfx.num_compute_rings; i++)
482 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
483 RESET_QUEUES, 0, 0);
484
485 return amdgpu_ring_test_helper(kiq_ring);
486}
487
488int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
489 int queue_bit)
490{
491 int mec, pipe, queue;
492 int set_resource_bit = 0;
493
494 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
495
496 set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
497
498 return set_resource_bit;
499}
500
501int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
502{
503 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
504 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
505 uint64_t queue_mask = 0;
506 int r, i;
507
508 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
509 return -EINVAL;
510
511 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
512 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
513 continue;
514
515
516
517
518 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
519 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
520 break;
521 }
522
523 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
524 }
525
526 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
527 kiq_ring->queue);
528
529 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
530 adev->gfx.num_compute_rings +
531 kiq->pmf->set_resources_size);
532 if (r) {
533 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
534 return r;
535 }
536
537 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
538 for (i = 0; i < adev->gfx.num_compute_rings; i++)
539 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
540
541 r = amdgpu_ring_test_helper(kiq_ring);
542 if (r)
543 DRM_ERROR("KCQ enable failed\n");
544
545 return r;
546}
547
548
549
550
551
552
553
554
555
556
557
558
559void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
560{
561 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
562 return;
563
564 mutex_lock(&adev->gfx.gfx_off_mutex);
565
566 if (!enable)
567 adev->gfx.gfx_off_req_count++;
568 else if (adev->gfx.gfx_off_req_count > 0)
569 adev->gfx.gfx_off_req_count--;
570
571 if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
572 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
573 } else if (!enable && adev->gfx.gfx_off_state) {
574 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false))
575 adev->gfx.gfx_off_state = false;
576 }
577
578 mutex_unlock(&adev->gfx.gfx_off_mutex);
579}
580
581int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
582{
583 int r;
584 struct ras_fs_if fs_info = {
585 .sysfs_name = "gfx_err_count",
586 };
587 struct ras_ih_if ih_info = {
588 .cb = amdgpu_gfx_process_ras_data_cb,
589 };
590
591 if (!adev->gfx.ras_if) {
592 adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
593 if (!adev->gfx.ras_if)
594 return -ENOMEM;
595 adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
596 adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
597 adev->gfx.ras_if->sub_block_index = 0;
598 strcpy(adev->gfx.ras_if->name, "gfx");
599 }
600 fs_info.head = ih_info.head = *adev->gfx.ras_if;
601
602 r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
603 &fs_info, &ih_info);
604 if (r)
605 goto free;
606
607 if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
608 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
609 if (r)
610 goto late_fini;
611 } else {
612
613 r = 0;
614 goto free;
615 }
616
617 return 0;
618late_fini:
619 amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
620free:
621 kfree(adev->gfx.ras_if);
622 adev->gfx.ras_if = NULL;
623 return r;
624}
625
626void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
627{
628 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
629 adev->gfx.ras_if) {
630 struct ras_common_if *ras_if = adev->gfx.ras_if;
631 struct ras_ih_if ih_info = {
632 .head = *ras_if,
633 .cb = amdgpu_gfx_process_ras_data_cb,
634 };
635
636 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
637 kfree(ras_if);
638 }
639}
640
641int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
642 void *err_data,
643 struct amdgpu_iv_entry *entry)
644{
645
646
647
648
649
650
651 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
652 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
653 if (adev->gfx.funcs->query_ras_error_count)
654 adev->gfx.funcs->query_ras_error_count(adev, err_data);
655 amdgpu_ras_reset_gpu(adev);
656 }
657 return AMDGPU_RAS_SUCCESS;
658}
659
660int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
661 struct amdgpu_irq_src *source,
662 struct amdgpu_iv_entry *entry)
663{
664 struct ras_common_if *ras_if = adev->gfx.ras_if;
665 struct ras_dispatch_if ih_data = {
666 .entry = entry,
667 };
668
669 if (!ras_if)
670 return 0;
671
672 ih_data.head = *ras_if;
673
674 DRM_ERROR("CP ECC ERROR IRQ\n");
675 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
676 return 0;
677}
678
679uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
680{
681 signed long r, cnt = 0;
682 unsigned long flags;
683 uint32_t seq, reg_val_offs = 0, value = 0;
684 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
685 struct amdgpu_ring *ring = &kiq->ring;
686
687 BUG_ON(!ring->funcs->emit_rreg);
688
689 spin_lock_irqsave(&kiq->ring_lock, flags);
690 if (amdgpu_device_wb_get(adev, ®_val_offs)) {
691 pr_err("critical bug! too many kiq readers\n");
692 goto failed_unlock;
693 }
694 amdgpu_ring_alloc(ring, 32);
695 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
696 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
697 if (r)
698 goto failed_undo;
699
700 amdgpu_ring_commit(ring);
701 spin_unlock_irqrestore(&kiq->ring_lock, flags);
702
703 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
704
705
706
707
708
709
710
711
712
713 if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
714 goto failed_kiq_read;
715
716 might_sleep();
717 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
718 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
719 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
720 }
721
722 if (cnt > MAX_KIQ_REG_TRY)
723 goto failed_kiq_read;
724
725 mb();
726 value = adev->wb.wb[reg_val_offs];
727 amdgpu_device_wb_free(adev, reg_val_offs);
728 return value;
729
730failed_undo:
731 amdgpu_ring_undo(ring);
732failed_unlock:
733 spin_unlock_irqrestore(&kiq->ring_lock, flags);
734failed_kiq_read:
735 if (reg_val_offs)
736 amdgpu_device_wb_free(adev, reg_val_offs);
737 pr_err("failed to read reg:%x\n", reg);
738 return ~0;
739}
740
741void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
742{
743 signed long r, cnt = 0;
744 unsigned long flags;
745 uint32_t seq;
746 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
747 struct amdgpu_ring *ring = &kiq->ring;
748
749 BUG_ON(!ring->funcs->emit_wreg);
750
751 spin_lock_irqsave(&kiq->ring_lock, flags);
752 amdgpu_ring_alloc(ring, 32);
753 amdgpu_ring_emit_wreg(ring, reg, v);
754 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
755 if (r)
756 goto failed_undo;
757
758 amdgpu_ring_commit(ring);
759 spin_unlock_irqrestore(&kiq->ring_lock, flags);
760
761 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
762
763
764
765
766
767
768
769
770
771 if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
772 goto failed_kiq_write;
773
774 might_sleep();
775 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
776
777 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
778 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
779 }
780
781 if (cnt > MAX_KIQ_REG_TRY)
782 goto failed_kiq_write;
783
784 return;
785
786failed_undo:
787 amdgpu_ring_undo(ring);
788 spin_unlock_irqrestore(&kiq->ring_lock, flags);
789failed_kiq_write:
790 pr_err("failed to write reg:%x\n", reg);
791}
792