LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2012 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __AMDGPU_UCODE_H__
  24#define __AMDGPU_UCODE_H__
  25
  26#include "amdgpu_socbb.h"
  27
  28struct common_firmware_header {
  29        uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  30        uint32_t header_size_bytes; /* size of just the header in bytes */
  31        uint16_t header_version_major; /* header version */
  32        uint16_t header_version_minor; /* header version */
  33        uint16_t ip_version_major; /* IP version */
  34        uint16_t ip_version_minor; /* IP version */
  35        uint32_t ucode_version;
  36        uint32_t ucode_size_bytes; /* size of ucode in bytes */
  37        uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  38        uint32_t crc32;  /* crc32 checksum of the payload */
  39};
  40
  41/* version_major=1, version_minor=0 */
  42struct mc_firmware_header_v1_0 {
  43        struct common_firmware_header header;
  44        uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  45        uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  46};
  47
  48/* version_major=1, version_minor=0 */
  49struct smc_firmware_header_v1_0 {
  50        struct common_firmware_header header;
  51        uint32_t ucode_start_addr;
  52};
  53
  54/* version_major=2, version_minor=0 */
  55struct smc_firmware_header_v2_0 {
  56        struct smc_firmware_header_v1_0 v1_0;
  57        uint32_t ppt_offset_bytes; /* soft pptable offset */
  58        uint32_t ppt_size_bytes; /* soft pptable size */
  59};
  60
  61struct smc_soft_pptable_entry {
  62        uint32_t id;
  63        uint32_t ppt_offset_bytes;
  64        uint32_t ppt_size_bytes;
  65};
  66
  67/* version_major=2, version_minor=1 */
  68struct smc_firmware_header_v2_1 {
  69        struct smc_firmware_header_v1_0 v1_0;
  70        uint32_t pptable_count;
  71        uint32_t pptable_entry_offset;
  72};
  73
  74/* version_major=1, version_minor=0 */
  75struct psp_firmware_header_v1_0 {
  76        struct common_firmware_header header;
  77        uint32_t ucode_feature_version;
  78        uint32_t sos_offset_bytes;
  79        uint32_t sos_size_bytes;
  80};
  81
  82/* version_major=1, version_minor=1 */
  83struct psp_firmware_header_v1_1 {
  84        struct psp_firmware_header_v1_0 v1_0;
  85        uint32_t toc_header_version;
  86        uint32_t toc_offset_bytes;
  87        uint32_t toc_size_bytes;
  88        uint32_t kdb_header_version;
  89        uint32_t kdb_offset_bytes;
  90        uint32_t kdb_size_bytes;
  91};
  92
  93/* version_major=1, version_minor=2 */
  94struct psp_firmware_header_v1_2 {
  95        struct psp_firmware_header_v1_0 v1_0;
  96        uint32_t reserve[3];
  97        uint32_t kdb_header_version;
  98        uint32_t kdb_offset_bytes;
  99        uint32_t kdb_size_bytes;
 100};
 101
 102/* version_major=1, version_minor=0 */
 103struct ta_firmware_header_v1_0 {
 104        struct common_firmware_header header;
 105        uint32_t ta_xgmi_ucode_version;
 106        uint32_t ta_xgmi_offset_bytes;
 107        uint32_t ta_xgmi_size_bytes;
 108        uint32_t ta_ras_ucode_version;
 109        uint32_t ta_ras_offset_bytes;
 110        uint32_t ta_ras_size_bytes;
 111        uint32_t ta_hdcp_ucode_version;
 112        uint32_t ta_hdcp_offset_bytes;
 113        uint32_t ta_hdcp_size_bytes;
 114        uint32_t ta_dtm_ucode_version;
 115        uint32_t ta_dtm_offset_bytes;
 116        uint32_t ta_dtm_size_bytes;
 117};
 118
 119/* version_major=1, version_minor=0 */
 120struct gfx_firmware_header_v1_0 {
 121        struct common_firmware_header header;
 122        uint32_t ucode_feature_version;
 123        uint32_t jt_offset; /* jt location */
 124        uint32_t jt_size;  /* size of jt */
 125};
 126
 127/* version_major=1, version_minor=0 */
 128struct mes_firmware_header_v1_0 {
 129        struct common_firmware_header header;
 130        uint32_t mes_ucode_version;
 131        uint32_t mes_ucode_size_bytes;
 132        uint32_t mes_ucode_offset_bytes;
 133        uint32_t mes_ucode_data_version;
 134        uint32_t mes_ucode_data_size_bytes;
 135        uint32_t mes_ucode_data_offset_bytes;
 136        uint32_t mes_uc_start_addr_lo;
 137        uint32_t mes_uc_start_addr_hi;
 138        uint32_t mes_data_start_addr_lo;
 139        uint32_t mes_data_start_addr_hi;
 140};
 141
 142/* version_major=1, version_minor=0 */
 143struct rlc_firmware_header_v1_0 {
 144        struct common_firmware_header header;
 145        uint32_t ucode_feature_version;
 146        uint32_t save_and_restore_offset;
 147        uint32_t clear_state_descriptor_offset;
 148        uint32_t avail_scratch_ram_locations;
 149        uint32_t master_pkt_description_offset;
 150};
 151
 152/* version_major=2, version_minor=0 */
 153struct rlc_firmware_header_v2_0 {
 154        struct common_firmware_header header;
 155        uint32_t ucode_feature_version;
 156        uint32_t jt_offset; /* jt location */
 157        uint32_t jt_size;  /* size of jt */
 158        uint32_t save_and_restore_offset;
 159        uint32_t clear_state_descriptor_offset;
 160        uint32_t avail_scratch_ram_locations;
 161        uint32_t reg_restore_list_size;
 162        uint32_t reg_list_format_start;
 163        uint32_t reg_list_format_separate_start;
 164        uint32_t starting_offsets_start;
 165        uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
 166        uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
 167        uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
 168        uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
 169        uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
 170        uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
 171        uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
 172        uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
 173};
 174
 175/* version_major=2, version_minor=1 */
 176struct rlc_firmware_header_v2_1 {
 177        struct rlc_firmware_header_v2_0 v2_0;
 178        uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
 179        uint32_t save_restore_list_cntl_ucode_ver;
 180        uint32_t save_restore_list_cntl_feature_ver;
 181        uint32_t save_restore_list_cntl_size_bytes;
 182        uint32_t save_restore_list_cntl_offset_bytes;
 183        uint32_t save_restore_list_gpm_ucode_ver;
 184        uint32_t save_restore_list_gpm_feature_ver;
 185        uint32_t save_restore_list_gpm_size_bytes;
 186        uint32_t save_restore_list_gpm_offset_bytes;
 187        uint32_t save_restore_list_srm_ucode_ver;
 188        uint32_t save_restore_list_srm_feature_ver;
 189        uint32_t save_restore_list_srm_size_bytes;
 190        uint32_t save_restore_list_srm_offset_bytes;
 191};
 192
 193/* version_major=1, version_minor=0 */
 194struct sdma_firmware_header_v1_0 {
 195        struct common_firmware_header header;
 196        uint32_t ucode_feature_version;
 197        uint32_t ucode_change_version;
 198        uint32_t jt_offset; /* jt location */
 199        uint32_t jt_size; /* size of jt */
 200};
 201
 202/* version_major=1, version_minor=1 */
 203struct sdma_firmware_header_v1_1 {
 204        struct sdma_firmware_header_v1_0 v1_0;
 205        uint32_t digest_size;
 206};
 207
 208/* gpu info payload */
 209struct gpu_info_firmware_v1_0 {
 210        uint32_t gc_num_se;
 211        uint32_t gc_num_cu_per_sh;
 212        uint32_t gc_num_sh_per_se;
 213        uint32_t gc_num_rb_per_se;
 214        uint32_t gc_num_tccs;
 215        uint32_t gc_num_gprs;
 216        uint32_t gc_num_max_gs_thds;
 217        uint32_t gc_gs_table_depth;
 218        uint32_t gc_gsprim_buff_depth;
 219        uint32_t gc_parameter_cache_depth;
 220        uint32_t gc_double_offchip_lds_buffer;
 221        uint32_t gc_wave_size;
 222        uint32_t gc_max_waves_per_simd;
 223        uint32_t gc_max_scratch_slots_per_cu;
 224        uint32_t gc_lds_size;
 225};
 226
 227struct gpu_info_firmware_v1_1 {
 228        struct gpu_info_firmware_v1_0 v1_0;
 229        uint32_t num_sc_per_sh;
 230        uint32_t num_packer_per_sc;
 231};
 232
 233/* gpu info payload
 234 * version_major=1, version_minor=1 */
 235struct gpu_info_firmware_v1_2 {
 236        struct gpu_info_firmware_v1_1 v1_1;
 237        struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
 238};
 239
 240/* version_major=1, version_minor=0 */
 241struct gpu_info_firmware_header_v1_0 {
 242        struct common_firmware_header header;
 243        uint16_t version_major; /* version */
 244        uint16_t version_minor; /* version */
 245};
 246
 247/* version_major=1, version_minor=0 */
 248struct dmcu_firmware_header_v1_0 {
 249        struct common_firmware_header header;
 250        uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
 251        uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
 252};
 253
 254/* version_major=1, version_minor=0 */
 255struct dmcub_firmware_header_v1_0 {
 256        struct common_firmware_header header;
 257        uint32_t inst_const_bytes; /* size of instruction region, in bytes */
 258        uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
 259};
 260
 261/* header is fixed size */
 262union amdgpu_firmware_header {
 263        struct common_firmware_header common;
 264        struct mc_firmware_header_v1_0 mc;
 265        struct smc_firmware_header_v1_0 smc;
 266        struct smc_firmware_header_v2_0 smc_v2_0;
 267        struct psp_firmware_header_v1_0 psp;
 268        struct psp_firmware_header_v1_1 psp_v1_1;
 269        struct ta_firmware_header_v1_0 ta;
 270        struct gfx_firmware_header_v1_0 gfx;
 271        struct rlc_firmware_header_v1_0 rlc;
 272        struct rlc_firmware_header_v2_0 rlc_v2_0;
 273        struct rlc_firmware_header_v2_1 rlc_v2_1;
 274        struct sdma_firmware_header_v1_0 sdma;
 275        struct sdma_firmware_header_v1_1 sdma_v1_1;
 276        struct gpu_info_firmware_header_v1_0 gpu_info;
 277        struct dmcu_firmware_header_v1_0 dmcu;
 278        struct dmcub_firmware_header_v1_0 dmcub;
 279        uint8_t raw[0x100];
 280};
 281
 282/*
 283 * fw loading support
 284 */
 285enum AMDGPU_UCODE_ID {
 286        AMDGPU_UCODE_ID_SDMA0 = 0,
 287        AMDGPU_UCODE_ID_SDMA1,
 288        AMDGPU_UCODE_ID_SDMA2,
 289        AMDGPU_UCODE_ID_SDMA3,
 290        AMDGPU_UCODE_ID_SDMA4,
 291        AMDGPU_UCODE_ID_SDMA5,
 292        AMDGPU_UCODE_ID_SDMA6,
 293        AMDGPU_UCODE_ID_SDMA7,
 294        AMDGPU_UCODE_ID_CP_CE,
 295        AMDGPU_UCODE_ID_CP_PFP,
 296        AMDGPU_UCODE_ID_CP_ME,
 297        AMDGPU_UCODE_ID_CP_MEC1,
 298        AMDGPU_UCODE_ID_CP_MEC1_JT,
 299        AMDGPU_UCODE_ID_CP_MEC2,
 300        AMDGPU_UCODE_ID_CP_MEC2_JT,
 301        AMDGPU_UCODE_ID_CP_MES,
 302        AMDGPU_UCODE_ID_CP_MES_DATA,
 303        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
 304        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
 305        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
 306        AMDGPU_UCODE_ID_RLC_G,
 307        AMDGPU_UCODE_ID_STORAGE,
 308        AMDGPU_UCODE_ID_SMC,
 309        AMDGPU_UCODE_ID_UVD,
 310        AMDGPU_UCODE_ID_UVD1,
 311        AMDGPU_UCODE_ID_VCE,
 312        AMDGPU_UCODE_ID_VCN,
 313        AMDGPU_UCODE_ID_VCN1,
 314        AMDGPU_UCODE_ID_DMCU_ERAM,
 315        AMDGPU_UCODE_ID_DMCU_INTV,
 316        AMDGPU_UCODE_ID_VCN0_RAM,
 317        AMDGPU_UCODE_ID_VCN1_RAM,
 318        AMDGPU_UCODE_ID_DMCUB,
 319        AMDGPU_UCODE_ID_MAXIMUM,
 320};
 321
 322/* engine firmware status */
 323enum AMDGPU_UCODE_STATUS {
 324        AMDGPU_UCODE_STATUS_INVALID,
 325        AMDGPU_UCODE_STATUS_NOT_LOADED,
 326        AMDGPU_UCODE_STATUS_LOADED,
 327};
 328
 329enum amdgpu_firmware_load_type {
 330        AMDGPU_FW_LOAD_DIRECT = 0,
 331        AMDGPU_FW_LOAD_SMU,
 332        AMDGPU_FW_LOAD_PSP,
 333        AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
 334};
 335
 336/* conform to smu_ucode_xfer_cz.h */
 337#define AMDGPU_SDMA0_UCODE_LOADED       0x00000001
 338#define AMDGPU_SDMA1_UCODE_LOADED       0x00000002
 339#define AMDGPU_CPCE_UCODE_LOADED        0x00000004
 340#define AMDGPU_CPPFP_UCODE_LOADED       0x00000008
 341#define AMDGPU_CPME_UCODE_LOADED        0x00000010
 342#define AMDGPU_CPMEC1_UCODE_LOADED      0x00000020
 343#define AMDGPU_CPMEC2_UCODE_LOADED      0x00000040
 344#define AMDGPU_CPRLC_UCODE_LOADED       0x00000100
 345
 346/* amdgpu firmware info */
 347struct amdgpu_firmware_info {
 348        /* ucode ID */
 349        enum AMDGPU_UCODE_ID ucode_id;
 350        /* request_firmware */
 351        const struct firmware *fw;
 352        /* starting mc address */
 353        uint64_t mc_addr;
 354        /* kernel linear address */
 355        void *kaddr;
 356        /* ucode_size_bytes */
 357        uint32_t ucode_size;
 358        /* starting tmr mc address */
 359        uint32_t tmr_mc_addr_lo;
 360        uint32_t tmr_mc_addr_hi;
 361};
 362
 363struct amdgpu_firmware {
 364        struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
 365        enum amdgpu_firmware_load_type load_type;
 366        struct amdgpu_bo *fw_buf;
 367        unsigned int fw_size;
 368        unsigned int max_ucodes;
 369        /* firmwares are loaded by psp instead of smu from vega10 */
 370        const struct amdgpu_psp_funcs *funcs;
 371        struct amdgpu_bo *rbuf;
 372        struct mutex mutex;
 373
 374        /* gpu info firmware data pointer */
 375        const struct firmware *gpu_info_fw;
 376
 377        void *fw_buf_ptr;
 378        uint64_t fw_buf_mc;
 379};
 380
 381void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 382void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 383void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 384void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 385void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 386void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
 387void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
 388int amdgpu_ucode_validate(const struct firmware *fw);
 389bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 390                                uint16_t hdr_major, uint16_t hdr_minor);
 391
 392int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 393int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
 394int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
 395void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
 396void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
 397
 398enum amdgpu_firmware_load_type
 399amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
 400
 401#endif
 402