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22#ifndef __AMDGPU_XGMI_H__
23#define __AMDGPU_XGMI_H__
24
25#include <drm/task_barrier.h>
26#include "amdgpu_psp.h"
27
28
29struct amdgpu_hive_info {
30 uint64_t hive_id;
31 struct list_head device_list;
32 int number_devices;
33 struct mutex hive_lock, reset_lock;
34 struct kobject *kobj;
35 struct device_attribute dev_attr;
36 struct amdgpu_device *adev;
37 int hi_req_count;
38 struct amdgpu_device *hi_req_gpu;
39 struct task_barrier tb;
40 enum {
41 AMDGPU_XGMI_PSTATE_MIN,
42 AMDGPU_XGMI_PSTATE_MAX_VEGA20,
43 AMDGPU_XGMI_PSTATE_UNKNOWN
44 } pstate;
45};
46
47struct amdgpu_pcs_ras_field {
48 const char *err_name;
49 uint32_t pcs_err_mask;
50 uint32_t pcs_err_shift;
51};
52
53struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock);
54int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
55int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
56int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
57int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
58int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
59 struct amdgpu_device *peer_adev);
60int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev);
61void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev);
62uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
63 uint64_t addr);
64int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
65 void *ras_error_status);
66void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev);
67
68static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
69 struct amdgpu_device *bo_adev)
70{
71 return (adev != bo_adev &&
72 adev->gmc.xgmi.hive_id &&
73 adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
74}
75
76#endif
77