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31#include <linux/export.h>
32#include <linux/pci.h>
33
34#include <drm/drm_atomic.h>
35#include <drm/drm_atomic_helper.h>
36#include <drm/drm_atomic_state_helper.h>
37#include <drm/drm_crtc.h>
38#include <drm/drm_crtc_helper.h>
39#include <drm/drm_fourcc.h>
40#include <drm/drm_gem_vram_helper.h>
41#include <drm/drm_plane_helper.h>
42#include <drm/drm_probe_helper.h>
43#include <drm/drm_simple_kms_helper.h>
44
45#include "ast_drv.h"
46#include "ast_tables.h"
47
48static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
49static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
50static int ast_cursor_move(struct drm_crtc *crtc,
51 int x, int y);
52
53
54static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height);
55static int ast_cursor_update(void *dst, void *src, unsigned int width,
56 unsigned int height);
57static void ast_cursor_set_base(struct ast_private *ast, u64 address);
58static int ast_cursor_move(struct drm_crtc *crtc,
59 int x, int y);
60
61static inline void ast_load_palette_index(struct ast_private *ast,
62 u8 index, u8 red, u8 green,
63 u8 blue)
64{
65 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
66 ast_io_read8(ast, AST_IO_SEQ_PORT);
67 ast_io_write8(ast, AST_IO_DAC_DATA, red);
68 ast_io_read8(ast, AST_IO_SEQ_PORT);
69 ast_io_write8(ast, AST_IO_DAC_DATA, green);
70 ast_io_read8(ast, AST_IO_SEQ_PORT);
71 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
72 ast_io_read8(ast, AST_IO_SEQ_PORT);
73}
74
75static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
76{
77 u16 *r, *g, *b;
78 int i;
79
80 if (!crtc->enabled)
81 return;
82
83 r = crtc->gamma_store;
84 g = r + crtc->gamma_size;
85 b = g + crtc->gamma_size;
86
87 for (i = 0; i < 256; i++)
88 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
89}
90
91static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
92 const struct drm_display_mode *mode,
93 struct drm_display_mode *adjusted_mode,
94 struct ast_vbios_mode_info *vbios_mode)
95{
96 u32 refresh_rate_index = 0, refresh_rate;
97 const struct ast_vbios_enhtable *best = NULL;
98 u32 hborder, vborder;
99 bool check_sync;
100
101 switch (format->cpp[0] * 8) {
102 case 8:
103 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
104 break;
105 case 16:
106 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
107 break;
108 case 24:
109 case 32:
110 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
111 break;
112 default:
113 return false;
114 }
115
116 switch (mode->crtc_hdisplay) {
117 case 640:
118 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
119 break;
120 case 800:
121 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
122 break;
123 case 1024:
124 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
125 break;
126 case 1280:
127 if (mode->crtc_vdisplay == 800)
128 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
129 else
130 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
131 break;
132 case 1360:
133 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
134 break;
135 case 1440:
136 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
137 break;
138 case 1600:
139 if (mode->crtc_vdisplay == 900)
140 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
141 else
142 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
143 break;
144 case 1680:
145 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
146 break;
147 case 1920:
148 if (mode->crtc_vdisplay == 1080)
149 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
150 else
151 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
152 break;
153 default:
154 return false;
155 }
156
157 refresh_rate = drm_mode_vrefresh(mode);
158 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
159
160 while (1) {
161 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
162
163 while (loop->refresh_rate != 0xff) {
164 if ((check_sync) &&
165 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
166 (loop->flags & PVSync)) ||
167 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
168 (loop->flags & NVSync)) ||
169 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
170 (loop->flags & PHSync)) ||
171 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
172 (loop->flags & NHSync)))) {
173 loop++;
174 continue;
175 }
176 if (loop->refresh_rate <= refresh_rate
177 && (!best || loop->refresh_rate > best->refresh_rate))
178 best = loop;
179 loop++;
180 }
181 if (best || !check_sync)
182 break;
183 check_sync = 0;
184 }
185
186 if (best)
187 vbios_mode->enh_table = best;
188
189 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
190 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
191
192 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
193 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
194 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
195 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
196 vbios_mode->enh_table->hfp;
197 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
198 vbios_mode->enh_table->hfp +
199 vbios_mode->enh_table->hsync);
200
201 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
202 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
203 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
204 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
205 vbios_mode->enh_table->vfp;
206 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
207 vbios_mode->enh_table->vfp +
208 vbios_mode->enh_table->vsync);
209
210 return true;
211}
212
213static void ast_set_vbios_color_reg(struct ast_private *ast,
214 const struct drm_format_info *format,
215 const struct ast_vbios_mode_info *vbios_mode)
216{
217 u32 color_index;
218
219 switch (format->cpp[0]) {
220 case 1:
221 color_index = VGAModeIndex - 1;
222 break;
223 case 2:
224 color_index = HiCModeIndex;
225 break;
226 case 3:
227 case 4:
228 color_index = TrueCModeIndex;
229 break;
230 default:
231 return;
232 }
233
234 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
235
236 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
237
238 if (vbios_mode->enh_table->flags & NewModeInfo) {
239 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
240 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
241 }
242}
243
244static void ast_set_vbios_mode_reg(struct ast_private *ast,
245 const struct drm_display_mode *adjusted_mode,
246 const struct ast_vbios_mode_info *vbios_mode)
247{
248 u32 refresh_rate_index, mode_id;
249
250 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
251 mode_id = vbios_mode->enh_table->mode_id;
252
253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
255
256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
257
258 if (vbios_mode->enh_table->flags & NewModeInfo) {
259 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
260 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
261 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
262 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
263 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
264 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
265 }
266}
267
268static void ast_set_std_reg(struct ast_private *ast,
269 struct drm_display_mode *mode,
270 struct ast_vbios_mode_info *vbios_mode)
271{
272 const struct ast_vbios_stdtable *stdtable;
273 u32 i;
274 u8 jreg;
275
276 stdtable = vbios_mode->std_table;
277
278 jreg = stdtable->misc;
279 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
280
281
282 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
283 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
284 for (i = 1; i < 4; i++) {
285 jreg = stdtable->seq[i];
286 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
287 }
288
289
290 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
291 for (i = 0; i < 12; i++)
292 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
293 for (i = 14; i < 19; i++)
294 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
295 for (i = 20; i < 25; i++)
296 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
297
298
299 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
300 for (i = 0; i < 20; i++) {
301 jreg = stdtable->ar[i];
302 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
303 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
304 }
305 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
306 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
307
308 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
309 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
310
311
312 for (i = 0; i < 9; i++)
313 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
314}
315
316static void ast_set_crtc_reg(struct ast_private *ast,
317 struct drm_display_mode *mode,
318 struct ast_vbios_mode_info *vbios_mode)
319{
320 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
321 u16 temp, precache = 0;
322
323 if ((ast->chip == AST2500) &&
324 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
325 precache = 40;
326
327 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
328
329 temp = (mode->crtc_htotal >> 3) - 5;
330 if (temp & 0x100)
331 jregAC |= 0x01;
332 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
333
334 temp = (mode->crtc_hdisplay >> 3) - 1;
335 if (temp & 0x100)
336 jregAC |= 0x04;
337 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
338
339 temp = (mode->crtc_hblank_start >> 3) - 1;
340 if (temp & 0x100)
341 jregAC |= 0x10;
342 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
343
344 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
345 if (temp & 0x20)
346 jreg05 |= 0x80;
347 if (temp & 0x40)
348 jregAD |= 0x01;
349 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
350
351 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
352 if (temp & 0x100)
353 jregAC |= 0x40;
354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
355
356 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
357 if (temp & 0x20)
358 jregAD |= 0x04;
359 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
360
361 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
363
364
365 temp = (mode->crtc_vtotal) - 2;
366 if (temp & 0x100)
367 jreg07 |= 0x01;
368 if (temp & 0x200)
369 jreg07 |= 0x20;
370 if (temp & 0x400)
371 jregAE |= 0x01;
372 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
373
374 temp = (mode->crtc_vsync_start) - 1;
375 if (temp & 0x100)
376 jreg07 |= 0x04;
377 if (temp & 0x200)
378 jreg07 |= 0x80;
379 if (temp & 0x400)
380 jregAE |= 0x08;
381 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
382
383 temp = (mode->crtc_vsync_end - 1) & 0x3f;
384 if (temp & 0x10)
385 jregAE |= 0x20;
386 if (temp & 0x20)
387 jregAE |= 0x40;
388 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
389
390 temp = mode->crtc_vdisplay - 1;
391 if (temp & 0x100)
392 jreg07 |= 0x02;
393 if (temp & 0x200)
394 jreg07 |= 0x40;
395 if (temp & 0x400)
396 jregAE |= 0x02;
397 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
398
399 temp = mode->crtc_vblank_start - 1;
400 if (temp & 0x100)
401 jreg07 |= 0x08;
402 if (temp & 0x200)
403 jreg09 |= 0x20;
404 if (temp & 0x400)
405 jregAE |= 0x04;
406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
407
408 temp = mode->crtc_vblank_end - 1;
409 if (temp & 0x100)
410 jregAE |= 0x10;
411 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
412
413 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
415 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
416
417 if (precache)
418 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
419 else
420 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
421
422 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
423}
424
425static void ast_set_offset_reg(struct ast_private *ast,
426 struct drm_framebuffer *fb)
427{
428 u16 offset;
429
430 offset = fb->pitches[0] >> 3;
431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
432 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
433}
434
435static void ast_set_dclk_reg(struct ast_private *ast,
436 struct drm_display_mode *mode,
437 struct ast_vbios_mode_info *vbios_mode)
438{
439 const struct ast_vbios_dclk_info *clk_info;
440
441 if (ast->chip == AST2500)
442 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
443 else
444 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
445
446 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
447 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
448 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
449 (clk_info->param3 & 0xc0) |
450 ((clk_info->param3 & 0x3) << 4));
451}
452
453static void ast_set_color_reg(struct ast_private *ast,
454 const struct drm_format_info *format)
455{
456 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
457
458 switch (format->cpp[0] * 8) {
459 case 8:
460 jregA0 = 0x70;
461 jregA3 = 0x01;
462 jregA8 = 0x00;
463 break;
464 case 15:
465 case 16:
466 jregA0 = 0x70;
467 jregA3 = 0x04;
468 jregA8 = 0x02;
469 break;
470 case 32:
471 jregA0 = 0x70;
472 jregA3 = 0x08;
473 jregA8 = 0x02;
474 break;
475 }
476
477 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
478 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
479 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
480}
481
482static void ast_set_crtthd_reg(struct ast_private *ast)
483{
484
485 if (ast->chip == AST2300 || ast->chip == AST2400 ||
486 ast->chip == AST2500) {
487 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
488 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
489 } else if (ast->chip == AST2100 ||
490 ast->chip == AST1100 ||
491 ast->chip == AST2200 ||
492 ast->chip == AST2150) {
493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
494 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
495 } else {
496 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
497 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
498 }
499}
500
501static void ast_set_sync_reg(struct ast_private *ast,
502 struct drm_display_mode *mode,
503 struct ast_vbios_mode_info *vbios_mode)
504{
505 u8 jreg;
506
507 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
508 jreg &= ~0xC0;
509 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
510 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
511 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
512}
513
514static void ast_set_start_address_crt1(struct ast_private *ast,
515 unsigned offset)
516{
517 u32 addr;
518
519 addr = offset >> 2;
520 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
521 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
522 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
523
524}
525
526
527
528
529
530static const uint32_t ast_primary_plane_formats[] = {
531 DRM_FORMAT_XRGB8888,
532 DRM_FORMAT_RGB565,
533 DRM_FORMAT_C8,
534};
535
536static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
537 struct drm_plane_state *state)
538{
539 struct drm_crtc_state *crtc_state;
540 struct ast_crtc_state *ast_crtc_state;
541 int ret;
542
543 if (!state->crtc)
544 return 0;
545
546 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
547
548 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
549 DRM_PLANE_HELPER_NO_SCALING,
550 DRM_PLANE_HELPER_NO_SCALING,
551 false, true);
552 if (ret)
553 return ret;
554
555 if (!state->visible)
556 return 0;
557
558 ast_crtc_state = to_ast_crtc_state(crtc_state);
559
560 ast_crtc_state->format = state->fb->format;
561
562 return 0;
563}
564
565static void
566ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
567 struct drm_plane_state *old_state)
568{
569 struct ast_private *ast = plane->dev->dev_private;
570 struct drm_plane_state *state = plane->state;
571 struct drm_gem_vram_object *gbo;
572 s64 gpu_addr;
573
574 gbo = drm_gem_vram_of_gem(state->fb->obj[0]);
575 gpu_addr = drm_gem_vram_offset(gbo);
576 if (WARN_ON_ONCE(gpu_addr < 0))
577 return;
578
579 ast_set_offset_reg(ast, state->fb);
580 ast_set_start_address_crt1(ast, (u32)gpu_addr);
581
582 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
583}
584
585static void
586ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
587 struct drm_plane_state *old_state)
588{
589 struct ast_private *ast = plane->dev->dev_private;
590
591 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
592}
593
594static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
595 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb,
596 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb,
597 .atomic_check = ast_primary_plane_helper_atomic_check,
598 .atomic_update = ast_primary_plane_helper_atomic_update,
599 .atomic_disable = ast_primary_plane_helper_atomic_disable,
600};
601
602static const struct drm_plane_funcs ast_primary_plane_funcs = {
603 .update_plane = drm_atomic_helper_update_plane,
604 .disable_plane = drm_atomic_helper_disable_plane,
605 .destroy = drm_plane_cleanup,
606 .reset = drm_atomic_helper_plane_reset,
607 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
608 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
609};
610
611
612
613
614
615static const uint32_t ast_cursor_plane_formats[] = {
616 DRM_FORMAT_ARGB8888,
617};
618
619static int
620ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane,
621 struct drm_plane_state *new_state)
622{
623 struct drm_framebuffer *fb = new_state->fb;
624 struct drm_crtc *crtc = new_state->crtc;
625 struct drm_gem_vram_object *gbo;
626 struct ast_private *ast;
627 int ret;
628 void *src, *dst;
629
630 if (!crtc || !fb)
631 return 0;
632
633 if (WARN_ON_ONCE(fb->width > AST_MAX_HWC_WIDTH) ||
634 WARN_ON_ONCE(fb->height > AST_MAX_HWC_HEIGHT))
635 return -EINVAL;
636
637 ast = crtc->dev->dev_private;
638
639 gbo = drm_gem_vram_of_gem(fb->obj[0]);
640 src = drm_gem_vram_vmap(gbo);
641 if (IS_ERR(src)) {
642 ret = PTR_ERR(src);
643 goto err_drm_gem_vram_unpin;
644 }
645
646 dst = drm_gem_vram_vmap(ast->cursor.gbo[ast->cursor.next_index]);
647 if (IS_ERR(dst)) {
648 ret = PTR_ERR(dst);
649 goto err_drm_gem_vram_vunmap_src;
650 }
651
652 ret = ast_cursor_update(dst, src, fb->width, fb->height);
653 if (ret)
654 goto err_drm_gem_vram_vunmap_dst;
655
656
657
658
659
660 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst);
661 drm_gem_vram_vunmap(gbo, src);
662
663 return 0;
664
665err_drm_gem_vram_vunmap_dst:
666 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst);
667err_drm_gem_vram_vunmap_src:
668 drm_gem_vram_vunmap(gbo, src);
669err_drm_gem_vram_unpin:
670 drm_gem_vram_unpin(gbo);
671 return ret;
672}
673
674static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
675 struct drm_plane_state *state)
676{
677 struct drm_framebuffer *fb = state->fb;
678 struct drm_crtc_state *crtc_state;
679 int ret;
680
681 if (!state->crtc)
682 return 0;
683
684 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
685
686 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
687 DRM_PLANE_HELPER_NO_SCALING,
688 DRM_PLANE_HELPER_NO_SCALING,
689 true, true);
690 if (ret)
691 return ret;
692
693 if (!state->visible)
694 return 0;
695
696 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
697 return -EINVAL;
698
699 return 0;
700}
701
702static void
703ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
704 struct drm_plane_state *old_state)
705{
706 struct drm_plane_state *state = plane->state;
707 struct drm_crtc *crtc = state->crtc;
708 struct drm_framebuffer *fb = state->fb;
709 struct ast_private *ast = plane->dev->dev_private;
710 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
711 struct drm_gem_vram_object *gbo;
712 s64 off;
713 u8 jreg;
714
715 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - fb->width;
716 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - fb->height;
717
718 if (state->fb != old_state->fb) {
719
720 gbo = ast->cursor.gbo[ast->cursor.next_index];
721 off = drm_gem_vram_offset(gbo);
722 if (WARN_ON_ONCE(off < 0))
723 return;
724 ast_cursor_set_base(ast, off);
725
726 ++ast->cursor.next_index;
727 ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo);
728 }
729
730 ast_cursor_move(crtc, state->crtc_x, state->crtc_y);
731
732 jreg = 0x2;
733
734 jreg |= 1;
735 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
736}
737
738static void
739ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
740 struct drm_plane_state *old_state)
741{
742 struct ast_private *ast = plane->dev->dev_private;
743
744 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
745}
746
747static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
748 .prepare_fb = ast_cursor_plane_helper_prepare_fb,
749 .cleanup_fb = NULL,
750 .atomic_check = ast_cursor_plane_helper_atomic_check,
751 .atomic_update = ast_cursor_plane_helper_atomic_update,
752 .atomic_disable = ast_cursor_plane_helper_atomic_disable,
753};
754
755static const struct drm_plane_funcs ast_cursor_plane_funcs = {
756 .update_plane = drm_atomic_helper_update_plane,
757 .disable_plane = drm_atomic_helper_disable_plane,
758 .destroy = drm_plane_cleanup,
759 .reset = drm_atomic_helper_plane_reset,
760 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
761 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
762};
763
764
765
766
767
768static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
769{
770 struct ast_private *ast = crtc->dev->dev_private;
771
772 if (ast->chip == AST1180)
773 return;
774
775
776
777
778 switch (mode) {
779 case DRM_MODE_DPMS_ON:
780 case DRM_MODE_DPMS_STANDBY:
781 case DRM_MODE_DPMS_SUSPEND:
782 if (ast->tx_chip_type == AST_TX_DP501)
783 ast_set_dp501_video_output(crtc->dev, 1);
784 ast_crtc_load_lut(ast, crtc);
785 break;
786 case DRM_MODE_DPMS_OFF:
787 if (ast->tx_chip_type == AST_TX_DP501)
788 ast_set_dp501_video_output(crtc->dev, 0);
789 break;
790 }
791}
792
793static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
794 struct drm_crtc_state *state)
795{
796 struct ast_private *ast = crtc->dev->dev_private;
797 struct ast_crtc_state *ast_state;
798 const struct drm_format_info *format;
799 bool succ;
800
801 if (ast->chip == AST1180) {
802 DRM_ERROR("AST 1180 modesetting not supported\n");
803 return -EINVAL;
804 }
805
806 if (!state->enable)
807 return 0;
808
809 ast_state = to_ast_crtc_state(state);
810
811 format = ast_state->format;
812 if (!format)
813 return 0;
814
815 succ = ast_get_vbios_mode_info(format, &state->mode,
816 &state->adjusted_mode,
817 &ast_state->vbios_mode_info);
818 if (!succ)
819 return -EINVAL;
820
821 return 0;
822}
823
824static void ast_crtc_helper_atomic_begin(struct drm_crtc *crtc,
825 struct drm_crtc_state *old_crtc_state)
826{
827 struct ast_private *ast = crtc->dev->dev_private;
828
829 ast_open_key(ast);
830}
831
832static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
833 struct drm_crtc_state *old_crtc_state)
834{
835 struct drm_device *dev = crtc->dev;
836 struct ast_private *ast = dev->dev_private;
837 struct ast_crtc_state *ast_state;
838 const struct drm_format_info *format;
839 struct ast_vbios_mode_info *vbios_mode_info;
840 struct drm_display_mode *adjusted_mode;
841
842 ast_state = to_ast_crtc_state(crtc->state);
843
844 format = ast_state->format;
845 if (!format)
846 return;
847
848 vbios_mode_info = &ast_state->vbios_mode_info;
849
850 ast_set_color_reg(ast, format);
851 ast_set_vbios_color_reg(ast, format, vbios_mode_info);
852
853 if (!crtc->state->mode_changed)
854 return;
855
856 adjusted_mode = &crtc->state->adjusted_mode;
857
858 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
859 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
860 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
861 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
862 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
863 ast_set_crtthd_reg(ast);
864 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
865}
866
867static void
868ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
869 struct drm_crtc_state *old_crtc_state)
870{
871 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
872}
873
874static void
875ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
876 struct drm_crtc_state *old_crtc_state)
877{
878 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
879}
880
881static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
882 .atomic_check = ast_crtc_helper_atomic_check,
883 .atomic_begin = ast_crtc_helper_atomic_begin,
884 .atomic_flush = ast_crtc_helper_atomic_flush,
885 .atomic_enable = ast_crtc_helper_atomic_enable,
886 .atomic_disable = ast_crtc_helper_atomic_disable,
887};
888
889static void ast_crtc_reset(struct drm_crtc *crtc)
890{
891 struct ast_crtc_state *ast_state =
892 kzalloc(sizeof(*ast_state), GFP_KERNEL);
893
894 if (crtc->state)
895 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
896
897 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
898}
899
900static void ast_crtc_destroy(struct drm_crtc *crtc)
901{
902 drm_crtc_cleanup(crtc);
903 kfree(crtc);
904}
905
906static struct drm_crtc_state *
907ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
908{
909 struct ast_crtc_state *new_ast_state, *ast_state;
910
911 if (WARN_ON(!crtc->state))
912 return NULL;
913
914 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
915 if (!new_ast_state)
916 return NULL;
917 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
918
919 ast_state = to_ast_crtc_state(crtc->state);
920
921 new_ast_state->format = ast_state->format;
922 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
923 sizeof(new_ast_state->vbios_mode_info));
924
925 return &new_ast_state->base;
926}
927
928static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
929 struct drm_crtc_state *state)
930{
931 struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
932
933 __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
934 kfree(ast_state);
935}
936
937static const struct drm_crtc_funcs ast_crtc_funcs = {
938 .reset = ast_crtc_reset,
939 .gamma_set = drm_atomic_helper_legacy_gamma_set,
940 .destroy = ast_crtc_destroy,
941 .set_config = drm_atomic_helper_set_config,
942 .page_flip = drm_atomic_helper_page_flip,
943 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
944 .atomic_destroy_state = ast_crtc_atomic_destroy_state,
945};
946
947static int ast_crtc_init(struct drm_device *dev)
948{
949 struct ast_private *ast = dev->dev_private;
950 struct ast_crtc *crtc;
951 int ret;
952
953 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
954 if (!crtc)
955 return -ENOMEM;
956
957 ret = drm_crtc_init_with_planes(dev, &crtc->base, &ast->primary_plane,
958 &ast->cursor_plane, &ast_crtc_funcs,
959 NULL);
960 if (ret)
961 goto err_kfree;
962
963 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
964 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
965 return 0;
966
967err_kfree:
968 kfree(crtc);
969 return ret;
970}
971
972
973
974
975
976static int ast_encoder_init(struct drm_device *dev)
977{
978 struct ast_private *ast = dev->dev_private;
979 struct drm_encoder *encoder = &ast->encoder;
980 int ret;
981
982 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
983 if (ret)
984 return ret;
985
986 encoder->possible_crtcs = 1;
987
988 return 0;
989}
990
991
992
993
994
995static int ast_get_modes(struct drm_connector *connector)
996{
997 struct ast_connector *ast_connector = to_ast_connector(connector);
998 struct ast_private *ast = connector->dev->dev_private;
999 struct edid *edid;
1000 int ret;
1001 bool flags = false;
1002 if (ast->tx_chip_type == AST_TX_DP501) {
1003 ast->dp501_maxclk = 0xff;
1004 edid = kmalloc(128, GFP_KERNEL);
1005 if (!edid)
1006 return -ENOMEM;
1007
1008 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1009 if (flags)
1010 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1011 else
1012 kfree(edid);
1013 }
1014 if (!flags)
1015 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1016 if (edid) {
1017 drm_connector_update_edid_property(&ast_connector->base, edid);
1018 ret = drm_add_edid_modes(connector, edid);
1019 kfree(edid);
1020 return ret;
1021 } else
1022 drm_connector_update_edid_property(&ast_connector->base, NULL);
1023 return 0;
1024}
1025
1026static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1027 struct drm_display_mode *mode)
1028{
1029 struct ast_private *ast = connector->dev->dev_private;
1030 int flags = MODE_NOMODE;
1031 uint32_t jtemp;
1032
1033 if (ast->support_wide_screen) {
1034 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1035 return MODE_OK;
1036 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1037 return MODE_OK;
1038 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1039 return MODE_OK;
1040 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1041 return MODE_OK;
1042 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1043 return MODE_OK;
1044
1045 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1046 (ast->chip == AST2300) || (ast->chip == AST2400) ||
1047 (ast->chip == AST2500) || (ast->chip == AST1180)) {
1048 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1049 return MODE_OK;
1050
1051 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1052 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1053 if (jtemp & 0x01)
1054 return MODE_NOMODE;
1055 else
1056 return MODE_OK;
1057 }
1058 }
1059 }
1060 switch (mode->hdisplay) {
1061 case 640:
1062 if (mode->vdisplay == 480) flags = MODE_OK;
1063 break;
1064 case 800:
1065 if (mode->vdisplay == 600) flags = MODE_OK;
1066 break;
1067 case 1024:
1068 if (mode->vdisplay == 768) flags = MODE_OK;
1069 break;
1070 case 1280:
1071 if (mode->vdisplay == 1024) flags = MODE_OK;
1072 break;
1073 case 1600:
1074 if (mode->vdisplay == 1200) flags = MODE_OK;
1075 break;
1076 default:
1077 return flags;
1078 }
1079
1080 return flags;
1081}
1082
1083static void ast_connector_destroy(struct drm_connector *connector)
1084{
1085 struct ast_connector *ast_connector = to_ast_connector(connector);
1086 ast_i2c_destroy(ast_connector->i2c);
1087 drm_connector_cleanup(connector);
1088 kfree(connector);
1089}
1090
1091static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1092 .get_modes = ast_get_modes,
1093 .mode_valid = ast_mode_valid,
1094};
1095
1096static const struct drm_connector_funcs ast_connector_funcs = {
1097 .reset = drm_atomic_helper_connector_reset,
1098 .fill_modes = drm_helper_probe_single_connector_modes,
1099 .destroy = ast_connector_destroy,
1100 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1101 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1102};
1103
1104static int ast_connector_init(struct drm_device *dev)
1105{
1106 struct ast_connector *ast_connector;
1107 struct drm_connector *connector;
1108 struct drm_encoder *encoder;
1109
1110 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
1111 if (!ast_connector)
1112 return -ENOMEM;
1113
1114 connector = &ast_connector->base;
1115 ast_connector->i2c = ast_i2c_create(dev);
1116 if (!ast_connector->i2c)
1117 DRM_ERROR("failed to add ddc bus for connector\n");
1118
1119 drm_connector_init_with_ddc(dev, connector,
1120 &ast_connector_funcs,
1121 DRM_MODE_CONNECTOR_VGA,
1122 &ast_connector->i2c->adapter);
1123
1124 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1125
1126 connector->interlace_allowed = 0;
1127 connector->doublescan_allowed = 0;
1128
1129 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1130
1131 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
1132 drm_connector_attach_encoder(connector, encoder);
1133
1134 return 0;
1135}
1136
1137
1138static int ast_cursor_init(struct drm_device *dev)
1139{
1140 struct ast_private *ast = dev->dev_private;
1141 size_t size, i;
1142 struct drm_gem_vram_object *gbo;
1143 int ret;
1144
1145 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
1146
1147 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
1148 gbo = drm_gem_vram_create(dev, size, 0);
1149 if (IS_ERR(gbo)) {
1150 ret = PTR_ERR(gbo);
1151 goto err_drm_gem_vram_put;
1152 }
1153 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
1154 DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
1155 if (ret) {
1156 drm_gem_vram_put(gbo);
1157 goto err_drm_gem_vram_put;
1158 }
1159
1160 ast->cursor.gbo[i] = gbo;
1161 }
1162
1163 return 0;
1164
1165err_drm_gem_vram_put:
1166 while (i) {
1167 --i;
1168 gbo = ast->cursor.gbo[i];
1169 drm_gem_vram_unpin(gbo);
1170 drm_gem_vram_put(gbo);
1171 ast->cursor.gbo[i] = NULL;
1172 }
1173 return ret;
1174}
1175
1176static void ast_cursor_fini(struct drm_device *dev)
1177{
1178 struct ast_private *ast = dev->dev_private;
1179 size_t i;
1180 struct drm_gem_vram_object *gbo;
1181
1182 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
1183 gbo = ast->cursor.gbo[i];
1184 drm_gem_vram_unpin(gbo);
1185 drm_gem_vram_put(gbo);
1186 }
1187}
1188
1189int ast_mode_init(struct drm_device *dev)
1190{
1191 struct ast_private *ast = dev->dev_private;
1192 int ret;
1193
1194 memset(&ast->primary_plane, 0, sizeof(ast->primary_plane));
1195 ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01,
1196 &ast_primary_plane_funcs,
1197 ast_primary_plane_formats,
1198 ARRAY_SIZE(ast_primary_plane_formats),
1199 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1200 if (ret) {
1201 DRM_ERROR("ast: drm_universal_plane_init() failed: %d\n", ret);
1202 return ret;
1203 }
1204 drm_plane_helper_add(&ast->primary_plane,
1205 &ast_primary_plane_helper_funcs);
1206
1207 ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01,
1208 &ast_cursor_plane_funcs,
1209 ast_cursor_plane_formats,
1210 ARRAY_SIZE(ast_cursor_plane_formats),
1211 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
1212 if (ret) {
1213 DRM_ERROR("drm_universal_plane_failed(): %d\n", ret);
1214 return ret;
1215 }
1216 drm_plane_helper_add(&ast->cursor_plane,
1217 &ast_cursor_plane_helper_funcs);
1218
1219 ast_cursor_init(dev);
1220 ast_crtc_init(dev);
1221 ast_encoder_init(dev);
1222 ast_connector_init(dev);
1223
1224 return 0;
1225}
1226
1227void ast_mode_fini(struct drm_device *dev)
1228{
1229 ast_cursor_fini(dev);
1230}
1231
1232static int get_clock(void *i2c_priv)
1233{
1234 struct ast_i2c_chan *i2c = i2c_priv;
1235 struct ast_private *ast = i2c->dev->dev_private;
1236 uint32_t val, val2, count, pass;
1237
1238 count = 0;
1239 pass = 0;
1240 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1241 do {
1242 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1243 if (val == val2) {
1244 pass++;
1245 } else {
1246 pass = 0;
1247 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1248 }
1249 } while ((pass < 5) && (count++ < 0x10000));
1250
1251 return val & 1 ? 1 : 0;
1252}
1253
1254static int get_data(void *i2c_priv)
1255{
1256 struct ast_i2c_chan *i2c = i2c_priv;
1257 struct ast_private *ast = i2c->dev->dev_private;
1258 uint32_t val, val2, count, pass;
1259
1260 count = 0;
1261 pass = 0;
1262 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1263 do {
1264 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1265 if (val == val2) {
1266 pass++;
1267 } else {
1268 pass = 0;
1269 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1270 }
1271 } while ((pass < 5) && (count++ < 0x10000));
1272
1273 return val & 1 ? 1 : 0;
1274}
1275
1276static void set_clock(void *i2c_priv, int clock)
1277{
1278 struct ast_i2c_chan *i2c = i2c_priv;
1279 struct ast_private *ast = i2c->dev->dev_private;
1280 int i;
1281 u8 ujcrb7, jtemp;
1282
1283 for (i = 0; i < 0x10000; i++) {
1284 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1285 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1286 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1287 if (ujcrb7 == jtemp)
1288 break;
1289 }
1290}
1291
1292static void set_data(void *i2c_priv, int data)
1293{
1294 struct ast_i2c_chan *i2c = i2c_priv;
1295 struct ast_private *ast = i2c->dev->dev_private;
1296 int i;
1297 u8 ujcrb7, jtemp;
1298
1299 for (i = 0; i < 0x10000; i++) {
1300 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1301 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1302 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1303 if (ujcrb7 == jtemp)
1304 break;
1305 }
1306}
1307
1308static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1309{
1310 struct ast_i2c_chan *i2c;
1311 int ret;
1312
1313 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1314 if (!i2c)
1315 return NULL;
1316
1317 i2c->adapter.owner = THIS_MODULE;
1318 i2c->adapter.class = I2C_CLASS_DDC;
1319 i2c->adapter.dev.parent = &dev->pdev->dev;
1320 i2c->dev = dev;
1321 i2c_set_adapdata(&i2c->adapter, i2c);
1322 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1323 "AST i2c bit bus");
1324 i2c->adapter.algo_data = &i2c->bit;
1325
1326 i2c->bit.udelay = 20;
1327 i2c->bit.timeout = 2;
1328 i2c->bit.data = i2c;
1329 i2c->bit.setsda = set_data;
1330 i2c->bit.setscl = set_clock;
1331 i2c->bit.getsda = get_data;
1332 i2c->bit.getscl = get_clock;
1333 ret = i2c_bit_add_bus(&i2c->adapter);
1334 if (ret) {
1335 DRM_ERROR("Failed to register bit i2c\n");
1336 goto out_free;
1337 }
1338
1339 return i2c;
1340out_free:
1341 kfree(i2c);
1342 return NULL;
1343}
1344
1345static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1346{
1347 if (!i2c)
1348 return;
1349 i2c_del_adapter(&i2c->adapter);
1350 kfree(i2c);
1351}
1352
1353static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1354{
1355 union {
1356 u32 ul;
1357 u8 b[4];
1358 } srcdata32[2], data32;
1359 union {
1360 u16 us;
1361 u8 b[2];
1362 } data16;
1363 u32 csum = 0;
1364 s32 alpha_dst_delta, last_alpha_dst_delta;
1365 u8 *srcxor, *dstxor;
1366 int i, j;
1367 u32 per_pixel_copy, two_pixel_copy;
1368
1369 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1370 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1371
1372 srcxor = src;
1373 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1374 per_pixel_copy = width & 1;
1375 two_pixel_copy = width >> 1;
1376
1377 for (j = 0; j < height; j++) {
1378 for (i = 0; i < two_pixel_copy; i++) {
1379 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1380 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1381 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1382 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1383 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1384 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
1385
1386 writel(data32.ul, dstxor);
1387 csum += data32.ul;
1388
1389 dstxor += 4;
1390 srcxor += 8;
1391
1392 }
1393
1394 for (i = 0; i < per_pixel_copy; i++) {
1395 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1396 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1397 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1398 writew(data16.us, dstxor);
1399 csum += (u32)data16.us;
1400
1401 dstxor += 2;
1402 srcxor += 4;
1403 }
1404 dstxor += last_alpha_dst_delta;
1405 }
1406 return csum;
1407}
1408
1409static int ast_cursor_update(void *dst, void *src, unsigned int width,
1410 unsigned int height)
1411{
1412 u32 csum;
1413
1414
1415 csum = copy_cursor_image(src, dst, width, height);
1416
1417
1418 dst += AST_HWC_SIZE;
1419 writel(csum, dst);
1420 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1421 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1422 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1423 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1424
1425 return 0;
1426}
1427
1428static void ast_cursor_set_base(struct ast_private *ast, u64 address)
1429{
1430 u8 addr0 = (address >> 3) & 0xff;
1431 u8 addr1 = (address >> 11) & 0xff;
1432 u8 addr2 = (address >> 19) & 0xff;
1433
1434 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
1435 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
1436 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
1437}
1438
1439static int ast_cursor_move(struct drm_crtc *crtc,
1440 int x, int y)
1441{
1442 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1443 struct ast_private *ast = crtc->dev->dev_private;
1444 struct drm_gem_vram_object *gbo;
1445 int x_offset, y_offset;
1446 u8 *dst, *sig;
1447 u8 jreg;
1448
1449 gbo = ast->cursor.gbo[ast->cursor.next_index];
1450 dst = drm_gem_vram_vmap(gbo);
1451 if (IS_ERR(dst))
1452 return PTR_ERR(dst);
1453
1454 sig = dst + AST_HWC_SIZE;
1455 writel(x, sig + AST_HWC_SIGNATURE_X);
1456 writel(y, sig + AST_HWC_SIGNATURE_Y);
1457
1458 x_offset = ast_crtc->offset_x;
1459 y_offset = ast_crtc->offset_y;
1460 if (x < 0) {
1461 x_offset = (-x) + ast_crtc->offset_x;
1462 x = 0;
1463 }
1464
1465 if (y < 0) {
1466 y_offset = (-y) + ast_crtc->offset_y;
1467 y = 0;
1468 }
1469 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1470 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1471 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1472 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1473 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1474 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1475
1476
1477 jreg = 0x02 |
1478 0x01;
1479 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1480
1481 drm_gem_vram_vunmap(gbo, dst);
1482
1483 return 0;
1484}
1485
