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24#include "intel_atomic.h"
25#include "intel_cdclk.h"
26#include "intel_display_types.h"
27#include "intel_sideband.h"
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57static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
58 struct intel_cdclk_config *cdclk_config)
59{
60 cdclk_config->cdclk = 133333;
61}
62
63static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
64 struct intel_cdclk_config *cdclk_config)
65{
66 cdclk_config->cdclk = 200000;
67}
68
69static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
70 struct intel_cdclk_config *cdclk_config)
71{
72 cdclk_config->cdclk = 266667;
73}
74
75static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
76 struct intel_cdclk_config *cdclk_config)
77{
78 cdclk_config->cdclk = 333333;
79}
80
81static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
82 struct intel_cdclk_config *cdclk_config)
83{
84 cdclk_config->cdclk = 400000;
85}
86
87static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
88 struct intel_cdclk_config *cdclk_config)
89{
90 cdclk_config->cdclk = 450000;
91}
92
93static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
94 struct intel_cdclk_config *cdclk_config)
95{
96 struct pci_dev *pdev = dev_priv->drm.pdev;
97 u16 hpllcc = 0;
98
99
100
101
102
103
104 if (pdev->revision == 0x1) {
105 cdclk_config->cdclk = 133333;
106 return;
107 }
108
109 pci_bus_read_config_word(pdev->bus,
110 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
111
112
113
114
115 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
116 case GC_CLOCK_133_200:
117 case GC_CLOCK_133_200_2:
118 case GC_CLOCK_100_200:
119 cdclk_config->cdclk = 200000;
120 break;
121 case GC_CLOCK_166_250:
122 cdclk_config->cdclk = 250000;
123 break;
124 case GC_CLOCK_100_133:
125 cdclk_config->cdclk = 133333;
126 break;
127 case GC_CLOCK_133_266:
128 case GC_CLOCK_133_266_2:
129 case GC_CLOCK_166_266:
130 cdclk_config->cdclk = 266667;
131 break;
132 }
133}
134
135static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
136 struct intel_cdclk_config *cdclk_config)
137{
138 struct pci_dev *pdev = dev_priv->drm.pdev;
139 u16 gcfgc = 0;
140
141 pci_read_config_word(pdev, GCFGC, &gcfgc);
142
143 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
144 cdclk_config->cdclk = 133333;
145 return;
146 }
147
148 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
149 case GC_DISPLAY_CLOCK_333_320_MHZ:
150 cdclk_config->cdclk = 333333;
151 break;
152 default:
153 case GC_DISPLAY_CLOCK_190_200_MHZ:
154 cdclk_config->cdclk = 190000;
155 break;
156 }
157}
158
159static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
160 struct intel_cdclk_config *cdclk_config)
161{
162 struct pci_dev *pdev = dev_priv->drm.pdev;
163 u16 gcfgc = 0;
164
165 pci_read_config_word(pdev, GCFGC, &gcfgc);
166
167 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
168 cdclk_config->cdclk = 133333;
169 return;
170 }
171
172 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
173 case GC_DISPLAY_CLOCK_333_320_MHZ:
174 cdclk_config->cdclk = 320000;
175 break;
176 default:
177 case GC_DISPLAY_CLOCK_190_200_MHZ:
178 cdclk_config->cdclk = 200000;
179 break;
180 }
181}
182
183static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
184{
185 static const unsigned int blb_vco[8] = {
186 [0] = 3200000,
187 [1] = 4000000,
188 [2] = 5333333,
189 [3] = 4800000,
190 [4] = 6400000,
191 };
192 static const unsigned int pnv_vco[8] = {
193 [0] = 3200000,
194 [1] = 4000000,
195 [2] = 5333333,
196 [3] = 4800000,
197 [4] = 2666667,
198 };
199 static const unsigned int cl_vco[8] = {
200 [0] = 3200000,
201 [1] = 4000000,
202 [2] = 5333333,
203 [3] = 6400000,
204 [4] = 3333333,
205 [5] = 3566667,
206 [6] = 4266667,
207 };
208 static const unsigned int elk_vco[8] = {
209 [0] = 3200000,
210 [1] = 4000000,
211 [2] = 5333333,
212 [3] = 4800000,
213 };
214 static const unsigned int ctg_vco[8] = {
215 [0] = 3200000,
216 [1] = 4000000,
217 [2] = 5333333,
218 [3] = 6400000,
219 [4] = 2666667,
220 [5] = 4266667,
221 };
222 const unsigned int *vco_table;
223 unsigned int vco;
224 u8 tmp = 0;
225
226
227 if (IS_GM45(dev_priv))
228 vco_table = ctg_vco;
229 else if (IS_G45(dev_priv))
230 vco_table = elk_vco;
231 else if (IS_I965GM(dev_priv))
232 vco_table = cl_vco;
233 else if (IS_PINEVIEW(dev_priv))
234 vco_table = pnv_vco;
235 else if (IS_G33(dev_priv))
236 vco_table = blb_vco;
237 else
238 return 0;
239
240 tmp = intel_de_read(dev_priv,
241 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
242
243 vco = vco_table[tmp & 0x7];
244 if (vco == 0)
245 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
246 tmp);
247 else
248 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
249
250 return vco;
251}
252
253static void g33_get_cdclk(struct drm_i915_private *dev_priv,
254 struct intel_cdclk_config *cdclk_config)
255{
256 struct pci_dev *pdev = dev_priv->drm.pdev;
257 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
258 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
259 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
260 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
261 const u8 *div_table;
262 unsigned int cdclk_sel;
263 u16 tmp = 0;
264
265 cdclk_config->vco = intel_hpll_vco(dev_priv);
266
267 pci_read_config_word(pdev, GCFGC, &tmp);
268
269 cdclk_sel = (tmp >> 4) & 0x7;
270
271 if (cdclk_sel >= ARRAY_SIZE(div_3200))
272 goto fail;
273
274 switch (cdclk_config->vco) {
275 case 3200000:
276 div_table = div_3200;
277 break;
278 case 4000000:
279 div_table = div_4000;
280 break;
281 case 4800000:
282 div_table = div_4800;
283 break;
284 case 5333333:
285 div_table = div_5333;
286 break;
287 default:
288 goto fail;
289 }
290
291 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
292 div_table[cdclk_sel]);
293 return;
294
295fail:
296 drm_err(&dev_priv->drm,
297 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
298 cdclk_config->vco, tmp);
299 cdclk_config->cdclk = 190476;
300}
301
302static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
303 struct intel_cdclk_config *cdclk_config)
304{
305 struct pci_dev *pdev = dev_priv->drm.pdev;
306 u16 gcfgc = 0;
307
308 pci_read_config_word(pdev, GCFGC, &gcfgc);
309
310 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
311 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
312 cdclk_config->cdclk = 266667;
313 break;
314 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
315 cdclk_config->cdclk = 333333;
316 break;
317 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
318 cdclk_config->cdclk = 444444;
319 break;
320 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
321 cdclk_config->cdclk = 200000;
322 break;
323 default:
324 drm_err(&dev_priv->drm,
325 "Unknown pnv display core clock 0x%04x\n", gcfgc);
326
327 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
328 cdclk_config->cdclk = 133333;
329 break;
330 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
331 cdclk_config->cdclk = 166667;
332 break;
333 }
334}
335
336static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
337 struct intel_cdclk_config *cdclk_config)
338{
339 struct pci_dev *pdev = dev_priv->drm.pdev;
340 static const u8 div_3200[] = { 16, 10, 8 };
341 static const u8 div_4000[] = { 20, 12, 10 };
342 static const u8 div_5333[] = { 24, 16, 14 };
343 const u8 *div_table;
344 unsigned int cdclk_sel;
345 u16 tmp = 0;
346
347 cdclk_config->vco = intel_hpll_vco(dev_priv);
348
349 pci_read_config_word(pdev, GCFGC, &tmp);
350
351 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
352
353 if (cdclk_sel >= ARRAY_SIZE(div_3200))
354 goto fail;
355
356 switch (cdclk_config->vco) {
357 case 3200000:
358 div_table = div_3200;
359 break;
360 case 4000000:
361 div_table = div_4000;
362 break;
363 case 5333333:
364 div_table = div_5333;
365 break;
366 default:
367 goto fail;
368 }
369
370 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
371 div_table[cdclk_sel]);
372 return;
373
374fail:
375 drm_err(&dev_priv->drm,
376 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
377 cdclk_config->vco, tmp);
378 cdclk_config->cdclk = 200000;
379}
380
381static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
382 struct intel_cdclk_config *cdclk_config)
383{
384 struct pci_dev *pdev = dev_priv->drm.pdev;
385 unsigned int cdclk_sel;
386 u16 tmp = 0;
387
388 cdclk_config->vco = intel_hpll_vco(dev_priv);
389
390 pci_read_config_word(pdev, GCFGC, &tmp);
391
392 cdclk_sel = (tmp >> 12) & 0x1;
393
394 switch (cdclk_config->vco) {
395 case 2666667:
396 case 4000000:
397 case 5333333:
398 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
399 break;
400 case 3200000:
401 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
402 break;
403 default:
404 drm_err(&dev_priv->drm,
405 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
406 cdclk_config->vco, tmp);
407 cdclk_config->cdclk = 222222;
408 break;
409 }
410}
411
412static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
413 struct intel_cdclk_config *cdclk_config)
414{
415 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
416 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
417
418 if (lcpll & LCPLL_CD_SOURCE_FCLK)
419 cdclk_config->cdclk = 800000;
420 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
421 cdclk_config->cdclk = 450000;
422 else if (freq == LCPLL_CLK_FREQ_450)
423 cdclk_config->cdclk = 450000;
424 else if (IS_HSW_ULT(dev_priv))
425 cdclk_config->cdclk = 337500;
426 else
427 cdclk_config->cdclk = 540000;
428}
429
430static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
431{
432 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
433 333333 : 320000;
434
435
436
437
438
439
440 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
441 return 400000;
442 else if (min_cdclk > 266667)
443 return freq_320;
444 else if (min_cdclk > 0)
445 return 266667;
446 else
447 return 200000;
448}
449
450static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
451{
452 if (IS_VALLEYVIEW(dev_priv)) {
453 if (cdclk >= 320000)
454 return 2;
455 else if (cdclk >= 266667)
456 return 1;
457 else
458 return 0;
459 } else {
460
461
462
463
464
465 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
466 }
467}
468
469static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
470 struct intel_cdclk_config *cdclk_config)
471{
472 u32 val;
473
474 vlv_iosf_sb_get(dev_priv,
475 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
476
477 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
478 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
479 CCK_DISPLAY_CLOCK_CONTROL,
480 cdclk_config->vco);
481
482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
483
484 vlv_iosf_sb_put(dev_priv,
485 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
486
487 if (IS_VALLEYVIEW(dev_priv))
488 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
489 DSPFREQGUAR_SHIFT;
490 else
491 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
492 DSPFREQGUAR_SHIFT_CHV;
493}
494
495static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
496{
497 unsigned int credits, default_credits;
498
499 if (IS_CHERRYVIEW(dev_priv))
500 default_credits = PFI_CREDIT(12);
501 else
502 default_credits = PFI_CREDIT(8);
503
504 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
505
506 if (IS_CHERRYVIEW(dev_priv))
507 credits = PFI_CREDIT_63;
508 else
509 credits = PFI_CREDIT(15);
510 } else {
511 credits = default_credits;
512 }
513
514
515
516
517
518 intel_de_write(dev_priv, GCI_CONTROL,
519 VGA_FAST_MODE_DISABLE | default_credits);
520
521 intel_de_write(dev_priv, GCI_CONTROL,
522 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
523
524
525
526
527
528 drm_WARN_ON(&dev_priv->drm,
529 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
530}
531
532static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
533 const struct intel_cdclk_config *cdclk_config,
534 enum pipe pipe)
535{
536 int cdclk = cdclk_config->cdclk;
537 u32 val, cmd = cdclk_config->voltage_level;
538 intel_wakeref_t wakeref;
539
540 switch (cdclk) {
541 case 400000:
542 case 333333:
543 case 320000:
544 case 266667:
545 case 200000:
546 break;
547 default:
548 MISSING_CASE(cdclk);
549 return;
550 }
551
552
553
554
555
556
557
558 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
559
560 vlv_iosf_sb_get(dev_priv,
561 BIT(VLV_IOSF_SB_CCK) |
562 BIT(VLV_IOSF_SB_BUNIT) |
563 BIT(VLV_IOSF_SB_PUNIT));
564
565 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
566 val &= ~DSPFREQGUAR_MASK;
567 val |= (cmd << DSPFREQGUAR_SHIFT);
568 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
569 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
570 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
571 50)) {
572 drm_err(&dev_priv->drm,
573 "timed out waiting for CDclk change\n");
574 }
575
576 if (cdclk == 400000) {
577 u32 divider;
578
579 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
580 cdclk) - 1;
581
582
583 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
584 val &= ~CCK_FREQUENCY_VALUES;
585 val |= divider;
586 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
587
588 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
589 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
590 50))
591 drm_err(&dev_priv->drm,
592 "timed out waiting for CDclk change\n");
593 }
594
595
596 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
597 val &= ~0x7f;
598
599
600
601
602
603 if (cdclk == 400000)
604 val |= 4500 / 250;
605 else
606 val |= 3000 / 250;
607 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
608
609 vlv_iosf_sb_put(dev_priv,
610 BIT(VLV_IOSF_SB_CCK) |
611 BIT(VLV_IOSF_SB_BUNIT) |
612 BIT(VLV_IOSF_SB_PUNIT));
613
614 intel_update_cdclk(dev_priv);
615
616 vlv_program_pfi_credits(dev_priv);
617
618 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
619}
620
621static void chv_set_cdclk(struct drm_i915_private *dev_priv,
622 const struct intel_cdclk_config *cdclk_config,
623 enum pipe pipe)
624{
625 int cdclk = cdclk_config->cdclk;
626 u32 val, cmd = cdclk_config->voltage_level;
627 intel_wakeref_t wakeref;
628
629 switch (cdclk) {
630 case 333333:
631 case 320000:
632 case 266667:
633 case 200000:
634 break;
635 default:
636 MISSING_CASE(cdclk);
637 return;
638 }
639
640
641
642
643
644
645
646 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
647
648 vlv_punit_get(dev_priv);
649 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
650 val &= ~DSPFREQGUAR_MASK_CHV;
651 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
652 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
653 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
654 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
655 50)) {
656 drm_err(&dev_priv->drm,
657 "timed out waiting for CDclk change\n");
658 }
659
660 vlv_punit_put(dev_priv);
661
662 intel_update_cdclk(dev_priv);
663
664 vlv_program_pfi_credits(dev_priv);
665
666 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
667}
668
669static int bdw_calc_cdclk(int min_cdclk)
670{
671 if (min_cdclk > 540000)
672 return 675000;
673 else if (min_cdclk > 450000)
674 return 540000;
675 else if (min_cdclk > 337500)
676 return 450000;
677 else
678 return 337500;
679}
680
681static u8 bdw_calc_voltage_level(int cdclk)
682{
683 switch (cdclk) {
684 default:
685 case 337500:
686 return 2;
687 case 450000:
688 return 0;
689 case 540000:
690 return 1;
691 case 675000:
692 return 3;
693 }
694}
695
696static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
697 struct intel_cdclk_config *cdclk_config)
698{
699 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
700 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
701
702 if (lcpll & LCPLL_CD_SOURCE_FCLK)
703 cdclk_config->cdclk = 800000;
704 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
705 cdclk_config->cdclk = 450000;
706 else if (freq == LCPLL_CLK_FREQ_450)
707 cdclk_config->cdclk = 450000;
708 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
709 cdclk_config->cdclk = 540000;
710 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
711 cdclk_config->cdclk = 337500;
712 else
713 cdclk_config->cdclk = 675000;
714
715
716
717
718
719 cdclk_config->voltage_level =
720 bdw_calc_voltage_level(cdclk_config->cdclk);
721}
722
723static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
724 const struct intel_cdclk_config *cdclk_config,
725 enum pipe pipe)
726{
727 int cdclk = cdclk_config->cdclk;
728 u32 val;
729 int ret;
730
731 if (drm_WARN(&dev_priv->drm,
732 (intel_de_read(dev_priv, LCPLL_CTL) &
733 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
734 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
735 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
736 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
737 "trying to change cdclk frequency with cdclk not enabled\n"))
738 return;
739
740 ret = sandybridge_pcode_write(dev_priv,
741 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
742 if (ret) {
743 drm_err(&dev_priv->drm,
744 "failed to inform pcode about cdclk change\n");
745 return;
746 }
747
748 val = intel_de_read(dev_priv, LCPLL_CTL);
749 val |= LCPLL_CD_SOURCE_FCLK;
750 intel_de_write(dev_priv, LCPLL_CTL, val);
751
752
753
754
755
756 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
757 LCPLL_CD_SOURCE_FCLK_DONE, 100))
758 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
759
760 val = intel_de_read(dev_priv, LCPLL_CTL);
761 val &= ~LCPLL_CLK_FREQ_MASK;
762
763 switch (cdclk) {
764 default:
765 MISSING_CASE(cdclk);
766
767 case 337500:
768 val |= LCPLL_CLK_FREQ_337_5_BDW;
769 break;
770 case 450000:
771 val |= LCPLL_CLK_FREQ_450;
772 break;
773 case 540000:
774 val |= LCPLL_CLK_FREQ_54O_BDW;
775 break;
776 case 675000:
777 val |= LCPLL_CLK_FREQ_675_BDW;
778 break;
779 }
780
781 intel_de_write(dev_priv, LCPLL_CTL, val);
782
783 val = intel_de_read(dev_priv, LCPLL_CTL);
784 val &= ~LCPLL_CD_SOURCE_FCLK;
785 intel_de_write(dev_priv, LCPLL_CTL, val);
786
787 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
788 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
789 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
790
791 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
792 cdclk_config->voltage_level);
793
794 intel_de_write(dev_priv, CDCLK_FREQ,
795 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
796
797 intel_update_cdclk(dev_priv);
798}
799
800static int skl_calc_cdclk(int min_cdclk, int vco)
801{
802 if (vco == 8640000) {
803 if (min_cdclk > 540000)
804 return 617143;
805 else if (min_cdclk > 432000)
806 return 540000;
807 else if (min_cdclk > 308571)
808 return 432000;
809 else
810 return 308571;
811 } else {
812 if (min_cdclk > 540000)
813 return 675000;
814 else if (min_cdclk > 450000)
815 return 540000;
816 else if (min_cdclk > 337500)
817 return 450000;
818 else
819 return 337500;
820 }
821}
822
823static u8 skl_calc_voltage_level(int cdclk)
824{
825 if (cdclk > 540000)
826 return 3;
827 else if (cdclk > 450000)
828 return 2;
829 else if (cdclk > 337500)
830 return 1;
831 else
832 return 0;
833}
834
835static void skl_dpll0_update(struct drm_i915_private *dev_priv,
836 struct intel_cdclk_config *cdclk_config)
837{
838 u32 val;
839
840 cdclk_config->ref = 24000;
841 cdclk_config->vco = 0;
842
843 val = intel_de_read(dev_priv, LCPLL1_CTL);
844 if ((val & LCPLL_PLL_ENABLE) == 0)
845 return;
846
847 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
848 return;
849
850 val = intel_de_read(dev_priv, DPLL_CTRL1);
851
852 if (drm_WARN_ON(&dev_priv->drm,
853 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
854 DPLL_CTRL1_SSC(SKL_DPLL0) |
855 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
856 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
857 return;
858
859 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
860 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
861 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
862 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
863 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
864 cdclk_config->vco = 8100000;
865 break;
866 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
867 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
868 cdclk_config->vco = 8640000;
869 break;
870 default:
871 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
872 break;
873 }
874}
875
876static void skl_get_cdclk(struct drm_i915_private *dev_priv,
877 struct intel_cdclk_config *cdclk_config)
878{
879 u32 cdctl;
880
881 skl_dpll0_update(dev_priv, cdclk_config);
882
883 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
884
885 if (cdclk_config->vco == 0)
886 goto out;
887
888 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
889
890 if (cdclk_config->vco == 8640000) {
891 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
892 case CDCLK_FREQ_450_432:
893 cdclk_config->cdclk = 432000;
894 break;
895 case CDCLK_FREQ_337_308:
896 cdclk_config->cdclk = 308571;
897 break;
898 case CDCLK_FREQ_540:
899 cdclk_config->cdclk = 540000;
900 break;
901 case CDCLK_FREQ_675_617:
902 cdclk_config->cdclk = 617143;
903 break;
904 default:
905 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
906 break;
907 }
908 } else {
909 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
910 case CDCLK_FREQ_450_432:
911 cdclk_config->cdclk = 450000;
912 break;
913 case CDCLK_FREQ_337_308:
914 cdclk_config->cdclk = 337500;
915 break;
916 case CDCLK_FREQ_540:
917 cdclk_config->cdclk = 540000;
918 break;
919 case CDCLK_FREQ_675_617:
920 cdclk_config->cdclk = 675000;
921 break;
922 default:
923 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
924 break;
925 }
926 }
927
928 out:
929
930
931
932
933 cdclk_config->voltage_level =
934 skl_calc_voltage_level(cdclk_config->cdclk);
935}
936
937
938static int skl_cdclk_decimal(int cdclk)
939{
940 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
941}
942
943static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
944 int vco)
945{
946 bool changed = dev_priv->skl_preferred_vco_freq != vco;
947
948 dev_priv->skl_preferred_vco_freq = vco;
949
950 if (changed)
951 intel_update_max_cdclk(dev_priv);
952}
953
954static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
955{
956 u32 val;
957
958 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
959
960
961
962
963
964
965
966
967
968
969 val = intel_de_read(dev_priv, DPLL_CTRL1);
970
971 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
972 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
973 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
974 if (vco == 8640000)
975 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
976 SKL_DPLL0);
977 else
978 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
979 SKL_DPLL0);
980
981 intel_de_write(dev_priv, DPLL_CTRL1, val);
982 intel_de_posting_read(dev_priv, DPLL_CTRL1);
983
984 intel_de_write(dev_priv, LCPLL1_CTL,
985 intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE);
986
987 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
988 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
989
990 dev_priv->cdclk.hw.vco = vco;
991
992
993 skl_set_preferred_cdclk_vco(dev_priv, vco);
994}
995
996static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
997{
998 intel_de_write(dev_priv, LCPLL1_CTL,
999 intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
1000 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1001 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1002
1003 dev_priv->cdclk.hw.vco = 0;
1004}
1005
1006static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1007 const struct intel_cdclk_config *cdclk_config,
1008 enum pipe pipe)
1009{
1010 int cdclk = cdclk_config->cdclk;
1011 int vco = cdclk_config->vco;
1012 u32 freq_select, cdclk_ctl;
1013 int ret;
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023 drm_WARN_ON_ONCE(&dev_priv->drm,
1024 IS_SKYLAKE(dev_priv) && vco == 8640000);
1025
1026 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1027 SKL_CDCLK_PREPARE_FOR_CHANGE,
1028 SKL_CDCLK_READY_FOR_CHANGE,
1029 SKL_CDCLK_READY_FOR_CHANGE, 3);
1030 if (ret) {
1031 drm_err(&dev_priv->drm,
1032 "Failed to inform PCU about cdclk change (%d)\n", ret);
1033 return;
1034 }
1035
1036
1037 switch (cdclk) {
1038 default:
1039 drm_WARN_ON(&dev_priv->drm,
1040 cdclk != dev_priv->cdclk.hw.bypass);
1041 drm_WARN_ON(&dev_priv->drm, vco != 0);
1042
1043 case 308571:
1044 case 337500:
1045 freq_select = CDCLK_FREQ_337_308;
1046 break;
1047 case 450000:
1048 case 432000:
1049 freq_select = CDCLK_FREQ_450_432;
1050 break;
1051 case 540000:
1052 freq_select = CDCLK_FREQ_540;
1053 break;
1054 case 617143:
1055 case 675000:
1056 freq_select = CDCLK_FREQ_675_617;
1057 break;
1058 }
1059
1060 if (dev_priv->cdclk.hw.vco != 0 &&
1061 dev_priv->cdclk.hw.vco != vco)
1062 skl_dpll0_disable(dev_priv);
1063
1064 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1065
1066 if (dev_priv->cdclk.hw.vco != vco) {
1067
1068 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1069 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1070 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1071 }
1072
1073
1074 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1075 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1076 intel_de_posting_read(dev_priv, CDCLK_CTL);
1077
1078 if (dev_priv->cdclk.hw.vco != vco)
1079 skl_dpll0_enable(dev_priv, vco);
1080
1081
1082 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1083 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1084
1085 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1086 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1087
1088
1089 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1090 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1091 intel_de_posting_read(dev_priv, CDCLK_CTL);
1092
1093
1094 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1095 cdclk_config->voltage_level);
1096
1097 intel_update_cdclk(dev_priv);
1098}
1099
1100static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1101{
1102 u32 cdctl, expected;
1103
1104
1105
1106
1107
1108
1109 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1110 goto sanitize;
1111
1112 intel_update_cdclk(dev_priv);
1113 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1114
1115
1116 if (dev_priv->cdclk.hw.vco == 0 ||
1117 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1118 goto sanitize;
1119
1120
1121
1122
1123
1124
1125
1126 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1127 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1128 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1129 if (cdctl == expected)
1130
1131 return;
1132
1133sanitize:
1134 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1135
1136
1137 dev_priv->cdclk.hw.cdclk = 0;
1138
1139 dev_priv->cdclk.hw.vco = -1;
1140}
1141
1142static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1143{
1144 struct intel_cdclk_config cdclk_config;
1145
1146 skl_sanitize_cdclk(dev_priv);
1147
1148 if (dev_priv->cdclk.hw.cdclk != 0 &&
1149 dev_priv->cdclk.hw.vco != 0) {
1150
1151
1152
1153
1154 if (dev_priv->skl_preferred_vco_freq == 0)
1155 skl_set_preferred_cdclk_vco(dev_priv,
1156 dev_priv->cdclk.hw.vco);
1157 return;
1158 }
1159
1160 cdclk_config = dev_priv->cdclk.hw;
1161
1162 cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1163 if (cdclk_config.vco == 0)
1164 cdclk_config.vco = 8100000;
1165 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1166 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1167
1168 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1169}
1170
1171static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1172{
1173 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1174
1175 cdclk_config.cdclk = cdclk_config.bypass;
1176 cdclk_config.vco = 0;
1177 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1178
1179 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1180}
1181
1182static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1183 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1184 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1185 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1186 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1187 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1188 {}
1189};
1190
1191static const struct intel_cdclk_vals glk_cdclk_table[] = {
1192 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1193 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1194 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1195 {}
1196};
1197
1198static const struct intel_cdclk_vals cnl_cdclk_table[] = {
1199 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
1200 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
1201 { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
1202
1203 { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
1204 { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
1205 { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
1206 {}
1207};
1208
1209static const struct intel_cdclk_vals icl_cdclk_table[] = {
1210 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1211 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1212 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1213 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1214 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1215 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1216
1217 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1218 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1219 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1220 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1221 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1222 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1223
1224 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1225 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1226 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1227 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1228 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1229 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1230 {}
1231};
1232
1233static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1234{
1235 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1236 int i;
1237
1238 for (i = 0; table[i].refclk; i++)
1239 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1240 table[i].cdclk >= min_cdclk)
1241 return table[i].cdclk;
1242
1243 drm_WARN(&dev_priv->drm, 1,
1244 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1245 min_cdclk, dev_priv->cdclk.hw.ref);
1246 return 0;
1247}
1248
1249static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1250{
1251 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1252 int i;
1253
1254 if (cdclk == dev_priv->cdclk.hw.bypass)
1255 return 0;
1256
1257 for (i = 0; table[i].refclk; i++)
1258 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1259 table[i].cdclk == cdclk)
1260 return dev_priv->cdclk.hw.ref * table[i].ratio;
1261
1262 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1263 cdclk, dev_priv->cdclk.hw.ref);
1264 return 0;
1265}
1266
1267static u8 bxt_calc_voltage_level(int cdclk)
1268{
1269 return DIV_ROUND_UP(cdclk, 25000);
1270}
1271
1272static u8 cnl_calc_voltage_level(int cdclk)
1273{
1274 if (cdclk > 336000)
1275 return 2;
1276 else if (cdclk > 168000)
1277 return 1;
1278 else
1279 return 0;
1280}
1281
1282static u8 icl_calc_voltage_level(int cdclk)
1283{
1284 if (cdclk > 556800)
1285 return 2;
1286 else if (cdclk > 312000)
1287 return 1;
1288 else
1289 return 0;
1290}
1291
1292static u8 ehl_calc_voltage_level(int cdclk)
1293{
1294 if (cdclk > 326400)
1295 return 3;
1296 else if (cdclk > 312000)
1297 return 2;
1298 else if (cdclk > 180000)
1299 return 1;
1300 else
1301 return 0;
1302}
1303
1304static u8 tgl_calc_voltage_level(int cdclk)
1305{
1306 if (cdclk > 556800)
1307 return 3;
1308 else if (cdclk > 326400)
1309 return 2;
1310 else if (cdclk > 312000)
1311 return 1;
1312 else
1313 return 0;
1314}
1315
1316static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
1317 struct intel_cdclk_config *cdclk_config)
1318{
1319 if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1320 cdclk_config->ref = 24000;
1321 else
1322 cdclk_config->ref = 19200;
1323}
1324
1325static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1326 struct intel_cdclk_config *cdclk_config)
1327{
1328 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1329
1330 switch (dssm) {
1331 default:
1332 MISSING_CASE(dssm);
1333
1334 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1335 cdclk_config->ref = 24000;
1336 break;
1337 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1338 cdclk_config->ref = 19200;
1339 break;
1340 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1341 cdclk_config->ref = 38400;
1342 break;
1343 }
1344}
1345
1346static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1347 struct intel_cdclk_config *cdclk_config)
1348{
1349 u32 val, ratio;
1350
1351 if (INTEL_GEN(dev_priv) >= 11)
1352 icl_readout_refclk(dev_priv, cdclk_config);
1353 else if (IS_CANNONLAKE(dev_priv))
1354 cnl_readout_refclk(dev_priv, cdclk_config);
1355 else
1356 cdclk_config->ref = 19200;
1357
1358 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1359 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1360 (val & BXT_DE_PLL_LOCK) == 0) {
1361
1362
1363
1364
1365 cdclk_config->vco = 0;
1366 return;
1367 }
1368
1369
1370
1371
1372
1373 if (INTEL_GEN(dev_priv) >= 10)
1374 ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
1375 else
1376 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1377
1378 cdclk_config->vco = ratio * cdclk_config->ref;
1379}
1380
1381static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1382 struct intel_cdclk_config *cdclk_config)
1383{
1384 u32 divider;
1385 int div;
1386
1387 bxt_de_pll_readout(dev_priv, cdclk_config);
1388
1389 if (INTEL_GEN(dev_priv) >= 12)
1390 cdclk_config->bypass = cdclk_config->ref / 2;
1391 else if (INTEL_GEN(dev_priv) >= 11)
1392 cdclk_config->bypass = 50000;
1393 else
1394 cdclk_config->bypass = cdclk_config->ref;
1395
1396 if (cdclk_config->vco == 0) {
1397 cdclk_config->cdclk = cdclk_config->bypass;
1398 goto out;
1399 }
1400
1401 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1402
1403 switch (divider) {
1404 case BXT_CDCLK_CD2X_DIV_SEL_1:
1405 div = 2;
1406 break;
1407 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1408 drm_WARN(&dev_priv->drm,
1409 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1410 "Unsupported divider\n");
1411 div = 3;
1412 break;
1413 case BXT_CDCLK_CD2X_DIV_SEL_2:
1414 div = 4;
1415 break;
1416 case BXT_CDCLK_CD2X_DIV_SEL_4:
1417 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
1418 "Unsupported divider\n");
1419 div = 8;
1420 break;
1421 default:
1422 MISSING_CASE(divider);
1423 return;
1424 }
1425
1426 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1427
1428 out:
1429
1430
1431
1432
1433 cdclk_config->voltage_level =
1434 dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
1435}
1436
1437static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1438{
1439 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1440
1441
1442 if (intel_de_wait_for_clear(dev_priv,
1443 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1444 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1445
1446 dev_priv->cdclk.hw.vco = 0;
1447}
1448
1449static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1450{
1451 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1452 u32 val;
1453
1454 val = intel_de_read(dev_priv, BXT_DE_PLL_CTL);
1455 val &= ~BXT_DE_PLL_RATIO_MASK;
1456 val |= BXT_DE_PLL_RATIO(ratio);
1457 intel_de_write(dev_priv, BXT_DE_PLL_CTL, val);
1458
1459 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1460
1461
1462 if (intel_de_wait_for_set(dev_priv,
1463 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1464 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1465
1466 dev_priv->cdclk.hw.vco = vco;
1467}
1468
1469static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1470{
1471 u32 val;
1472
1473 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1474 val &= ~BXT_DE_PLL_PLL_ENABLE;
1475 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1476
1477
1478 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1479 drm_err(&dev_priv->drm,
1480 "timeout waiting for CDCLK PLL unlock\n");
1481
1482 dev_priv->cdclk.hw.vco = 0;
1483}
1484
1485static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1486{
1487 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1488 u32 val;
1489
1490 val = CNL_CDCLK_PLL_RATIO(ratio);
1491 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1492
1493 val |= BXT_DE_PLL_PLL_ENABLE;
1494 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1495
1496
1497 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1498 drm_err(&dev_priv->drm,
1499 "timeout waiting for CDCLK PLL lock\n");
1500
1501 dev_priv->cdclk.hw.vco = vco;
1502}
1503
1504static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1505{
1506 if (INTEL_GEN(dev_priv) >= 12) {
1507 if (pipe == INVALID_PIPE)
1508 return TGL_CDCLK_CD2X_PIPE_NONE;
1509 else
1510 return TGL_CDCLK_CD2X_PIPE(pipe);
1511 } else if (INTEL_GEN(dev_priv) >= 11) {
1512 if (pipe == INVALID_PIPE)
1513 return ICL_CDCLK_CD2X_PIPE_NONE;
1514 else
1515 return ICL_CDCLK_CD2X_PIPE(pipe);
1516 } else {
1517 if (pipe == INVALID_PIPE)
1518 return BXT_CDCLK_CD2X_PIPE_NONE;
1519 else
1520 return BXT_CDCLK_CD2X_PIPE(pipe);
1521 }
1522}
1523
1524static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1525 const struct intel_cdclk_config *cdclk_config,
1526 enum pipe pipe)
1527{
1528 int cdclk = cdclk_config->cdclk;
1529 int vco = cdclk_config->vco;
1530 u32 val, divider;
1531 int ret;
1532
1533
1534 if (INTEL_GEN(dev_priv) >= 10)
1535 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1536 SKL_CDCLK_PREPARE_FOR_CHANGE,
1537 SKL_CDCLK_READY_FOR_CHANGE,
1538 SKL_CDCLK_READY_FOR_CHANGE, 3);
1539 else
1540
1541
1542
1543
1544 ret = sandybridge_pcode_write_timeout(dev_priv,
1545 HSW_PCODE_DE_WRITE_FREQ_REQ,
1546 0x80000000, 150, 2);
1547
1548 if (ret) {
1549 drm_err(&dev_priv->drm,
1550 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1551 ret, cdclk);
1552 return;
1553 }
1554
1555
1556 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1557 default:
1558 drm_WARN_ON(&dev_priv->drm,
1559 cdclk != dev_priv->cdclk.hw.bypass);
1560 drm_WARN_ON(&dev_priv->drm, vco != 0);
1561
1562 case 2:
1563 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1564 break;
1565 case 3:
1566 drm_WARN(&dev_priv->drm,
1567 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1568 "Unsupported divider\n");
1569 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1570 break;
1571 case 4:
1572 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1573 break;
1574 case 8:
1575 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
1576 "Unsupported divider\n");
1577 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1578 break;
1579 }
1580
1581 if (INTEL_GEN(dev_priv) >= 10) {
1582 if (dev_priv->cdclk.hw.vco != 0 &&
1583 dev_priv->cdclk.hw.vco != vco)
1584 cnl_cdclk_pll_disable(dev_priv);
1585
1586 if (dev_priv->cdclk.hw.vco != vco)
1587 cnl_cdclk_pll_enable(dev_priv, vco);
1588
1589 } else {
1590 if (dev_priv->cdclk.hw.vco != 0 &&
1591 dev_priv->cdclk.hw.vco != vco)
1592 bxt_de_pll_disable(dev_priv);
1593
1594 if (dev_priv->cdclk.hw.vco != vco)
1595 bxt_de_pll_enable(dev_priv, vco);
1596 }
1597
1598 val = divider | skl_cdclk_decimal(cdclk) |
1599 bxt_cdclk_cd2x_pipe(dev_priv, pipe);
1600
1601
1602
1603
1604
1605 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000)
1606 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1607 intel_de_write(dev_priv, CDCLK_CTL, val);
1608
1609 if (pipe != INVALID_PIPE)
1610 intel_wait_for_vblank(dev_priv, pipe);
1611
1612 if (INTEL_GEN(dev_priv) >= 10) {
1613 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1614 cdclk_config->voltage_level);
1615 } else {
1616
1617
1618
1619
1620
1621
1622 ret = sandybridge_pcode_write_timeout(dev_priv,
1623 HSW_PCODE_DE_WRITE_FREQ_REQ,
1624 cdclk_config->voltage_level,
1625 150, 2);
1626 }
1627
1628 if (ret) {
1629 drm_err(&dev_priv->drm,
1630 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
1631 ret, cdclk);
1632 return;
1633 }
1634
1635 intel_update_cdclk(dev_priv);
1636
1637 if (INTEL_GEN(dev_priv) >= 10)
1638
1639
1640
1641
1642 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
1643}
1644
1645static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1646{
1647 u32 cdctl, expected;
1648 int cdclk, vco;
1649
1650 intel_update_cdclk(dev_priv);
1651 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1652
1653 if (dev_priv->cdclk.hw.vco == 0 ||
1654 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1655 goto sanitize;
1656
1657
1658
1659
1660
1661
1662
1663 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1664
1665
1666
1667
1668
1669 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
1670
1671
1672 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
1673 if (cdclk != dev_priv->cdclk.hw.cdclk)
1674 goto sanitize;
1675
1676
1677 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
1678 if (vco != dev_priv->cdclk.hw.vco)
1679 goto sanitize;
1680
1681 expected = skl_cdclk_decimal(cdclk);
1682
1683
1684 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
1685 dev_priv->cdclk.hw.cdclk)) {
1686 case 2:
1687 expected |= BXT_CDCLK_CD2X_DIV_SEL_1;
1688 break;
1689 case 3:
1690 expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5;
1691 break;
1692 case 4:
1693 expected |= BXT_CDCLK_CD2X_DIV_SEL_2;
1694 break;
1695 case 8:
1696 expected |= BXT_CDCLK_CD2X_DIV_SEL_4;
1697 break;
1698 default:
1699 goto sanitize;
1700 }
1701
1702
1703
1704
1705
1706 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)
1707 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1708
1709 if (cdctl == expected)
1710
1711 return;
1712
1713sanitize:
1714 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1715
1716
1717 dev_priv->cdclk.hw.cdclk = 0;
1718
1719
1720 dev_priv->cdclk.hw.vco = -1;
1721}
1722
1723static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
1724{
1725 struct intel_cdclk_config cdclk_config;
1726
1727 bxt_sanitize_cdclk(dev_priv);
1728
1729 if (dev_priv->cdclk.hw.cdclk != 0 &&
1730 dev_priv->cdclk.hw.vco != 0)
1731 return;
1732
1733 cdclk_config = dev_priv->cdclk.hw;
1734
1735
1736
1737
1738
1739
1740 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
1741 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
1742 cdclk_config.voltage_level =
1743 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1744
1745 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1746}
1747
1748static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1749{
1750 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1751
1752 cdclk_config.cdclk = cdclk_config.bypass;
1753 cdclk_config.vco = 0;
1754 cdclk_config.voltage_level =
1755 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1756
1757 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1758}
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769void intel_cdclk_init_hw(struct drm_i915_private *i915)
1770{
1771 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
1772 bxt_cdclk_init_hw(i915);
1773 else if (IS_GEN9_BC(i915))
1774 skl_cdclk_init_hw(i915);
1775}
1776
1777
1778
1779
1780
1781
1782
1783
1784void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
1785{
1786 if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
1787 bxt_cdclk_uninit_hw(i915);
1788 else if (IS_GEN9_BC(i915))
1789 skl_cdclk_uninit_hw(i915);
1790}
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
1803 const struct intel_cdclk_config *b)
1804{
1805 return a->cdclk != b->cdclk ||
1806 a->vco != b->vco ||
1807 a->ref != b->ref;
1808}
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
1822 const struct intel_cdclk_config *a,
1823 const struct intel_cdclk_config *b)
1824{
1825
1826 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
1827 return false;
1828
1829 return a->cdclk != b->cdclk &&
1830 a->vco == b->vco &&
1831 a->ref == b->ref;
1832}
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
1843 const struct intel_cdclk_config *b)
1844{
1845 return intel_cdclk_needs_modeset(a, b) ||
1846 a->voltage_level != b->voltage_level;
1847}
1848
1849void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
1850 const char *context)
1851{
1852 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
1853 context, cdclk_config->cdclk, cdclk_config->vco,
1854 cdclk_config->ref, cdclk_config->bypass,
1855 cdclk_config->voltage_level);
1856}
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867static void intel_set_cdclk(struct drm_i915_private *dev_priv,
1868 const struct intel_cdclk_config *cdclk_config,
1869 enum pipe pipe)
1870{
1871 struct intel_encoder *encoder;
1872
1873 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
1874 return;
1875
1876 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
1877 return;
1878
1879 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
1880
1881
1882
1883
1884
1885
1886 mutex_lock(&dev_priv->gmbus_mutex);
1887 for_each_intel_dp(&dev_priv->drm, encoder) {
1888 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1889
1890 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
1891 &dev_priv->gmbus_mutex);
1892 }
1893
1894 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
1895
1896 for_each_intel_dp(&dev_priv->drm, encoder) {
1897 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1898
1899 mutex_unlock(&intel_dp->aux.hw_mutex);
1900 }
1901 mutex_unlock(&dev_priv->gmbus_mutex);
1902
1903 if (drm_WARN(&dev_priv->drm,
1904 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
1905 "cdclk state doesn't match!\n")) {
1906 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
1907 intel_dump_cdclk_config(cdclk_config, "[sw state]");
1908 }
1909}
1910
1911
1912
1913
1914
1915
1916
1917
1918void
1919intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
1920{
1921 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1922 const struct intel_cdclk_state *old_cdclk_state =
1923 intel_atomic_get_old_cdclk_state(state);
1924 const struct intel_cdclk_state *new_cdclk_state =
1925 intel_atomic_get_new_cdclk_state(state);
1926 enum pipe pipe = new_cdclk_state->pipe;
1927
1928 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1929 &new_cdclk_state->actual))
1930 return;
1931
1932 if (pipe == INVALID_PIPE ||
1933 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
1934 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
1935
1936 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
1937 }
1938}
1939
1940
1941
1942
1943
1944
1945
1946
1947void
1948intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
1949{
1950 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1951 const struct intel_cdclk_state *old_cdclk_state =
1952 intel_atomic_get_old_cdclk_state(state);
1953 const struct intel_cdclk_state *new_cdclk_state =
1954 intel_atomic_get_new_cdclk_state(state);
1955 enum pipe pipe = new_cdclk_state->pipe;
1956
1957 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1958 &new_cdclk_state->actual))
1959 return;
1960
1961 if (pipe != INVALID_PIPE &&
1962 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
1963 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
1964
1965 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
1966 }
1967}
1968
1969static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
1970{
1971 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1972 int pixel_rate = crtc_state->pixel_rate;
1973
1974 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1975 return DIV_ROUND_UP(pixel_rate, 2);
1976 else if (IS_GEN(dev_priv, 9) ||
1977 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1978 return pixel_rate;
1979 else if (IS_CHERRYVIEW(dev_priv))
1980 return DIV_ROUND_UP(pixel_rate * 100, 95);
1981 else if (crtc_state->double_wide)
1982 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
1983 else
1984 return DIV_ROUND_UP(pixel_rate * 100, 90);
1985}
1986
1987static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
1988{
1989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1990 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1991 struct intel_plane *plane;
1992 int min_cdclk = 0;
1993
1994 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1995 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
1996
1997 return min_cdclk;
1998}
1999
2000int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2001{
2002 struct drm_i915_private *dev_priv =
2003 to_i915(crtc_state->uapi.crtc->dev);
2004 int min_cdclk;
2005
2006 if (!crtc_state->hw.enable)
2007 return 0;
2008
2009 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2010
2011
2012 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2013 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2014
2015
2016
2017
2018
2019
2020 if (intel_crtc_has_dp_encoder(crtc_state) &&
2021 crtc_state->has_audio &&
2022 crtc_state->port_clock >= 540000 &&
2023 crtc_state->lane_count == 4) {
2024 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2025
2026 min_cdclk = max(316800, min_cdclk);
2027 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2028
2029 min_cdclk = max(432000, min_cdclk);
2030 }
2031 }
2032
2033
2034
2035
2036
2037 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
2038 min_cdclk = max(2 * 96000, min_cdclk);
2039
2040
2041
2042
2043
2044
2045
2046
2047 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2048 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2049 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2050
2051
2052
2053
2054
2055 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2056 IS_VALLEYVIEW(dev_priv))
2057 min_cdclk = max(320000, min_cdclk);
2058
2059
2060
2061
2062
2063
2064 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2065 IS_GEMINILAKE(dev_priv))
2066 min_cdclk = max(158400, min_cdclk);
2067
2068
2069 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080 if (IS_TIGERLAKE(dev_priv))
2081 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
2082
2083 if (min_cdclk > dev_priv->max_cdclk_freq) {
2084 drm_dbg_kms(&dev_priv->drm,
2085 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2086 min_cdclk, dev_priv->max_cdclk_freq);
2087 return -EINVAL;
2088 }
2089
2090 return min_cdclk;
2091}
2092
2093static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2094{
2095 struct intel_atomic_state *state = cdclk_state->base.state;
2096 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2097 struct intel_crtc *crtc;
2098 struct intel_crtc_state *crtc_state;
2099 int min_cdclk, i;
2100 enum pipe pipe;
2101
2102 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2103 int ret;
2104
2105 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2106 if (min_cdclk < 0)
2107 return min_cdclk;
2108
2109 if (cdclk_state->min_cdclk[i] == min_cdclk)
2110 continue;
2111
2112 cdclk_state->min_cdclk[i] = min_cdclk;
2113
2114 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2115 if (ret)
2116 return ret;
2117 }
2118
2119 min_cdclk = cdclk_state->force_min_cdclk;
2120 for_each_pipe(dev_priv, pipe)
2121 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2122
2123 return min_cdclk;
2124}
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2140{
2141 struct intel_atomic_state *state = cdclk_state->base.state;
2142 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2143 struct intel_crtc *crtc;
2144 struct intel_crtc_state *crtc_state;
2145 u8 min_voltage_level;
2146 int i;
2147 enum pipe pipe;
2148
2149 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2150 int ret;
2151
2152 if (crtc_state->hw.enable)
2153 min_voltage_level = crtc_state->min_voltage_level;
2154 else
2155 min_voltage_level = 0;
2156
2157 if (cdclk_state->min_voltage_level[i] == min_voltage_level)
2158 continue;
2159
2160 cdclk_state->min_voltage_level[i] = min_voltage_level;
2161
2162 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2163 if (ret)
2164 return ret;
2165 }
2166
2167 min_voltage_level = 0;
2168 for_each_pipe(dev_priv, pipe)
2169 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2170 min_voltage_level);
2171
2172 return min_voltage_level;
2173}
2174
2175static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2176{
2177 struct intel_atomic_state *state = cdclk_state->base.state;
2178 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2179 int min_cdclk, cdclk;
2180
2181 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2182 if (min_cdclk < 0)
2183 return min_cdclk;
2184
2185 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2186
2187 cdclk_state->logical.cdclk = cdclk;
2188 cdclk_state->logical.voltage_level =
2189 vlv_calc_voltage_level(dev_priv, cdclk);
2190
2191 if (!cdclk_state->active_pipes) {
2192 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2193
2194 cdclk_state->actual.cdclk = cdclk;
2195 cdclk_state->actual.voltage_level =
2196 vlv_calc_voltage_level(dev_priv, cdclk);
2197 } else {
2198 cdclk_state->actual = cdclk_state->logical;
2199 }
2200
2201 return 0;
2202}
2203
2204static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2205{
2206 int min_cdclk, cdclk;
2207
2208 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2209 if (min_cdclk < 0)
2210 return min_cdclk;
2211
2212
2213
2214
2215
2216 cdclk = bdw_calc_cdclk(min_cdclk);
2217
2218 cdclk_state->logical.cdclk = cdclk;
2219 cdclk_state->logical.voltage_level =
2220 bdw_calc_voltage_level(cdclk);
2221
2222 if (!cdclk_state->active_pipes) {
2223 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2224
2225 cdclk_state->actual.cdclk = cdclk;
2226 cdclk_state->actual.voltage_level =
2227 bdw_calc_voltage_level(cdclk);
2228 } else {
2229 cdclk_state->actual = cdclk_state->logical;
2230 }
2231
2232 return 0;
2233}
2234
2235static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2236{
2237 struct intel_atomic_state *state = cdclk_state->base.state;
2238 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2239 struct intel_crtc *crtc;
2240 struct intel_crtc_state *crtc_state;
2241 int vco, i;
2242
2243 vco = cdclk_state->logical.vco;
2244 if (!vco)
2245 vco = dev_priv->skl_preferred_vco_freq;
2246
2247 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2248 if (!crtc_state->hw.enable)
2249 continue;
2250
2251 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2252 continue;
2253
2254
2255
2256
2257
2258 switch (crtc_state->port_clock / 2) {
2259 case 108000:
2260 case 216000:
2261 vco = 8640000;
2262 break;
2263 default:
2264 vco = 8100000;
2265 break;
2266 }
2267 }
2268
2269 return vco;
2270}
2271
2272static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2273{
2274 int min_cdclk, cdclk, vco;
2275
2276 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2277 if (min_cdclk < 0)
2278 return min_cdclk;
2279
2280 vco = skl_dpll0_vco(cdclk_state);
2281
2282
2283
2284
2285
2286 cdclk = skl_calc_cdclk(min_cdclk, vco);
2287
2288 cdclk_state->logical.vco = vco;
2289 cdclk_state->logical.cdclk = cdclk;
2290 cdclk_state->logical.voltage_level =
2291 skl_calc_voltage_level(cdclk);
2292
2293 if (!cdclk_state->active_pipes) {
2294 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
2295
2296 cdclk_state->actual.vco = vco;
2297 cdclk_state->actual.cdclk = cdclk;
2298 cdclk_state->actual.voltage_level =
2299 skl_calc_voltage_level(cdclk);
2300 } else {
2301 cdclk_state->actual = cdclk_state->logical;
2302 }
2303
2304 return 0;
2305}
2306
2307static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2308{
2309 struct intel_atomic_state *state = cdclk_state->base.state;
2310 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2311 int min_cdclk, min_voltage_level, cdclk, vco;
2312
2313 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2314 if (min_cdclk < 0)
2315 return min_cdclk;
2316
2317 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
2318 if (min_voltage_level < 0)
2319 return min_voltage_level;
2320
2321 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2322 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2323
2324 cdclk_state->logical.vco = vco;
2325 cdclk_state->logical.cdclk = cdclk;
2326 cdclk_state->logical.voltage_level =
2327 max_t(int, min_voltage_level,
2328 dev_priv->display.calc_voltage_level(cdclk));
2329
2330 if (!cdclk_state->active_pipes) {
2331 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2332 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2333
2334 cdclk_state->actual.vco = vco;
2335 cdclk_state->actual.cdclk = cdclk;
2336 cdclk_state->actual.voltage_level =
2337 dev_priv->display.calc_voltage_level(cdclk);
2338 } else {
2339 cdclk_state->actual = cdclk_state->logical;
2340 }
2341
2342 return 0;
2343}
2344
2345static int intel_modeset_all_pipes(struct intel_atomic_state *state)
2346{
2347 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2348 struct intel_crtc *crtc;
2349
2350
2351
2352
2353
2354 for_each_intel_crtc(&dev_priv->drm, crtc) {
2355 struct intel_crtc_state *crtc_state;
2356 int ret;
2357
2358 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2359 if (IS_ERR(crtc_state))
2360 return PTR_ERR(crtc_state);
2361
2362 if (!crtc_state->hw.active ||
2363 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
2364 continue;
2365
2366 crtc_state->uapi.mode_changed = true;
2367
2368 ret = drm_atomic_add_affected_connectors(&state->base,
2369 &crtc->base);
2370 if (ret)
2371 return ret;
2372
2373 ret = drm_atomic_add_affected_planes(&state->base,
2374 &crtc->base);
2375 if (ret)
2376 return ret;
2377
2378 crtc_state->update_planes |= crtc_state->active_planes;
2379 }
2380
2381 return 0;
2382}
2383
2384static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2385{
2386 int min_cdclk;
2387
2388
2389
2390
2391
2392
2393 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2394 if (min_cdclk < 0)
2395 return min_cdclk;
2396
2397 return 0;
2398}
2399
2400static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
2401{
2402 struct intel_cdclk_state *cdclk_state;
2403
2404 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
2405 if (!cdclk_state)
2406 return NULL;
2407
2408 cdclk_state->force_min_cdclk_changed = false;
2409 cdclk_state->pipe = INVALID_PIPE;
2410
2411 return &cdclk_state->base;
2412}
2413
2414static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
2415 struct intel_global_state *state)
2416{
2417 kfree(state);
2418}
2419
2420static const struct intel_global_state_funcs intel_cdclk_funcs = {
2421 .atomic_duplicate_state = intel_cdclk_duplicate_state,
2422 .atomic_destroy_state = intel_cdclk_destroy_state,
2423};
2424
2425struct intel_cdclk_state *
2426intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
2427{
2428 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2429 struct intel_global_state *cdclk_state;
2430
2431 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
2432 if (IS_ERR(cdclk_state))
2433 return ERR_CAST(cdclk_state);
2434
2435 return to_intel_cdclk_state(cdclk_state);
2436}
2437
2438int intel_cdclk_init(struct drm_i915_private *dev_priv)
2439{
2440 struct intel_cdclk_state *cdclk_state;
2441
2442 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
2443 if (!cdclk_state)
2444 return -ENOMEM;
2445
2446 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
2447 &cdclk_state->base, &intel_cdclk_funcs);
2448
2449 return 0;
2450}
2451
2452int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
2453{
2454 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2455 const struct intel_cdclk_state *old_cdclk_state;
2456 struct intel_cdclk_state *new_cdclk_state;
2457 enum pipe pipe;
2458 int ret;
2459
2460 new_cdclk_state = intel_atomic_get_cdclk_state(state);
2461 if (IS_ERR(new_cdclk_state))
2462 return PTR_ERR(new_cdclk_state);
2463
2464 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
2465
2466 new_cdclk_state->active_pipes =
2467 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
2468
2469 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
2470 if (ret)
2471 return ret;
2472
2473 if (intel_cdclk_changed(&old_cdclk_state->actual,
2474 &new_cdclk_state->actual)) {
2475
2476
2477
2478
2479 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
2480 if (ret)
2481 return ret;
2482 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
2483 intel_cdclk_changed(&old_cdclk_state->logical,
2484 &new_cdclk_state->logical)) {
2485 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
2486 if (ret)
2487 return ret;
2488 } else {
2489 return 0;
2490 }
2491
2492 if (is_power_of_2(new_cdclk_state->active_pipes) &&
2493 intel_cdclk_can_cd2x_update(dev_priv,
2494 &old_cdclk_state->actual,
2495 &new_cdclk_state->actual)) {
2496 struct intel_crtc *crtc;
2497 struct intel_crtc_state *crtc_state;
2498
2499 pipe = ilog2(new_cdclk_state->active_pipes);
2500 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2501
2502 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2503 if (IS_ERR(crtc_state))
2504 return PTR_ERR(crtc_state);
2505
2506 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
2507 pipe = INVALID_PIPE;
2508 } else {
2509 pipe = INVALID_PIPE;
2510 }
2511
2512 if (pipe != INVALID_PIPE) {
2513 new_cdclk_state->pipe = pipe;
2514
2515 drm_dbg_kms(&dev_priv->drm,
2516 "Can change cdclk with pipe %c active\n",
2517 pipe_name(pipe));
2518 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
2519 &new_cdclk_state->actual)) {
2520
2521 ret = intel_modeset_all_pipes(state);
2522 if (ret)
2523 return ret;
2524
2525 new_cdclk_state->pipe = INVALID_PIPE;
2526
2527 drm_dbg_kms(&dev_priv->drm,
2528 "Modeset required for cdclk change\n");
2529 }
2530
2531 drm_dbg_kms(&dev_priv->drm,
2532 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
2533 new_cdclk_state->logical.cdclk,
2534 new_cdclk_state->actual.cdclk);
2535 drm_dbg_kms(&dev_priv->drm,
2536 "New voltage level calculated to be logical %u, actual %u\n",
2537 new_cdclk_state->logical.voltage_level,
2538 new_cdclk_state->actual.voltage_level);
2539
2540 return 0;
2541}
2542
2543static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2544{
2545 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2546
2547 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2548 return 2 * max_cdclk_freq;
2549 else if (IS_GEN(dev_priv, 9) ||
2550 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2551 return max_cdclk_freq;
2552 else if (IS_CHERRYVIEW(dev_priv))
2553 return max_cdclk_freq*95/100;
2554 else if (INTEL_GEN(dev_priv) < 4)
2555 return 2*max_cdclk_freq*90/100;
2556 else
2557 return max_cdclk_freq*90/100;
2558}
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2569{
2570 if (IS_ELKHARTLAKE(dev_priv)) {
2571 if (dev_priv->cdclk.hw.ref == 24000)
2572 dev_priv->max_cdclk_freq = 552000;
2573 else
2574 dev_priv->max_cdclk_freq = 556800;
2575 } else if (INTEL_GEN(dev_priv) >= 11) {
2576 if (dev_priv->cdclk.hw.ref == 24000)
2577 dev_priv->max_cdclk_freq = 648000;
2578 else
2579 dev_priv->max_cdclk_freq = 652800;
2580 } else if (IS_CANNONLAKE(dev_priv)) {
2581 dev_priv->max_cdclk_freq = 528000;
2582 } else if (IS_GEN9_BC(dev_priv)) {
2583 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2584 int max_cdclk, vco;
2585
2586 vco = dev_priv->skl_preferred_vco_freq;
2587 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
2588
2589
2590
2591
2592
2593
2594 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2595 max_cdclk = 617143;
2596 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2597 max_cdclk = 540000;
2598 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2599 max_cdclk = 432000;
2600 else
2601 max_cdclk = 308571;
2602
2603 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2604 } else if (IS_GEMINILAKE(dev_priv)) {
2605 dev_priv->max_cdclk_freq = 316800;
2606 } else if (IS_BROXTON(dev_priv)) {
2607 dev_priv->max_cdclk_freq = 624000;
2608 } else if (IS_BROADWELL(dev_priv)) {
2609
2610
2611
2612
2613
2614
2615 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
2616 dev_priv->max_cdclk_freq = 450000;
2617 else if (IS_BDW_ULX(dev_priv))
2618 dev_priv->max_cdclk_freq = 450000;
2619 else if (IS_BDW_ULT(dev_priv))
2620 dev_priv->max_cdclk_freq = 540000;
2621 else
2622 dev_priv->max_cdclk_freq = 675000;
2623 } else if (IS_CHERRYVIEW(dev_priv)) {
2624 dev_priv->max_cdclk_freq = 320000;
2625 } else if (IS_VALLEYVIEW(dev_priv)) {
2626 dev_priv->max_cdclk_freq = 400000;
2627 } else {
2628
2629 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2630 }
2631
2632 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2633
2634 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
2635 dev_priv->max_cdclk_freq);
2636
2637 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
2638 dev_priv->max_dotclk_freq);
2639}
2640
2641
2642
2643
2644
2645
2646
2647void intel_update_cdclk(struct drm_i915_private *dev_priv)
2648{
2649 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2650
2651
2652
2653
2654
2655
2656
2657 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2658 intel_de_write(dev_priv, GMBUSFREQ_VLV,
2659 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2660}
2661
2662static int cnp_rawclk(struct drm_i915_private *dev_priv)
2663{
2664 u32 rawclk;
2665 int divider, fraction;
2666
2667 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2668
2669 divider = 24000;
2670 fraction = 0;
2671 } else {
2672
2673 divider = 19000;
2674 fraction = 200;
2675 }
2676
2677 rawclk = CNP_RAWCLK_DIV(divider / 1000);
2678 if (fraction) {
2679 int numerator = 1;
2680
2681 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2682 fraction) - 1);
2683 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2684 rawclk |= ICP_RAWCLK_NUM(numerator);
2685 }
2686
2687 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
2688 return divider + fraction;
2689}
2690
2691static int pch_rawclk(struct drm_i915_private *dev_priv)
2692{
2693 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2694}
2695
2696static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2697{
2698
2699 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2700 CCK_DISPLAY_REF_CLOCK_CONTROL);
2701}
2702
2703static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2704{
2705 u32 clkcfg;
2706
2707
2708 clkcfg = intel_de_read(dev_priv, CLKCFG);
2709 switch (clkcfg & CLKCFG_FSB_MASK) {
2710 case CLKCFG_FSB_400:
2711 return 100000;
2712 case CLKCFG_FSB_533:
2713 return 133333;
2714 case CLKCFG_FSB_667:
2715 return 166667;
2716 case CLKCFG_FSB_800:
2717 return 200000;
2718 case CLKCFG_FSB_1067:
2719 case CLKCFG_FSB_1067_ALT:
2720 return 266667;
2721 case CLKCFG_FSB_1333:
2722 case CLKCFG_FSB_1333_ALT:
2723 return 333333;
2724 default:
2725 return 133333;
2726 }
2727}
2728
2729
2730
2731
2732
2733
2734
2735
2736u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
2737{
2738 u32 freq;
2739
2740 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2741 freq = cnp_rawclk(dev_priv);
2742 else if (HAS_PCH_SPLIT(dev_priv))
2743 freq = pch_rawclk(dev_priv);
2744 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2745 freq = vlv_hrawclk(dev_priv);
2746 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2747 freq = g4x_hrawclk(dev_priv);
2748 else
2749
2750 return 0;
2751
2752 return freq;
2753}
2754
2755
2756
2757
2758
2759void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2760{
2761 if (INTEL_GEN(dev_priv) >= 12) {
2762 dev_priv->display.set_cdclk = bxt_set_cdclk;
2763 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2764 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2765 dev_priv->cdclk.table = icl_cdclk_table;
2766 } else if (IS_ELKHARTLAKE(dev_priv)) {
2767 dev_priv->display.set_cdclk = bxt_set_cdclk;
2768 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2769 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
2770 dev_priv->cdclk.table = icl_cdclk_table;
2771 } else if (INTEL_GEN(dev_priv) >= 11) {
2772 dev_priv->display.set_cdclk = bxt_set_cdclk;
2773 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2774 dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
2775 dev_priv->cdclk.table = icl_cdclk_table;
2776 } else if (IS_CANNONLAKE(dev_priv)) {
2777 dev_priv->display.set_cdclk = bxt_set_cdclk;
2778 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2779 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
2780 dev_priv->cdclk.table = cnl_cdclk_table;
2781 } else if (IS_GEN9_LP(dev_priv)) {
2782 dev_priv->display.set_cdclk = bxt_set_cdclk;
2783 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2784 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
2785 if (IS_GEMINILAKE(dev_priv))
2786 dev_priv->cdclk.table = glk_cdclk_table;
2787 else
2788 dev_priv->cdclk.table = bxt_cdclk_table;
2789 } else if (IS_GEN9_BC(dev_priv)) {
2790 dev_priv->display.set_cdclk = skl_set_cdclk;
2791 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
2792 } else if (IS_BROADWELL(dev_priv)) {
2793 dev_priv->display.set_cdclk = bdw_set_cdclk;
2794 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
2795 } else if (IS_CHERRYVIEW(dev_priv)) {
2796 dev_priv->display.set_cdclk = chv_set_cdclk;
2797 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2798 } else if (IS_VALLEYVIEW(dev_priv)) {
2799 dev_priv->display.set_cdclk = vlv_set_cdclk;
2800 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2801 } else {
2802 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
2803 }
2804
2805 if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
2806 dev_priv->display.get_cdclk = bxt_get_cdclk;
2807 else if (IS_GEN9_BC(dev_priv))
2808 dev_priv->display.get_cdclk = skl_get_cdclk;
2809 else if (IS_BROADWELL(dev_priv))
2810 dev_priv->display.get_cdclk = bdw_get_cdclk;
2811 else if (IS_HASWELL(dev_priv))
2812 dev_priv->display.get_cdclk = hsw_get_cdclk;
2813 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2814 dev_priv->display.get_cdclk = vlv_get_cdclk;
2815 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2816 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2817 else if (IS_GEN(dev_priv, 5))
2818 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2819 else if (IS_GM45(dev_priv))
2820 dev_priv->display.get_cdclk = gm45_get_cdclk;
2821 else if (IS_G45(dev_priv))
2822 dev_priv->display.get_cdclk = g33_get_cdclk;
2823 else if (IS_I965GM(dev_priv))
2824 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2825 else if (IS_I965G(dev_priv))
2826 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2827 else if (IS_PINEVIEW(dev_priv))
2828 dev_priv->display.get_cdclk = pnv_get_cdclk;
2829 else if (IS_G33(dev_priv))
2830 dev_priv->display.get_cdclk = g33_get_cdclk;
2831 else if (IS_I945GM(dev_priv))
2832 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2833 else if (IS_I945G(dev_priv))
2834 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2835 else if (IS_I915GM(dev_priv))
2836 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2837 else if (IS_I915G(dev_priv))
2838 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2839 else if (IS_I865G(dev_priv))
2840 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2841 else if (IS_I85X(dev_priv))
2842 dev_priv->display.get_cdclk = i85x_get_cdclk;
2843 else if (IS_I845G(dev_priv))
2844 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2845 else {
2846 drm_WARN(&dev_priv->drm, !IS_I830(dev_priv),
2847 "Unknown platform. Assuming 133 MHz CDCLK\n");
2848 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2849 }
2850}
2851