1
2
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4
5
6#include <linux/clk.h>
7#include <linux/mfd/syscon.h>
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/phy/phy.h>
11#include <linux/regmap.h>
12
13#include <drm/bridge/dw_hdmi.h>
14#include <drm/drm_edid.h>
15#include <drm/drm_of.h>
16#include <drm/drm_probe_helper.h>
17#include <drm/drm_simple_kms_helper.h>
18
19#include "rockchip_drm_drv.h"
20#include "rockchip_drm_vop.h"
21
22#define RK3228_GRF_SOC_CON2 0x0408
23#define RK3228_HDMI_SDAIN_MSK BIT(14)
24#define RK3228_HDMI_SCLIN_MSK BIT(13)
25#define RK3228_GRF_SOC_CON6 0x0418
26#define RK3228_HDMI_HPD_VSEL BIT(6)
27#define RK3228_HDMI_SDA_VSEL BIT(5)
28#define RK3228_HDMI_SCL_VSEL BIT(4)
29
30#define RK3288_GRF_SOC_CON6 0x025C
31#define RK3288_HDMI_LCDC_SEL BIT(4)
32#define RK3328_GRF_SOC_CON2 0x0408
33
34#define RK3328_HDMI_SDAIN_MSK BIT(11)
35#define RK3328_HDMI_SCLIN_MSK BIT(10)
36#define RK3328_HDMI_HPD_IOE BIT(2)
37#define RK3328_GRF_SOC_CON3 0x040c
38
39#define RK3328_HDMI_SDA5V_GRF BIT(15)
40#define RK3328_HDMI_SCL5V_GRF BIT(14)
41#define RK3328_HDMI_HPD5V_GRF BIT(13)
42#define RK3328_HDMI_CEC5V_GRF BIT(12)
43#define RK3328_GRF_SOC_CON4 0x0410
44#define RK3328_HDMI_HPD_SARADC BIT(13)
45#define RK3328_HDMI_CEC_5V BIT(11)
46#define RK3328_HDMI_SDA_5V BIT(10)
47#define RK3328_HDMI_SCL_5V BIT(9)
48#define RK3328_HDMI_HPD_5V BIT(8)
49
50#define RK3399_GRF_SOC_CON20 0x6250
51#define RK3399_HDMI_LCDC_SEL BIT(6)
52
53#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
54
55
56
57
58
59
60
61struct rockchip_hdmi_chip_data {
62 int lcdsel_grf_reg;
63 u32 lcdsel_big;
64 u32 lcdsel_lit;
65};
66
67struct rockchip_hdmi {
68 struct device *dev;
69 struct regmap *regmap;
70 struct drm_encoder encoder;
71 const struct rockchip_hdmi_chip_data *chip_data;
72 struct clk *vpll_clk;
73 struct clk *grf_clk;
74 struct dw_hdmi *hdmi;
75 struct phy *phy;
76};
77
78#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
79
80static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
81 {
82 27000000, {
83 { 0x00b3, 0x0000},
84 { 0x2153, 0x0000},
85 { 0x40f3, 0x0000}
86 },
87 }, {
88 36000000, {
89 { 0x00b3, 0x0000},
90 { 0x2153, 0x0000},
91 { 0x40f3, 0x0000}
92 },
93 }, {
94 40000000, {
95 { 0x00b3, 0x0000},
96 { 0x2153, 0x0000},
97 { 0x40f3, 0x0000}
98 },
99 }, {
100 54000000, {
101 { 0x0072, 0x0001},
102 { 0x2142, 0x0001},
103 { 0x40a2, 0x0001},
104 },
105 }, {
106 65000000, {
107 { 0x0072, 0x0001},
108 { 0x2142, 0x0001},
109 { 0x40a2, 0x0001},
110 },
111 }, {
112 66000000, {
113 { 0x013e, 0x0003},
114 { 0x217e, 0x0002},
115 { 0x4061, 0x0002}
116 },
117 }, {
118 74250000, {
119 { 0x0072, 0x0001},
120 { 0x2145, 0x0002},
121 { 0x4061, 0x0002}
122 },
123 }, {
124 83500000, {
125 { 0x0072, 0x0001},
126 },
127 }, {
128 108000000, {
129 { 0x0051, 0x0002},
130 { 0x2145, 0x0002},
131 { 0x4061, 0x0002}
132 },
133 }, {
134 106500000, {
135 { 0x0051, 0x0002},
136 { 0x2145, 0x0002},
137 { 0x4061, 0x0002}
138 },
139 }, {
140 146250000, {
141 { 0x0051, 0x0002},
142 { 0x2145, 0x0002},
143 { 0x4061, 0x0002}
144 },
145 }, {
146 148500000, {
147 { 0x0051, 0x0003},
148 { 0x214c, 0x0003},
149 { 0x4064, 0x0003}
150 },
151 }, {
152 ~0UL, {
153 { 0x00a0, 0x000a },
154 { 0x2001, 0x000f },
155 { 0x4002, 0x000f },
156 },
157 }
158};
159
160static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
161
162 {
163 40000000, { 0x0018, 0x0018, 0x0018 },
164 }, {
165 65000000, { 0x0028, 0x0028, 0x0028 },
166 }, {
167 66000000, { 0x0038, 0x0038, 0x0038 },
168 }, {
169 74250000, { 0x0028, 0x0038, 0x0038 },
170 }, {
171 83500000, { 0x0028, 0x0038, 0x0038 },
172 }, {
173 146250000, { 0x0038, 0x0038, 0x0038 },
174 }, {
175 148500000, { 0x0000, 0x0038, 0x0038 },
176 }, {
177 ~0UL, { 0x0000, 0x0000, 0x0000},
178 }
179};
180
181static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
182
183 { 74250000, 0x8009, 0x0004, 0x0272},
184 { 148500000, 0x802b, 0x0004, 0x028d},
185 { 297000000, 0x8039, 0x0005, 0x028d},
186 { ~0UL, 0x0000, 0x0000, 0x0000}
187};
188
189static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
190{
191 struct device_node *np = hdmi->dev->of_node;
192
193 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
194 if (IS_ERR(hdmi->regmap)) {
195 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
196 return PTR_ERR(hdmi->regmap);
197 }
198
199 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
200 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
201 hdmi->vpll_clk = NULL;
202 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
203 return -EPROBE_DEFER;
204 } else if (IS_ERR(hdmi->vpll_clk)) {
205 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
206 return PTR_ERR(hdmi->vpll_clk);
207 }
208
209 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
210 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
211 hdmi->grf_clk = NULL;
212 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
213 return -EPROBE_DEFER;
214 } else if (IS_ERR(hdmi->grf_clk)) {
215 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
216 return PTR_ERR(hdmi->grf_clk);
217 }
218
219 return 0;
220}
221
222static enum drm_mode_status
223dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
224 const struct drm_display_mode *mode)
225{
226 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
227 int pclk = mode->clock * 1000;
228 bool valid = false;
229 int i;
230
231 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
232 if (pclk == mpll_cfg[i].mpixelclock) {
233 valid = true;
234 break;
235 }
236 }
237
238 return (valid) ? MODE_OK : MODE_BAD;
239}
240
241static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
242{
243}
244
245static bool
246dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
247 const struct drm_display_mode *mode,
248 struct drm_display_mode *adj_mode)
249{
250 return true;
251}
252
253static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
254 struct drm_display_mode *mode,
255 struct drm_display_mode *adj_mode)
256{
257 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
258
259 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
260}
261
262static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
263{
264 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
265 u32 val;
266 int ret;
267
268 if (hdmi->chip_data->lcdsel_grf_reg < 0)
269 return;
270
271 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
272 if (ret)
273 val = hdmi->chip_data->lcdsel_lit;
274 else
275 val = hdmi->chip_data->lcdsel_big;
276
277 ret = clk_prepare_enable(hdmi->grf_clk);
278 if (ret < 0) {
279 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
280 return;
281 }
282
283 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
284 if (ret != 0)
285 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
286
287 clk_disable_unprepare(hdmi->grf_clk);
288 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
289 ret ? "LIT" : "BIG");
290}
291
292static int
293dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
294 struct drm_crtc_state *crtc_state,
295 struct drm_connector_state *conn_state)
296{
297 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
298
299 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
300 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
301
302 return 0;
303}
304
305static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
306 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
307 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
308 .enable = dw_hdmi_rockchip_encoder_enable,
309 .disable = dw_hdmi_rockchip_encoder_disable,
310 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
311};
312
313static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
314 struct drm_display_mode *mode)
315{
316 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
317
318 return phy_power_on(hdmi->phy);
319}
320
321static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
322{
323 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
324
325 phy_power_off(hdmi->phy);
326}
327
328static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
329{
330 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
331
332 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
333
334 regmap_write(hdmi->regmap,
335 RK3228_GRF_SOC_CON6,
336 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
337 RK3228_HDMI_SCL_VSEL,
338 RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
339 RK3228_HDMI_SCL_VSEL));
340
341 regmap_write(hdmi->regmap,
342 RK3228_GRF_SOC_CON2,
343 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
344 RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
345}
346
347static enum drm_connector_status
348dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
349{
350 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
351 enum drm_connector_status status;
352
353 status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
354
355 if (status == connector_status_connected)
356 regmap_write(hdmi->regmap,
357 RK3328_GRF_SOC_CON4,
358 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
359 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
360 else
361 regmap_write(hdmi->regmap,
362 RK3328_GRF_SOC_CON4,
363 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
364 RK3328_HDMI_SCL_5V));
365 return status;
366}
367
368static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
369{
370 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
371
372 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
373
374
375 regmap_write(hdmi->regmap,
376 RK3328_GRF_SOC_CON4,
377 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
378 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
379 RK3328_HDMI_HPD_5V));
380 regmap_write(hdmi->regmap,
381 RK3328_GRF_SOC_CON3,
382 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
383 RK3328_HDMI_HPD5V_GRF |
384 RK3328_HDMI_CEC5V_GRF));
385 regmap_write(hdmi->regmap,
386 RK3328_GRF_SOC_CON2,
387 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
388 RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
389 RK3328_HDMI_HPD_IOE));
390}
391
392static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
393 .init = dw_hdmi_rockchip_genphy_init,
394 .disable = dw_hdmi_rockchip_genphy_disable,
395 .read_hpd = dw_hdmi_phy_read_hpd,
396 .update_hpd = dw_hdmi_phy_update_hpd,
397 .setup_hpd = dw_hdmi_rk3228_setup_hpd,
398};
399
400static struct rockchip_hdmi_chip_data rk3228_chip_data = {
401 .lcdsel_grf_reg = -1,
402};
403
404static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
405 .mode_valid = dw_hdmi_rockchip_mode_valid,
406 .mpll_cfg = rockchip_mpll_cfg,
407 .cur_ctr = rockchip_cur_ctr,
408 .phy_config = rockchip_phy_config,
409 .phy_data = &rk3228_chip_data,
410 .phy_ops = &rk3228_hdmi_phy_ops,
411 .phy_name = "inno_dw_hdmi_phy2",
412 .phy_force_vendor = true,
413};
414
415static struct rockchip_hdmi_chip_data rk3288_chip_data = {
416 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
417 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
418 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
419};
420
421static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
422 .mode_valid = dw_hdmi_rockchip_mode_valid,
423 .mpll_cfg = rockchip_mpll_cfg,
424 .cur_ctr = rockchip_cur_ctr,
425 .phy_config = rockchip_phy_config,
426 .phy_data = &rk3288_chip_data,
427};
428
429static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
430 .init = dw_hdmi_rockchip_genphy_init,
431 .disable = dw_hdmi_rockchip_genphy_disable,
432 .read_hpd = dw_hdmi_rk3328_read_hpd,
433 .update_hpd = dw_hdmi_phy_update_hpd,
434 .setup_hpd = dw_hdmi_rk3328_setup_hpd,
435};
436
437static struct rockchip_hdmi_chip_data rk3328_chip_data = {
438 .lcdsel_grf_reg = -1,
439};
440
441static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
442 .mode_valid = dw_hdmi_rockchip_mode_valid,
443 .mpll_cfg = rockchip_mpll_cfg,
444 .cur_ctr = rockchip_cur_ctr,
445 .phy_config = rockchip_phy_config,
446 .phy_data = &rk3328_chip_data,
447 .phy_ops = &rk3328_hdmi_phy_ops,
448 .phy_name = "inno_dw_hdmi_phy2",
449 .phy_force_vendor = true,
450 .use_drm_infoframe = true,
451};
452
453static struct rockchip_hdmi_chip_data rk3399_chip_data = {
454 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
455 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
456 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
457};
458
459static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
460 .mode_valid = dw_hdmi_rockchip_mode_valid,
461 .mpll_cfg = rockchip_mpll_cfg,
462 .cur_ctr = rockchip_cur_ctr,
463 .phy_config = rockchip_phy_config,
464 .phy_data = &rk3399_chip_data,
465 .use_drm_infoframe = true,
466};
467
468static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
469 { .compatible = "rockchip,rk3228-dw-hdmi",
470 .data = &rk3228_hdmi_drv_data
471 },
472 { .compatible = "rockchip,rk3288-dw-hdmi",
473 .data = &rk3288_hdmi_drv_data
474 },
475 { .compatible = "rockchip,rk3328-dw-hdmi",
476 .data = &rk3328_hdmi_drv_data
477 },
478 { .compatible = "rockchip,rk3399-dw-hdmi",
479 .data = &rk3399_hdmi_drv_data
480 },
481 {},
482};
483MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
484
485static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
486 void *data)
487{
488 struct platform_device *pdev = to_platform_device(dev);
489 struct dw_hdmi_plat_data *plat_data;
490 const struct of_device_id *match;
491 struct drm_device *drm = data;
492 struct drm_encoder *encoder;
493 struct rockchip_hdmi *hdmi;
494 int ret;
495
496 if (!pdev->dev.of_node)
497 return -ENODEV;
498
499 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
500 if (!hdmi)
501 return -ENOMEM;
502
503 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
504 plat_data = devm_kmemdup(&pdev->dev, match->data,
505 sizeof(*plat_data), GFP_KERNEL);
506 if (!plat_data)
507 return -ENOMEM;
508
509 hdmi->dev = &pdev->dev;
510 hdmi->chip_data = plat_data->phy_data;
511 plat_data->phy_data = hdmi;
512 encoder = &hdmi->encoder;
513
514 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
515
516
517
518
519
520
521 if (encoder->possible_crtcs == 0)
522 return -EPROBE_DEFER;
523
524 ret = rockchip_hdmi_parse_dt(hdmi);
525 if (ret) {
526 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
527 return ret;
528 }
529
530 ret = clk_prepare_enable(hdmi->vpll_clk);
531 if (ret) {
532 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
533 ret);
534 return ret;
535 }
536
537 hdmi->phy = devm_phy_optional_get(dev, "hdmi");
538 if (IS_ERR(hdmi->phy)) {
539 ret = PTR_ERR(hdmi->phy);
540 if (ret != -EPROBE_DEFER)
541 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
542 return ret;
543 }
544
545 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
546 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
547
548 platform_set_drvdata(pdev, hdmi);
549
550 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
551
552
553
554
555
556 if (IS_ERR(hdmi->hdmi)) {
557 ret = PTR_ERR(hdmi->hdmi);
558 drm_encoder_cleanup(encoder);
559 clk_disable_unprepare(hdmi->vpll_clk);
560 }
561
562 return ret;
563}
564
565static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
566 void *data)
567{
568 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
569
570 dw_hdmi_unbind(hdmi->hdmi);
571 clk_disable_unprepare(hdmi->vpll_clk);
572}
573
574static const struct component_ops dw_hdmi_rockchip_ops = {
575 .bind = dw_hdmi_rockchip_bind,
576 .unbind = dw_hdmi_rockchip_unbind,
577};
578
579static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
580{
581 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
582}
583
584static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
585{
586 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
587
588 return 0;
589}
590
591static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev)
592{
593 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
594
595 dw_hdmi_resume(hdmi->hdmi);
596
597 return 0;
598}
599
600static const struct dev_pm_ops dw_hdmi_rockchip_pm = {
601 SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume)
602};
603
604struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
605 .probe = dw_hdmi_rockchip_probe,
606 .remove = dw_hdmi_rockchip_remove,
607 .driver = {
608 .name = "dwhdmi-rockchip",
609 .pm = &dw_hdmi_rockchip_pm,
610 .of_match_table = dw_hdmi_rockchip_dt_ids,
611 },
612};
613
