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39#ifndef __BNXT_QPLIB_RES_H__
40#define __BNXT_QPLIB_RES_H__
41
42extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
43
44#define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *))
45#define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1)
46#define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
47#define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG)
48
49#define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1))
50
51#define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \
52 ((HWQ_CMP(hwq->prod, hwq)\
53 - HWQ_CMP(hwq->cons, hwq))\
54 & (hwq->max_elements - 1)))
55enum bnxt_qplib_hwq_type {
56 HWQ_TYPE_CTX,
57 HWQ_TYPE_QUEUE,
58 HWQ_TYPE_L2_CMPL,
59 HWQ_TYPE_MR
60};
61
62#define MAX_PBL_LVL_0_PGS 1
63#define MAX_PBL_LVL_1_PGS 512
64#define MAX_PBL_LVL_1_PGS_SHIFT 9
65#define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
66#define MAX_PBL_LVL_2_PGS (256 * 512)
67#define MAX_PDL_LVL_SHIFT 9
68
69enum bnxt_qplib_pbl_lvl {
70 PBL_LVL_0,
71 PBL_LVL_1,
72 PBL_LVL_2,
73 PBL_LVL_MAX
74};
75
76#define ROCE_PG_SIZE_4K (4 * 1024)
77#define ROCE_PG_SIZE_8K (8 * 1024)
78#define ROCE_PG_SIZE_64K (64 * 1024)
79#define ROCE_PG_SIZE_2M (2 * 1024 * 1024)
80#define ROCE_PG_SIZE_8M (8 * 1024 * 1024)
81#define ROCE_PG_SIZE_1G (1024 * 1024 * 1024)
82
83enum bnxt_qplib_hwrm_pg_size {
84 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0,
85 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1,
86 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2,
87 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3,
88 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4,
89 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5,
90};
91
92struct bnxt_qplib_reg_desc {
93 u8 bar_id;
94 resource_size_t bar_base;
95 void __iomem *bar_reg;
96 size_t len;
97};
98
99struct bnxt_qplib_pbl {
100 u32 pg_count;
101 u32 pg_size;
102 void **pg_arr;
103 dma_addr_t *pg_map_arr;
104};
105
106struct bnxt_qplib_sg_info {
107 struct scatterlist *sghead;
108 u32 nmap;
109 u32 npages;
110 u32 pgshft;
111 u32 pgsize;
112 bool nopte;
113};
114
115struct bnxt_qplib_hwq_attr {
116 struct bnxt_qplib_res *res;
117 struct bnxt_qplib_sg_info *sginfo;
118 enum bnxt_qplib_hwq_type type;
119 u32 depth;
120 u32 stride;
121 u32 aux_stride;
122 u32 aux_depth;
123};
124
125struct bnxt_qplib_hwq {
126 struct pci_dev *pdev;
127
128 spinlock_t lock;
129 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1];
130 enum bnxt_qplib_pbl_lvl level;
131
132 void **pbl_ptr;
133
134 dma_addr_t *pbl_dma_ptr;
135 u32 max_elements;
136 u32 depth;
137 u16 element_size;
138 u16 qe_ppg;
139
140 u32 prod;
141 u32 cons;
142 u8 cp_bit;
143 u8 is_user;
144};
145
146struct bnxt_qplib_db_info {
147 void __iomem *db;
148 void __iomem *priv_db;
149 struct bnxt_qplib_hwq *hwq;
150 u32 xid;
151};
152
153
154struct bnxt_qplib_pd_tbl {
155 unsigned long *tbl;
156 u32 max;
157};
158
159struct bnxt_qplib_sgid_tbl {
160 struct bnxt_qplib_gid_info *tbl;
161 u16 *hw_id;
162 u16 max;
163 u16 active;
164 void *ctx;
165 u8 *vlan;
166};
167
168struct bnxt_qplib_pkey_tbl {
169 u16 *tbl;
170 u16 max;
171 u16 active;
172};
173
174struct bnxt_qplib_dpi {
175 u32 dpi;
176 void __iomem *dbr;
177 u64 umdbr;
178};
179
180struct bnxt_qplib_dpi_tbl {
181 void **app_tbl;
182 unsigned long *tbl;
183 u16 max;
184 void __iomem *dbr_bar_reg_iomem;
185 u64 unmapped_dbr;
186};
187
188struct bnxt_qplib_stats {
189 dma_addr_t dma_map;
190 void *dma;
191 u32 size;
192 u32 fw_id;
193};
194
195struct bnxt_qplib_vf_res {
196 u32 max_qp_per_vf;
197 u32 max_mrw_per_vf;
198 u32 max_srq_per_vf;
199 u32 max_cq_per_vf;
200 u32 max_gid_per_vf;
201};
202
203#define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448
204#define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64
205#define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64
206#define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128
207
208#define MAX_TQM_ALLOC_REQ 48
209#define MAX_TQM_ALLOC_BLK_SIZE 8
210struct bnxt_qplib_tqm_ctx {
211 struct bnxt_qplib_hwq pde;
212 u8 pde_level;
213 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ];
214 u8 qcount[MAX_TQM_ALLOC_REQ];
215};
216
217struct bnxt_qplib_ctx {
218 u32 qpc_count;
219 struct bnxt_qplib_hwq qpc_tbl;
220 u32 mrw_count;
221 struct bnxt_qplib_hwq mrw_tbl;
222 u32 srqc_count;
223 struct bnxt_qplib_hwq srqc_tbl;
224 u32 cq_count;
225 struct bnxt_qplib_hwq cq_tbl;
226 struct bnxt_qplib_hwq tim_tbl;
227 struct bnxt_qplib_tqm_ctx tqm_ctx;
228 struct bnxt_qplib_stats stats;
229 struct bnxt_qplib_vf_res vf_res;
230 u64 hwrm_intf_ver;
231};
232
233struct bnxt_qplib_chip_ctx {
234 u16 chip_num;
235 u8 chip_rev;
236 u8 chip_metal;
237};
238
239#define CHIP_NUM_57508 0x1750
240#define CHIP_NUM_57504 0x1751
241#define CHIP_NUM_57502 0x1752
242
243struct bnxt_qplib_res {
244 struct pci_dev *pdev;
245 struct bnxt_qplib_chip_ctx *cctx;
246 struct net_device *netdev;
247
248 struct bnxt_qplib_rcfw *rcfw;
249 struct bnxt_qplib_pd_tbl pd_tbl;
250 struct bnxt_qplib_sgid_tbl sgid_tbl;
251 struct bnxt_qplib_pkey_tbl pkey_tbl;
252 struct bnxt_qplib_dpi_tbl dpi_tbl;
253 bool prio;
254};
255
256static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
257{
258 return (cctx->chip_num == CHIP_NUM_57508 ||
259 cctx->chip_num == CHIP_NUM_57504 ||
260 cctx->chip_num == CHIP_NUM_57502);
261}
262
263static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
264{
265 return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
266 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
267}
268
269static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
270{
271 return bnxt_qplib_is_chip_gen_p5(cctx) ?
272 RING_ALLOC_REQ_RING_TYPE_NQ :
273 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
274}
275
276static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
277{
278 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
279 struct bnxt_qplib_pbl *pbl;
280
281 pbl = &hwq->pbl[PBL_LVL_0];
282 switch (pbl->pg_size) {
283 case ROCE_PG_SIZE_4K:
284 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
285 break;
286 case ROCE_PG_SIZE_8K:
287 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
288 break;
289 case ROCE_PG_SIZE_64K:
290 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
291 break;
292 case ROCE_PG_SIZE_2M:
293 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
294 break;
295 case ROCE_PG_SIZE_8M:
296 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
297 break;
298 case ROCE_PG_SIZE_1G:
299 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
300 break;
301 default:
302 break;
303 }
304
305 return pg_size;
306}
307
308static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
309 u32 indx, u64 *pg)
310{
311 u32 pg_num, pg_idx;
312
313 pg_num = (indx / hwq->qe_ppg);
314 pg_idx = (indx % hwq->qe_ppg);
315 if (pg)
316 *pg = (u64)&hwq->pbl_ptr[pg_num];
317 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
318}
319
320#define to_bnxt_qplib(ptr, type, member) \
321 container_of(ptr, type, member)
322
323struct bnxt_qplib_pd;
324struct bnxt_qplib_dev_attr;
325
326void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
327 struct bnxt_qplib_hwq *hwq);
328int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
329 struct bnxt_qplib_hwq_attr *hwq_attr);
330void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
331int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
332 struct bnxt_qplib_pd *pd);
333int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
334 struct bnxt_qplib_pd_tbl *pd_tbl,
335 struct bnxt_qplib_pd *pd);
336int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
337 struct bnxt_qplib_dpi *dpi,
338 void *app);
339int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
340 struct bnxt_qplib_dpi_tbl *dpi_tbl,
341 struct bnxt_qplib_dpi *dpi);
342void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
343int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
344void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
345int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
346 struct net_device *netdev,
347 struct bnxt_qplib_dev_attr *dev_attr);
348void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
349 struct bnxt_qplib_ctx *ctx);
350int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
351 struct bnxt_qplib_ctx *ctx,
352 bool virt_fn, bool is_p5);
353
354static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
355 bool arm)
356{
357 u32 key;
358
359 key = info->hwq->cons & (info->hwq->max_elements - 1);
360 key |= (CMPL_DOORBELL_IDX_VALID |
361 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
362 if (!arm)
363 key |= CMPL_DOORBELL_MASK;
364 writel(key, info->db);
365}
366
367static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
368 u32 type)
369{
370 u64 key = 0;
371
372 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
373 key <<= 32;
374 key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
375 DBC_DBC_INDEX_MASK;
376 writeq(key, info->db);
377}
378
379static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
380 u32 type)
381{
382 u64 key = 0;
383
384 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
385 key <<= 32;
386 key |= (info->hwq->prod & (info->hwq->max_elements - 1)) &
387 DBC_DBC_INDEX_MASK;
388 writeq(key, info->db);
389}
390
391static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
392 u32 type)
393{
394 u64 key = 0;
395
396 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
397 key <<= 32;
398 writeq(key, info->priv_db);
399}
400
401static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
402 u32 th)
403{
404 u64 key = 0;
405
406 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
407 key <<= 32;
408 key |= th & DBC_DBC_INDEX_MASK;
409 writeq(key, info->priv_db);
410}
411
412static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
413 struct bnxt_qplib_chip_ctx *cctx,
414 bool arm)
415{
416 u32 type;
417
418 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
419 if (bnxt_qplib_is_chip_gen_p5(cctx))
420 bnxt_qplib_ring_db(info, type);
421 else
422 bnxt_qplib_ring_db32(info, arm);
423}
424#endif
425
