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5
6#ifndef _SIW_H
7#define _SIW_H
8
9#include <rdma/ib_verbs.h>
10#include <rdma/restrack.h>
11#include <linux/socket.h>
12#include <linux/skbuff.h>
13#include <crypto/hash.h>
14#include <linux/crc32.h>
15#include <linux/crc32c.h>
16
17#include <rdma/siw-abi.h>
18#include "iwarp.h"
19
20#define SIW_VENDOR_ID 0x626d74
21#define SIW_VENDORT_PART_ID 0
22#define SIW_MAX_QP (1024 * 100)
23#define SIW_MAX_QP_WR (1024 * 32)
24#define SIW_MAX_ORD_QP 128
25#define SIW_MAX_IRD_QP 128
26#define SIW_MAX_SGE_PBL 256
27#define SIW_MAX_SGE_RD 1
28#define SIW_MAX_CQ (1024 * 100)
29#define SIW_MAX_CQE (SIW_MAX_QP_WR * 100)
30#define SIW_MAX_MR (SIW_MAX_QP * 10)
31#define SIW_MAX_PD SIW_MAX_QP
32#define SIW_MAX_MW 0
33#define SIW_MAX_SRQ SIW_MAX_QP
34#define SIW_MAX_SRQ_WR (SIW_MAX_QP_WR * 10)
35#define SIW_MAX_CONTEXT SIW_MAX_PD
36
37
38#define SENDPAGE_THRESH PAGE_SIZE
39
40
41#define SQ_USER_MAXBURST 100
42
43
44
45
46
47#define SIW_IRQ_MAXBURST_SQ_ACTIVE 4
48
49struct siw_dev_cap {
50 int max_qp;
51 int max_qp_wr;
52 int max_ord;
53 int max_ird;
54 int max_sge;
55 int max_sge_rd;
56 int max_cq;
57 int max_cqe;
58 int max_mr;
59 int max_pd;
60 int max_mw;
61 int max_srq;
62 int max_srq_wr;
63 int max_srq_sge;
64};
65
66struct siw_pd {
67 struct ib_pd base_pd;
68};
69
70struct siw_device {
71 struct ib_device base_dev;
72 struct device_dma_parameters dma_parms;
73 struct net_device *netdev;
74 struct siw_dev_cap attrs;
75
76 u32 vendor_part_id;
77 int numa_node;
78
79
80 enum ib_port_state state;
81
82 spinlock_t lock;
83
84 struct xarray qp_xa;
85 struct xarray mem_xa;
86
87 struct list_head cep_list;
88 struct list_head qp_list;
89
90
91 atomic_t num_qp;
92 atomic_t num_cq;
93 atomic_t num_pd;
94 atomic_t num_mr;
95 atomic_t num_srq;
96 atomic_t num_ctx;
97
98 struct work_struct netdev_down;
99};
100
101struct siw_ucontext {
102 struct ib_ucontext base_ucontext;
103 struct siw_device *sdev;
104};
105
106
107
108
109
110#define IWARP_ACCESS_MASK \
111 (IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE | \
112 IB_ACCESS_REMOTE_READ)
113
114
115
116
117
118
119struct siw_page_chunk {
120 struct page **plist;
121};
122
123struct siw_umem {
124 struct siw_page_chunk *page_chunk;
125 int num_pages;
126 bool writable;
127 u64 fp_addr;
128 struct mm_struct *owning_mm;
129};
130
131struct siw_pble {
132 dma_addr_t addr;
133 unsigned int size;
134 unsigned long pbl_off;
135};
136
137struct siw_pbl {
138 unsigned int num_buf;
139 unsigned int max_buf;
140 struct siw_pble pbe[];
141};
142
143
144
145
146
147struct siw_mem {
148 struct siw_device *sdev;
149 struct kref ref;
150 u64 va;
151 u64 len;
152 u32 stag;
153 u8 stag_valid;
154 u8 is_pbl;
155 u8 is_mw;
156 enum ib_access_flags perms;
157 union {
158 struct siw_umem *umem;
159 struct siw_pbl *pbl;
160 void *mem_obj;
161 };
162 struct ib_pd *pd;
163};
164
165struct siw_mr {
166 struct ib_mr base_mr;
167 struct siw_mem *mem;
168 struct rcu_head rcu;
169};
170
171
172
173
174
175enum siw_access_state {
176 E_ACCESS_OK,
177 E_STAG_INVALID,
178 E_BASE_BOUNDS,
179 E_ACCESS_PERM,
180 E_PD_MISMATCH
181};
182
183enum siw_wr_state {
184 SIW_WR_IDLE,
185 SIW_WR_QUEUED,
186 SIW_WR_INPROGRESS
187};
188
189
190struct siw_wqe {
191
192 union {
193 struct siw_sqe sqe;
194 struct siw_rqe rqe;
195 };
196 struct siw_mem *mem[SIW_MAX_SGE];
197 enum siw_wr_state wr_status;
198 enum siw_wc_status wc_status;
199 u32 bytes;
200 u32 processed;
201};
202
203struct siw_cq {
204 struct ib_cq base_cq;
205 spinlock_t lock;
206 struct siw_cq_ctrl *notify;
207 struct siw_cqe *queue;
208 u32 cq_put;
209 u32 cq_get;
210 u32 num_cqe;
211 struct rdma_user_mmap_entry *cq_entry;
212 u32 id;
213};
214
215enum siw_qp_state {
216 SIW_QP_STATE_IDLE,
217 SIW_QP_STATE_RTR,
218 SIW_QP_STATE_RTS,
219 SIW_QP_STATE_CLOSING,
220 SIW_QP_STATE_TERMINATE,
221 SIW_QP_STATE_ERROR,
222 SIW_QP_STATE_COUNT
223};
224
225enum siw_qp_flags {
226 SIW_RDMA_BIND_ENABLED = (1 << 0),
227 SIW_RDMA_WRITE_ENABLED = (1 << 1),
228 SIW_RDMA_READ_ENABLED = (1 << 2),
229 SIW_SIGNAL_ALL_WR = (1 << 3),
230 SIW_MPA_CRC = (1 << 4),
231 SIW_QP_IN_DESTROY = (1 << 5)
232};
233
234enum siw_qp_attr_mask {
235 SIW_QP_ATTR_STATE = (1 << 0),
236 SIW_QP_ATTR_ACCESS_FLAGS = (1 << 1),
237 SIW_QP_ATTR_LLP_HANDLE = (1 << 2),
238 SIW_QP_ATTR_ORD = (1 << 3),
239 SIW_QP_ATTR_IRD = (1 << 4),
240 SIW_QP_ATTR_SQ_SIZE = (1 << 5),
241 SIW_QP_ATTR_RQ_SIZE = (1 << 6),
242 SIW_QP_ATTR_MPA = (1 << 7)
243};
244
245struct siw_srq {
246 struct ib_srq base_srq;
247 spinlock_t lock;
248 u32 max_sge;
249 u32 limit;
250 struct siw_rqe *recvq;
251 u32 rq_put;
252 u32 rq_get;
253 u32 num_rqe;
254 struct rdma_user_mmap_entry *srq_entry;
255 bool armed:1;
256 bool is_kernel_res:1;
257};
258
259struct siw_qp_attrs {
260 enum siw_qp_state state;
261 u32 sq_size;
262 u32 rq_size;
263 u32 orq_size;
264 u32 irq_size;
265 u32 sq_max_sges;
266 u32 rq_max_sges;
267 enum siw_qp_flags flags;
268
269 struct socket *sk;
270};
271
272enum siw_tx_ctx {
273 SIW_SEND_HDR,
274 SIW_SEND_DATA,
275 SIW_SEND_TRAILER,
276 SIW_SEND_SHORT_FPDU
277};
278
279enum siw_rx_state {
280 SIW_GET_HDR,
281 SIW_GET_DATA_START,
282 SIW_GET_DATA_MORE,
283 SIW_GET_TRAILER
284};
285
286struct siw_rx_stream {
287 struct sk_buff *skb;
288 int skb_new;
289 int skb_offset;
290 int skb_copied;
291
292 union iwarp_hdr hdr;
293 struct mpa_trailer trailer;
294
295 enum siw_rx_state state;
296
297
298
299
300
301
302
303
304 int fpdu_part_rcvd;
305 int fpdu_part_rem;
306
307
308
309
310
311
312 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT];
313 u32 ddp_stag;
314 u64 ddp_to;
315 u32 inval_stag;
316
317 struct shash_desc *mpa_crc_hd;
318 u8 rx_suspend : 1;
319 u8 pad : 2;
320 u8 rdmap_op : 4;
321};
322
323struct siw_rx_fpdu {
324
325
326
327
328 struct siw_wqe wqe_active;
329
330 unsigned int pbl_idx;
331 unsigned int sge_idx;
332 unsigned int sge_off;
333
334 char first_ddp_seg;
335 char more_ddp_segs;
336 u8 prev_rdmap_op : 4;
337};
338
339
340
341
342
343struct siw_send_pkt {
344 struct iwarp_send send;
345 __be32 crc;
346};
347
348struct siw_write_pkt {
349 struct iwarp_rdma_write write;
350 __be32 crc;
351};
352
353struct siw_rreq_pkt {
354 struct iwarp_rdma_rreq rreq;
355 __be32 crc;
356};
357
358struct siw_rresp_pkt {
359 struct iwarp_rdma_rresp rresp;
360 __be32 crc;
361};
362
363struct siw_iwarp_tx {
364 union {
365 union iwarp_hdr hdr;
366
367
368 struct iwarp_ctrl ctrl;
369 struct iwarp_ctrl_untagged c_untagged;
370 struct iwarp_ctrl_tagged c_tagged;
371
372
373 struct iwarp_rdma_write rwrite;
374 struct iwarp_rdma_rreq rreq;
375 struct iwarp_rdma_rresp rresp;
376 struct iwarp_terminate terminate;
377 struct iwarp_send send;
378 struct iwarp_send_inv send_inv;
379
380
381 struct siw_send_pkt send_pkt;
382 struct siw_write_pkt write_pkt;
383 struct siw_rreq_pkt rreq_pkt;
384 struct siw_rresp_pkt rresp_pkt;
385 } pkt;
386
387 struct mpa_trailer trailer;
388
389 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT];
390
391 enum siw_tx_ctx state;
392 u16 ctrl_len;
393 u16 ctrl_sent;
394 int burst;
395 int bytes_unsent;
396
397 struct shash_desc *mpa_crc_hd;
398
399 u8 do_crc : 1;
400 u8 use_sendpage : 1;
401 u8 tx_suspend : 1;
402 u8 pad : 2;
403 u8 orq_fence : 1;
404 u8 in_syscall : 1;
405 u8 zcopy_tx : 1;
406 u8 gso_seg_limit;
407
408 u16 fpdu_len;
409 unsigned int tcp_seglen;
410
411 struct siw_wqe wqe_active;
412
413 int pbl_idx;
414 int sge_idx;
415 u32 sge_off;
416};
417
418struct siw_qp {
419 struct ib_qp base_qp;
420 struct siw_device *sdev;
421 struct kref ref;
422 struct list_head devq;
423 int tx_cpu;
424 struct siw_qp_attrs attrs;
425
426 struct siw_cep *cep;
427 struct rw_semaphore state_lock;
428
429 struct ib_pd *pd;
430 struct siw_cq *scq;
431 struct siw_cq *rcq;
432 struct siw_srq *srq;
433
434 struct siw_iwarp_tx tx_ctx;
435 spinlock_t sq_lock;
436 struct siw_sqe *sendq;
437 uint32_t sq_get;
438 uint32_t sq_put;
439 struct llist_node tx_list;
440
441 struct siw_sqe *orq;
442 spinlock_t orq_lock;
443 uint32_t orq_get;
444 uint32_t orq_put;
445
446 struct siw_rx_stream rx_stream;
447 struct siw_rx_fpdu *rx_fpdu;
448 struct siw_rx_fpdu rx_tagged;
449 struct siw_rx_fpdu rx_untagged;
450 spinlock_t rq_lock;
451 struct siw_rqe *recvq;
452 uint32_t rq_get;
453 uint32_t rq_put;
454
455 struct siw_sqe *irq;
456 uint32_t irq_get;
457 uint32_t irq_put;
458 int irq_burst;
459
460 struct {
461 u8 valid;
462 u8 in_tx;
463 u8 layer : 4, etype : 4;
464 u8 ecode;
465 } term_info;
466 struct rdma_user_mmap_entry *sq_entry;
467 struct rdma_user_mmap_entry *rq_entry;
468 struct rcu_head rcu;
469};
470
471
472#define rx_qp(rx) container_of(rx, struct siw_qp, rx_stream)
473#define tx_qp(tx) container_of(tx, struct siw_qp, tx_ctx)
474#define tx_wqe(qp) (&(qp)->tx_ctx.wqe_active)
475#define rx_wqe(rctx) (&(rctx)->wqe_active)
476#define rx_mem(rctx) ((rctx)->wqe_active.mem[0])
477#define tx_type(wqe) ((wqe)->sqe.opcode)
478#define rx_type(wqe) ((wqe)->rqe.opcode)
479#define tx_flags(wqe) ((wqe)->sqe.flags)
480
481struct iwarp_msg_info {
482 int hdr_len;
483 struct iwarp_ctrl ctrl;
484 int (*rx_data)(struct siw_qp *qp);
485};
486
487struct siw_user_mmap_entry {
488 struct rdma_user_mmap_entry rdma_entry;
489 void *address;
490};
491
492
493extern const bool zcopy_tx;
494extern const bool try_gso;
495extern const bool loopback_enabled;
496extern const bool mpa_crc_required;
497extern const bool mpa_crc_strict;
498extern const bool siw_tcp_nagle;
499extern u_char mpa_version;
500extern const bool peer_to_peer;
501extern struct task_struct *siw_tx_thread[];
502
503extern struct crypto_shash *siw_crypto_shash;
504extern struct iwarp_msg_info iwarp_pktinfo[RDMAP_TERMINATE + 1];
505
506
507int siw_qp_modify(struct siw_qp *qp, struct siw_qp_attrs *attr,
508 enum siw_qp_attr_mask mask);
509int siw_qp_mpa_rts(struct siw_qp *qp, enum mpa_v2_ctrl ctrl);
510void siw_qp_llp_close(struct siw_qp *qp);
511void siw_qp_cm_drop(struct siw_qp *qp, int schedule);
512void siw_send_terminate(struct siw_qp *qp);
513
514void siw_qp_get_ref(struct ib_qp *qp);
515void siw_qp_put_ref(struct ib_qp *qp);
516int siw_qp_add(struct siw_device *sdev, struct siw_qp *qp);
517void siw_free_qp(struct kref *ref);
518
519void siw_init_terminate(struct siw_qp *qp, enum term_elayer layer,
520 u8 etype, u8 ecode, int in_tx);
521enum ddp_ecode siw_tagged_error(enum siw_access_state state);
522enum rdmap_ecode siw_rdmap_error(enum siw_access_state state);
523
524void siw_read_to_orq(struct siw_sqe *rreq, struct siw_sqe *sqe);
525int siw_sqe_complete(struct siw_qp *qp, struct siw_sqe *sqe, u32 bytes,
526 enum siw_wc_status status);
527int siw_rqe_complete(struct siw_qp *qp, struct siw_rqe *rqe, u32 bytes,
528 u32 inval_stag, enum siw_wc_status status);
529void siw_qp_llp_data_ready(struct sock *sk);
530void siw_qp_llp_write_space(struct sock *sk);
531
532
533int siw_run_sq(void *arg);
534int siw_qp_sq_process(struct siw_qp *qp);
535int siw_sq_start(struct siw_qp *qp);
536int siw_activate_tx(struct siw_qp *qp);
537void siw_stop_tx_thread(int nr_cpu);
538int siw_get_tx_cpu(struct siw_device *sdev);
539void siw_put_tx_cpu(int cpu);
540
541
542int siw_proc_send(struct siw_qp *qp);
543int siw_proc_rreq(struct siw_qp *qp);
544int siw_proc_rresp(struct siw_qp *qp);
545int siw_proc_write(struct siw_qp *qp);
546int siw_proc_terminate(struct siw_qp *qp);
547
548int siw_tcp_rx_data(read_descriptor_t *rd_desc, struct sk_buff *skb,
549 unsigned int off, size_t len);
550
551static inline void set_rx_fpdu_context(struct siw_qp *qp, u8 opcode)
552{
553 if (opcode == RDMAP_RDMA_WRITE || opcode == RDMAP_RDMA_READ_RESP)
554 qp->rx_fpdu = &qp->rx_tagged;
555 else
556 qp->rx_fpdu = &qp->rx_untagged;
557
558 qp->rx_stream.rdmap_op = opcode;
559}
560
561static inline struct siw_ucontext *to_siw_ctx(struct ib_ucontext *base_ctx)
562{
563 return container_of(base_ctx, struct siw_ucontext, base_ucontext);
564}
565
566static inline struct siw_qp *to_siw_qp(struct ib_qp *base_qp)
567{
568 return container_of(base_qp, struct siw_qp, base_qp);
569}
570
571static inline struct siw_cq *to_siw_cq(struct ib_cq *base_cq)
572{
573 return container_of(base_cq, struct siw_cq, base_cq);
574}
575
576static inline struct siw_srq *to_siw_srq(struct ib_srq *base_srq)
577{
578 return container_of(base_srq, struct siw_srq, base_srq);
579}
580
581static inline struct siw_device *to_siw_dev(struct ib_device *base_dev)
582{
583 return container_of(base_dev, struct siw_device, base_dev);
584}
585
586static inline struct siw_mr *to_siw_mr(struct ib_mr *base_mr)
587{
588 return container_of(base_mr, struct siw_mr, base_mr);
589}
590
591static inline struct siw_user_mmap_entry *
592to_siw_mmap_entry(struct rdma_user_mmap_entry *rdma_mmap)
593{
594 return container_of(rdma_mmap, struct siw_user_mmap_entry, rdma_entry);
595}
596
597static inline struct siw_qp *siw_qp_id2obj(struct siw_device *sdev, int id)
598{
599 struct siw_qp *qp;
600
601 rcu_read_lock();
602 qp = xa_load(&sdev->qp_xa, id);
603 if (likely(qp && kref_get_unless_zero(&qp->ref))) {
604 rcu_read_unlock();
605 return qp;
606 }
607 rcu_read_unlock();
608 return NULL;
609}
610
611static inline u32 qp_id(struct siw_qp *qp)
612{
613 return qp->base_qp.qp_num;
614}
615
616static inline void siw_qp_get(struct siw_qp *qp)
617{
618 kref_get(&qp->ref);
619}
620
621static inline void siw_qp_put(struct siw_qp *qp)
622{
623 kref_put(&qp->ref, siw_free_qp);
624}
625
626static inline int siw_sq_empty(struct siw_qp *qp)
627{
628 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size];
629
630 return READ_ONCE(sqe->flags) == 0;
631}
632
633static inline struct siw_sqe *sq_get_next(struct siw_qp *qp)
634{
635 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size];
636
637 if (READ_ONCE(sqe->flags) & SIW_WQE_VALID)
638 return sqe;
639
640 return NULL;
641}
642
643static inline struct siw_sqe *orq_get_current(struct siw_qp *qp)
644{
645 return &qp->orq[qp->orq_get % qp->attrs.orq_size];
646}
647
648static inline struct siw_sqe *orq_get_tail(struct siw_qp *qp)
649{
650 return &qp->orq[qp->orq_put % qp->attrs.orq_size];
651}
652
653static inline struct siw_sqe *orq_get_free(struct siw_qp *qp)
654{
655 struct siw_sqe *orq_e = orq_get_tail(qp);
656
657 if (orq_e && READ_ONCE(orq_e->flags) == 0)
658 return orq_e;
659
660 return NULL;
661}
662
663static inline int siw_orq_empty(struct siw_qp *qp)
664{
665 return qp->orq[qp->orq_get % qp->attrs.orq_size].flags == 0 ? 1 : 0;
666}
667
668static inline struct siw_sqe *irq_alloc_free(struct siw_qp *qp)
669{
670 struct siw_sqe *irq_e = &qp->irq[qp->irq_put % qp->attrs.irq_size];
671
672 if (READ_ONCE(irq_e->flags) == 0) {
673 qp->irq_put++;
674 return irq_e;
675 }
676 return NULL;
677}
678
679static inline __wsum siw_csum_update(const void *buff, int len, __wsum sum)
680{
681 return (__force __wsum)crc32c((__force __u32)sum, buff, len);
682}
683
684static inline __wsum siw_csum_combine(__wsum csum, __wsum csum2, int offset,
685 int len)
686{
687 return (__force __wsum)__crc32c_le_combine((__force __u32)csum,
688 (__force __u32)csum2, len);
689}
690
691static inline void siw_crc_skb(struct siw_rx_stream *srx, unsigned int len)
692{
693 const struct skb_checksum_ops siw_cs_ops = {
694 .update = siw_csum_update,
695 .combine = siw_csum_combine,
696 };
697 __wsum crc = *(u32 *)shash_desc_ctx(srx->mpa_crc_hd);
698
699 crc = __skb_checksum(srx->skb, srx->skb_offset, len, crc,
700 &siw_cs_ops);
701 *(u32 *)shash_desc_ctx(srx->mpa_crc_hd) = crc;
702}
703
704#define siw_dbg(ibdev, fmt, ...) \
705 ibdev_dbg(ibdev, "%s: " fmt, __func__, ##__VA_ARGS__)
706
707#define siw_dbg_qp(qp, fmt, ...) \
708 ibdev_dbg(&qp->sdev->base_dev, "QP[%u] %s: " fmt, qp_id(qp), __func__, \
709 ##__VA_ARGS__)
710
711#define siw_dbg_cq(cq, fmt, ...) \
712 ibdev_dbg(cq->base_cq.device, "CQ[%u] %s: " fmt, cq->id, __func__, \
713 ##__VA_ARGS__)
714
715#define siw_dbg_pd(pd, fmt, ...) \
716 ibdev_dbg(pd->device, "PD[%u] %s: " fmt, pd->res.id, __func__, \
717 ##__VA_ARGS__)
718
719#define siw_dbg_mem(mem, fmt, ...) \
720 ibdev_dbg(&mem->sdev->base_dev, \
721 "MEM[0x%08x] %s: " fmt, mem->stag, __func__, ##__VA_ARGS__)
722
723#define siw_dbg_cep(cep, fmt, ...) \
724 ibdev_dbg(&cep->sdev->base_dev, "CEP[0x%pK] %s: " fmt, \
725 cep, __func__, ##__VA_ARGS__)
726
727void siw_cq_flush(struct siw_cq *cq);
728void siw_sq_flush(struct siw_qp *qp);
729void siw_rq_flush(struct siw_qp *qp);
730int siw_reap_cqe(struct siw_cq *cq, struct ib_wc *wc);
731
732#endif
733