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8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14#include <linux/slab.h>
15#include <linux/of.h>
16#include <linux/gpio/consumer.h>
17#include <linux/videodev2.h>
18#include <media/v4l2-ioctl.h>
19#include <media/v4l2-event.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-ctrls.h>
22#include <linux/mutex.h>
23#include <linux/delay.h>
24
25#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
26#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
27#define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
28#define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
29#define ADV7180_STD_NTSC_J 0x4
30#define ADV7180_STD_NTSC_M 0x5
31#define ADV7180_STD_PAL60 0x6
32#define ADV7180_STD_NTSC_443 0x7
33#define ADV7180_STD_PAL_BG 0x8
34#define ADV7180_STD_PAL_N 0x9
35#define ADV7180_STD_PAL_M 0xa
36#define ADV7180_STD_PAL_M_PED 0xb
37#define ADV7180_STD_PAL_COMB_N 0xc
38#define ADV7180_STD_PAL_COMB_N_PED 0xd
39#define ADV7180_STD_PAL_SECAM 0xe
40#define ADV7180_STD_PAL_SECAM_PED 0xf
41
42#define ADV7180_REG_INPUT_CONTROL 0x0000
43#define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
44
45#define ADV7182_REG_INPUT_VIDSEL 0x0002
46
47#define ADV7180_REG_OUTPUT_CONTROL 0x0003
48#define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
49#define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
50
51#define ADV7180_REG_AUTODETECT_ENABLE 0x0007
52#define ADV7180_AUTODETECT_DEFAULT 0x7f
53
54#define ADV7180_REG_CON 0x0008
55#define ADV7180_CON_MIN 0
56#define ADV7180_CON_DEF 128
57#define ADV7180_CON_MAX 255
58
59#define ADV7180_REG_BRI 0x000a
60#define ADV7180_BRI_MIN -128
61#define ADV7180_BRI_DEF 0
62#define ADV7180_BRI_MAX 127
63
64#define ADV7180_REG_HUE 0x000b
65#define ADV7180_HUE_MIN -127
66#define ADV7180_HUE_DEF 0
67#define ADV7180_HUE_MAX 128
68
69#define ADV7180_REG_CTRL 0x000e
70#define ADV7180_CTRL_IRQ_SPACE 0x20
71
72#define ADV7180_REG_PWR_MAN 0x0f
73#define ADV7180_PWR_MAN_ON 0x04
74#define ADV7180_PWR_MAN_OFF 0x24
75#define ADV7180_PWR_MAN_RES 0x80
76
77#define ADV7180_REG_STATUS1 0x0010
78#define ADV7180_STATUS1_IN_LOCK 0x01
79#define ADV7180_STATUS1_AUTOD_MASK 0x70
80#define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
81#define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
82#define ADV7180_STATUS1_AUTOD_PAL_M 0x20
83#define ADV7180_STATUS1_AUTOD_PAL_60 0x30
84#define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
85#define ADV7180_STATUS1_AUTOD_SECAM 0x50
86#define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
87#define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
88
89#define ADV7180_REG_IDENT 0x0011
90#define ADV7180_ID_7180 0x18
91
92#define ADV7180_REG_STATUS3 0x0013
93#define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
94#define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
95#define ADV7180_REG_CTRL_2 0x001d
96#define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
97#define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
98#define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
99#define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
100#define ADV7180_REG_LOCK_CNT 0x0051
101#define ADV7180_REG_CVBS_TRIM 0x0052
102#define ADV7180_REG_CLAMP_ADJ 0x005a
103#define ADV7180_REG_RES_CIR 0x005f
104#define ADV7180_REG_DIFF_MODE 0x0060
105
106#define ADV7180_REG_ICONF1 0x2040
107#define ADV7180_ICONF1_ACTIVE_LOW 0x01
108#define ADV7180_ICONF1_PSYNC_ONLY 0x10
109#define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
110
111#define ADV7180_REG_SD_SAT_CB 0x00e3
112#define ADV7180_REG_SD_SAT_CR 0x00e4
113#define ADV7180_SAT_MIN 0
114#define ADV7180_SAT_DEF 128
115#define ADV7180_SAT_MAX 255
116
117#define ADV7180_IRQ1_LOCK 0x01
118#define ADV7180_IRQ1_UNLOCK 0x02
119#define ADV7180_REG_ISR1 0x2042
120#define ADV7180_REG_ICR1 0x2043
121#define ADV7180_REG_IMR1 0x2044
122#define ADV7180_REG_IMR2 0x2048
123#define ADV7180_IRQ3_AD_CHANGE 0x08
124#define ADV7180_REG_ISR3 0x204A
125#define ADV7180_REG_ICR3 0x204B
126#define ADV7180_REG_IMR3 0x204C
127#define ADV7180_REG_IMR4 0x2050
128
129#define ADV7180_REG_NTSC_V_BIT_END 0x00E6
130#define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
131
132#define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
133#define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
134
135#define ADV7180_REG_ACE_CTRL1 0x4080
136#define ADV7180_REG_ACE_CTRL5 0x4084
137#define ADV7180_REG_FLCONTROL 0x40e0
138#define ADV7180_FLCONTROL_FL_ENABLE 0x1
139
140#define ADV7180_REG_RST_CLAMP 0x809c
141#define ADV7180_REG_AGC_ADJ1 0x80b6
142#define ADV7180_REG_AGC_ADJ2 0x80c0
143
144#define ADV7180_CSI_REG_PWRDN 0x00
145#define ADV7180_CSI_PWRDN 0x80
146
147#define ADV7180_INPUT_CVBS_AIN1 0x00
148#define ADV7180_INPUT_CVBS_AIN2 0x01
149#define ADV7180_INPUT_CVBS_AIN3 0x02
150#define ADV7180_INPUT_CVBS_AIN4 0x03
151#define ADV7180_INPUT_CVBS_AIN5 0x04
152#define ADV7180_INPUT_CVBS_AIN6 0x05
153#define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
154#define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
155#define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
156#define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
157#define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
158
159#define ADV7182_INPUT_CVBS_AIN1 0x00
160#define ADV7182_INPUT_CVBS_AIN2 0x01
161#define ADV7182_INPUT_CVBS_AIN3 0x02
162#define ADV7182_INPUT_CVBS_AIN4 0x03
163#define ADV7182_INPUT_CVBS_AIN5 0x04
164#define ADV7182_INPUT_CVBS_AIN6 0x05
165#define ADV7182_INPUT_CVBS_AIN7 0x06
166#define ADV7182_INPUT_CVBS_AIN8 0x07
167#define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
168#define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
169#define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
170#define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
171#define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
172#define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
173#define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
174#define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
175#define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
176#define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
177
178#define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
179#define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
180
181#define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
182
183
184#define ADV7180_NUM_OF_SKIP_FRAMES 2
185
186struct adv7180_state;
187
188#define ADV7180_FLAG_RESET_POWERED BIT(0)
189#define ADV7180_FLAG_V2 BIT(1)
190#define ADV7180_FLAG_MIPI_CSI2 BIT(2)
191#define ADV7180_FLAG_I2P BIT(3)
192
193struct adv7180_chip_info {
194 unsigned int flags;
195 unsigned int valid_input_mask;
196 int (*set_std)(struct adv7180_state *st, unsigned int std);
197 int (*select_input)(struct adv7180_state *st, unsigned int input);
198 int (*init)(struct adv7180_state *state);
199};
200
201struct adv7180_state {
202 struct v4l2_ctrl_handler ctrl_hdl;
203 struct v4l2_subdev sd;
204 struct media_pad pad;
205 struct mutex mutex;
206 int irq;
207 struct gpio_desc *pwdn_gpio;
208 v4l2_std_id curr_norm;
209 bool powered;
210 bool streaming;
211 u8 input;
212
213 struct i2c_client *client;
214 unsigned int register_page;
215 struct i2c_client *csi_client;
216 struct i2c_client *vpp_client;
217 const struct adv7180_chip_info *chip_info;
218 enum v4l2_field field;
219};
220#define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
221 struct adv7180_state, \
222 ctrl_hdl)->sd)
223
224static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
225{
226 if (state->register_page != page) {
227 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
228 page);
229 state->register_page = page;
230 }
231
232 return 0;
233}
234
235static int adv7180_write(struct adv7180_state *state, unsigned int reg,
236 unsigned int value)
237{
238 lockdep_assert_held(&state->mutex);
239 adv7180_select_page(state, reg >> 8);
240 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
241}
242
243static int adv7180_read(struct adv7180_state *state, unsigned int reg)
244{
245 lockdep_assert_held(&state->mutex);
246 adv7180_select_page(state, reg >> 8);
247 return i2c_smbus_read_byte_data(state->client, reg & 0xff);
248}
249
250static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
251 unsigned int value)
252{
253 return i2c_smbus_write_byte_data(state->csi_client, reg, value);
254}
255
256static int adv7180_set_video_standard(struct adv7180_state *state,
257 unsigned int std)
258{
259 return state->chip_info->set_std(state, std);
260}
261
262static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
263 unsigned int value)
264{
265 return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
266}
267
268static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
269{
270
271 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
272 return V4L2_STD_UNKNOWN;
273
274 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
275 case ADV7180_STATUS1_AUTOD_NTSM_M_J:
276 return V4L2_STD_NTSC;
277 case ADV7180_STATUS1_AUTOD_NTSC_4_43:
278 return V4L2_STD_NTSC_443;
279 case ADV7180_STATUS1_AUTOD_PAL_M:
280 return V4L2_STD_PAL_M;
281 case ADV7180_STATUS1_AUTOD_PAL_60:
282 return V4L2_STD_PAL_60;
283 case ADV7180_STATUS1_AUTOD_PAL_B_G:
284 return V4L2_STD_PAL;
285 case ADV7180_STATUS1_AUTOD_SECAM:
286 return V4L2_STD_SECAM;
287 case ADV7180_STATUS1_AUTOD_PAL_COMB:
288 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
289 case ADV7180_STATUS1_AUTOD_SECAM_525:
290 return V4L2_STD_SECAM;
291 default:
292 return V4L2_STD_UNKNOWN;
293 }
294}
295
296static int v4l2_std_to_adv7180(v4l2_std_id std)
297{
298 if (std == V4L2_STD_PAL_60)
299 return ADV7180_STD_PAL60;
300 if (std == V4L2_STD_NTSC_443)
301 return ADV7180_STD_NTSC_443;
302 if (std == V4L2_STD_PAL_N)
303 return ADV7180_STD_PAL_N;
304 if (std == V4L2_STD_PAL_M)
305 return ADV7180_STD_PAL_M;
306 if (std == V4L2_STD_PAL_Nc)
307 return ADV7180_STD_PAL_COMB_N;
308
309 if (std & V4L2_STD_PAL)
310 return ADV7180_STD_PAL_BG;
311 if (std & V4L2_STD_NTSC)
312 return ADV7180_STD_NTSC_M;
313 if (std & V4L2_STD_SECAM)
314 return ADV7180_STD_PAL_SECAM;
315
316 return -EINVAL;
317}
318
319static u32 adv7180_status_to_v4l2(u8 status1)
320{
321 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
322 return V4L2_IN_ST_NO_SIGNAL;
323
324 return 0;
325}
326
327static int __adv7180_status(struct adv7180_state *state, u32 *status,
328 v4l2_std_id *std)
329{
330 int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
331
332 if (status1 < 0)
333 return status1;
334
335 if (status)
336 *status = adv7180_status_to_v4l2(status1);
337 if (std)
338 *std = adv7180_std_to_v4l2(status1);
339
340 return 0;
341}
342
343static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
344{
345 return container_of(sd, struct adv7180_state, sd);
346}
347
348static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
349{
350 struct adv7180_state *state = to_state(sd);
351 int err = mutex_lock_interruptible(&state->mutex);
352 if (err)
353 return err;
354
355 if (state->streaming) {
356 err = -EBUSY;
357 goto unlock;
358 }
359
360 err = adv7180_set_video_standard(state,
361 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
362 if (err)
363 goto unlock;
364
365 msleep(100);
366 __adv7180_status(state, NULL, std);
367
368 err = v4l2_std_to_adv7180(state->curr_norm);
369 if (err < 0)
370 goto unlock;
371
372 err = adv7180_set_video_standard(state, err);
373
374unlock:
375 mutex_unlock(&state->mutex);
376 return err;
377}
378
379static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
380 u32 output, u32 config)
381{
382 struct adv7180_state *state = to_state(sd);
383 int ret = mutex_lock_interruptible(&state->mutex);
384
385 if (ret)
386 return ret;
387
388 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
389 ret = -EINVAL;
390 goto out;
391 }
392
393 ret = state->chip_info->select_input(state, input);
394
395 if (ret == 0)
396 state->input = input;
397out:
398 mutex_unlock(&state->mutex);
399 return ret;
400}
401
402static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
403{
404 struct adv7180_state *state = to_state(sd);
405 int ret = mutex_lock_interruptible(&state->mutex);
406 if (ret)
407 return ret;
408
409 ret = __adv7180_status(state, status, NULL);
410 mutex_unlock(&state->mutex);
411 return ret;
412}
413
414static int adv7180_program_std(struct adv7180_state *state)
415{
416 int ret;
417
418 ret = v4l2_std_to_adv7180(state->curr_norm);
419 if (ret < 0)
420 return ret;
421
422 ret = adv7180_set_video_standard(state, ret);
423 if (ret < 0)
424 return ret;
425 return 0;
426}
427
428static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
429{
430 struct adv7180_state *state = to_state(sd);
431 int ret = mutex_lock_interruptible(&state->mutex);
432
433 if (ret)
434 return ret;
435
436
437 ret = v4l2_std_to_adv7180(std);
438 if (ret < 0)
439 goto out;
440
441 state->curr_norm = std;
442
443 ret = adv7180_program_std(state);
444out:
445 mutex_unlock(&state->mutex);
446 return ret;
447}
448
449static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
450{
451 struct adv7180_state *state = to_state(sd);
452
453 *norm = state->curr_norm;
454
455 return 0;
456}
457
458static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
459 struct v4l2_subdev_frame_interval *fi)
460{
461 struct adv7180_state *state = to_state(sd);
462
463 if (state->curr_norm & V4L2_STD_525_60) {
464 fi->interval.numerator = 1001;
465 fi->interval.denominator = 30000;
466 } else {
467 fi->interval.numerator = 1;
468 fi->interval.denominator = 25;
469 }
470
471 return 0;
472}
473
474static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
475{
476 if (!state->pwdn_gpio)
477 return;
478
479 if (on) {
480 gpiod_set_value_cansleep(state->pwdn_gpio, 0);
481 usleep_range(5000, 10000);
482 } else {
483 gpiod_set_value_cansleep(state->pwdn_gpio, 1);
484 }
485}
486
487static int adv7180_set_power(struct adv7180_state *state, bool on)
488{
489 u8 val;
490 int ret;
491
492 if (on)
493 val = ADV7180_PWR_MAN_ON;
494 else
495 val = ADV7180_PWR_MAN_OFF;
496
497 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
498 if (ret)
499 return ret;
500
501 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
502 if (on) {
503 adv7180_csi_write(state, 0xDE, 0x02);
504 adv7180_csi_write(state, 0xD2, 0xF7);
505 adv7180_csi_write(state, 0xD8, 0x65);
506 adv7180_csi_write(state, 0xE0, 0x09);
507 adv7180_csi_write(state, 0x2C, 0x00);
508 if (state->field == V4L2_FIELD_NONE)
509 adv7180_csi_write(state, 0x1D, 0x80);
510 adv7180_csi_write(state, 0x00, 0x00);
511 } else {
512 adv7180_csi_write(state, 0x00, 0x80);
513 }
514 }
515
516 return 0;
517}
518
519static int adv7180_s_power(struct v4l2_subdev *sd, int on)
520{
521 struct adv7180_state *state = to_state(sd);
522 int ret;
523
524 ret = mutex_lock_interruptible(&state->mutex);
525 if (ret)
526 return ret;
527
528 ret = adv7180_set_power(state, on);
529 if (ret == 0)
530 state->powered = on;
531
532 mutex_unlock(&state->mutex);
533 return ret;
534}
535
536static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
537{
538 struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
539 struct adv7180_state *state = to_state(sd);
540 int ret = mutex_lock_interruptible(&state->mutex);
541 int val;
542
543 if (ret)
544 return ret;
545 val = ctrl->val;
546 switch (ctrl->id) {
547 case V4L2_CID_BRIGHTNESS:
548 ret = adv7180_write(state, ADV7180_REG_BRI, val);
549 break;
550 case V4L2_CID_HUE:
551
552 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
553 break;
554 case V4L2_CID_CONTRAST:
555 ret = adv7180_write(state, ADV7180_REG_CON, val);
556 break;
557 case V4L2_CID_SATURATION:
558
559
560
561
562 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
563 if (ret < 0)
564 break;
565 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
566 break;
567 case V4L2_CID_ADV_FAST_SWITCH:
568 if (ctrl->val) {
569
570 adv7180_write(state, 0x80d9, 0x44);
571 adv7180_write(state, ADV7180_REG_FLCONTROL,
572 ADV7180_FLCONTROL_FL_ENABLE);
573 } else {
574
575 adv7180_write(state, 0x80d9, 0xc4);
576 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
577 }
578 break;
579 default:
580 ret = -EINVAL;
581 }
582
583 mutex_unlock(&state->mutex);
584 return ret;
585}
586
587static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
588 .s_ctrl = adv7180_s_ctrl,
589};
590
591static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
592 .ops = &adv7180_ctrl_ops,
593 .id = V4L2_CID_ADV_FAST_SWITCH,
594 .name = "Fast Switching",
595 .type = V4L2_CTRL_TYPE_BOOLEAN,
596 .min = 0,
597 .max = 1,
598 .step = 1,
599};
600
601static int adv7180_init_controls(struct adv7180_state *state)
602{
603 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
604
605 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
606 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
607 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
608 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
609 V4L2_CID_CONTRAST, ADV7180_CON_MIN,
610 ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
611 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
612 V4L2_CID_SATURATION, ADV7180_SAT_MIN,
613 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
614 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
615 V4L2_CID_HUE, ADV7180_HUE_MIN,
616 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
617 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
618
619 state->sd.ctrl_handler = &state->ctrl_hdl;
620 if (state->ctrl_hdl.error) {
621 int err = state->ctrl_hdl.error;
622
623 v4l2_ctrl_handler_free(&state->ctrl_hdl);
624 return err;
625 }
626 v4l2_ctrl_handler_setup(&state->ctrl_hdl);
627
628 return 0;
629}
630static void adv7180_exit_controls(struct adv7180_state *state)
631{
632 v4l2_ctrl_handler_free(&state->ctrl_hdl);
633}
634
635static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
636 struct v4l2_subdev_pad_config *cfg,
637 struct v4l2_subdev_mbus_code_enum *code)
638{
639 if (code->index != 0)
640 return -EINVAL;
641
642 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
643
644 return 0;
645}
646
647static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
648 struct v4l2_mbus_framefmt *fmt)
649{
650 struct adv7180_state *state = to_state(sd);
651
652 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
653 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
654 fmt->width = 720;
655 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
656
657 if (state->field == V4L2_FIELD_ALTERNATE)
658 fmt->height /= 2;
659
660 return 0;
661}
662
663static int adv7180_set_field_mode(struct adv7180_state *state)
664{
665 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
666 return 0;
667
668 if (state->field == V4L2_FIELD_NONE) {
669 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
670 adv7180_csi_write(state, 0x01, 0x20);
671 adv7180_csi_write(state, 0x02, 0x28);
672 adv7180_csi_write(state, 0x03, 0x38);
673 adv7180_csi_write(state, 0x04, 0x30);
674 adv7180_csi_write(state, 0x05, 0x30);
675 adv7180_csi_write(state, 0x06, 0x80);
676 adv7180_csi_write(state, 0x07, 0x70);
677 adv7180_csi_write(state, 0x08, 0x50);
678 }
679 adv7180_vpp_write(state, 0xa3, 0x00);
680 adv7180_vpp_write(state, 0x5b, 0x00);
681 adv7180_vpp_write(state, 0x55, 0x80);
682 } else {
683 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
684 adv7180_csi_write(state, 0x01, 0x18);
685 adv7180_csi_write(state, 0x02, 0x18);
686 adv7180_csi_write(state, 0x03, 0x30);
687 adv7180_csi_write(state, 0x04, 0x20);
688 adv7180_csi_write(state, 0x05, 0x28);
689 adv7180_csi_write(state, 0x06, 0x40);
690 adv7180_csi_write(state, 0x07, 0x58);
691 adv7180_csi_write(state, 0x08, 0x30);
692 }
693 adv7180_vpp_write(state, 0xa3, 0x70);
694 adv7180_vpp_write(state, 0x5b, 0x80);
695 adv7180_vpp_write(state, 0x55, 0x00);
696 }
697
698 return 0;
699}
700
701static int adv7180_get_pad_format(struct v4l2_subdev *sd,
702 struct v4l2_subdev_pad_config *cfg,
703 struct v4l2_subdev_format *format)
704{
705 struct adv7180_state *state = to_state(sd);
706
707 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
708 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
709 } else {
710 adv7180_mbus_fmt(sd, &format->format);
711 format->format.field = state->field;
712 }
713
714 return 0;
715}
716
717static int adv7180_set_pad_format(struct v4l2_subdev *sd,
718 struct v4l2_subdev_pad_config *cfg,
719 struct v4l2_subdev_format *format)
720{
721 struct adv7180_state *state = to_state(sd);
722 struct v4l2_mbus_framefmt *framefmt;
723 int ret;
724
725 switch (format->format.field) {
726 case V4L2_FIELD_NONE:
727 if (state->chip_info->flags & ADV7180_FLAG_I2P)
728 break;
729
730 default:
731 format->format.field = V4L2_FIELD_ALTERNATE;
732 break;
733 }
734
735 ret = adv7180_mbus_fmt(sd, &format->format);
736
737 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
738 if (state->field != format->format.field) {
739 state->field = format->format.field;
740 adv7180_set_power(state, false);
741 adv7180_set_field_mode(state);
742 adv7180_set_power(state, true);
743 }
744 } else {
745 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
746 *framefmt = format->format;
747 }
748
749 return ret;
750}
751
752static int adv7180_init_cfg(struct v4l2_subdev *sd,
753 struct v4l2_subdev_pad_config *cfg)
754{
755 struct v4l2_subdev_format fmt = {
756 .which = cfg ? V4L2_SUBDEV_FORMAT_TRY
757 : V4L2_SUBDEV_FORMAT_ACTIVE,
758 };
759
760 return adv7180_set_pad_format(sd, cfg, &fmt);
761}
762
763static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
764 struct v4l2_mbus_config *cfg)
765{
766 struct adv7180_state *state = to_state(sd);
767
768 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
769 cfg->type = V4L2_MBUS_CSI2_DPHY;
770 cfg->flags = V4L2_MBUS_CSI2_1_LANE |
771 V4L2_MBUS_CSI2_CHANNEL_0 |
772 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
773 } else {
774
775
776
777
778 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
779 V4L2_MBUS_DATA_ACTIVE_HIGH;
780 cfg->type = V4L2_MBUS_BT656;
781 }
782
783 return 0;
784}
785
786static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
787{
788 *frames = ADV7180_NUM_OF_SKIP_FRAMES;
789
790 return 0;
791}
792
793static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
794{
795 struct adv7180_state *state = to_state(sd);
796
797 if (state->curr_norm & V4L2_STD_525_60) {
798 aspect->numerator = 11;
799 aspect->denominator = 10;
800 } else {
801 aspect->numerator = 54;
802 aspect->denominator = 59;
803 }
804
805 return 0;
806}
807
808static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
809{
810 *norm = V4L2_STD_ALL;
811 return 0;
812}
813
814static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
815{
816 struct adv7180_state *state = to_state(sd);
817 int ret;
818
819
820 if (!enable) {
821 state->streaming = enable;
822 return 0;
823 }
824
825
826 ret = mutex_lock_interruptible(&state->mutex);
827 if (ret)
828 return ret;
829 state->streaming = enable;
830 mutex_unlock(&state->mutex);
831 return 0;
832}
833
834static int adv7180_subscribe_event(struct v4l2_subdev *sd,
835 struct v4l2_fh *fh,
836 struct v4l2_event_subscription *sub)
837{
838 switch (sub->type) {
839 case V4L2_EVENT_SOURCE_CHANGE:
840 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
841 case V4L2_EVENT_CTRL:
842 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
843 default:
844 return -EINVAL;
845 }
846}
847
848static const struct v4l2_subdev_video_ops adv7180_video_ops = {
849 .s_std = adv7180_s_std,
850 .g_std = adv7180_g_std,
851 .g_frame_interval = adv7180_g_frame_interval,
852 .querystd = adv7180_querystd,
853 .g_input_status = adv7180_g_input_status,
854 .s_routing = adv7180_s_routing,
855 .g_mbus_config = adv7180_g_mbus_config,
856 .g_pixelaspect = adv7180_g_pixelaspect,
857 .g_tvnorms = adv7180_g_tvnorms,
858 .s_stream = adv7180_s_stream,
859};
860
861static const struct v4l2_subdev_core_ops adv7180_core_ops = {
862 .s_power = adv7180_s_power,
863 .subscribe_event = adv7180_subscribe_event,
864 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
865};
866
867static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
868 .init_cfg = adv7180_init_cfg,
869 .enum_mbus_code = adv7180_enum_mbus_code,
870 .set_fmt = adv7180_set_pad_format,
871 .get_fmt = adv7180_get_pad_format,
872};
873
874static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
875 .g_skip_frames = adv7180_get_skip_frames,
876};
877
878static const struct v4l2_subdev_ops adv7180_ops = {
879 .core = &adv7180_core_ops,
880 .video = &adv7180_video_ops,
881 .pad = &adv7180_pad_ops,
882 .sensor = &adv7180_sensor_ops,
883};
884
885static irqreturn_t adv7180_irq(int irq, void *devid)
886{
887 struct adv7180_state *state = devid;
888 u8 isr3;
889
890 mutex_lock(&state->mutex);
891 isr3 = adv7180_read(state, ADV7180_REG_ISR3);
892
893 adv7180_write(state, ADV7180_REG_ICR3, isr3);
894
895 if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
896 static const struct v4l2_event src_ch = {
897 .type = V4L2_EVENT_SOURCE_CHANGE,
898 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
899 };
900
901 v4l2_subdev_notify_event(&state->sd, &src_ch);
902 }
903 mutex_unlock(&state->mutex);
904
905 return IRQ_HANDLED;
906}
907
908static int adv7180_init(struct adv7180_state *state)
909{
910 int ret;
911
912
913 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
914 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
915 if (ret < 0)
916 return ret;
917
918
919 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
920 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
921}
922
923static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
924{
925 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
926 (std << 4) | state->input);
927}
928
929static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
930{
931 int ret;
932
933 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
934 if (ret < 0)
935 return ret;
936
937 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
938 ret |= input;
939 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
940}
941
942static int adv7182_init(struct adv7180_state *state)
943{
944 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
945 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
946 ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
947
948 if (state->chip_info->flags & ADV7180_FLAG_I2P)
949 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
950 ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
951
952 if (state->chip_info->flags & ADV7180_FLAG_V2) {
953
954 adv7180_write(state, 0x0080, 0x51);
955 adv7180_write(state, 0x0081, 0x51);
956 adv7180_write(state, 0x0082, 0x68);
957 }
958
959
960 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
961 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
962 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
963 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
964 } else {
965 if (state->chip_info->flags & ADV7180_FLAG_V2)
966 adv7180_write(state,
967 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
968 0x17);
969 else
970 adv7180_write(state,
971 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
972 0x07);
973 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
974 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
975 }
976
977 adv7180_write(state, 0x0013, 0x00);
978
979 return 0;
980}
981
982static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
983{
984 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
985}
986
987enum adv7182_input_type {
988 ADV7182_INPUT_TYPE_CVBS,
989 ADV7182_INPUT_TYPE_DIFF_CVBS,
990 ADV7182_INPUT_TYPE_SVIDEO,
991 ADV7182_INPUT_TYPE_YPBPR,
992};
993
994static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
995{
996 switch (input) {
997 case ADV7182_INPUT_CVBS_AIN1:
998 case ADV7182_INPUT_CVBS_AIN2:
999 case ADV7182_INPUT_CVBS_AIN3:
1000 case ADV7182_INPUT_CVBS_AIN4:
1001 case ADV7182_INPUT_CVBS_AIN5:
1002 case ADV7182_INPUT_CVBS_AIN6:
1003 case ADV7182_INPUT_CVBS_AIN7:
1004 case ADV7182_INPUT_CVBS_AIN8:
1005 return ADV7182_INPUT_TYPE_CVBS;
1006 case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
1007 case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
1008 case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
1009 case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
1010 return ADV7182_INPUT_TYPE_SVIDEO;
1011 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
1012 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
1013 return ADV7182_INPUT_TYPE_YPBPR;
1014 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
1015 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
1016 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
1017 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1018 return ADV7182_INPUT_TYPE_DIFF_CVBS;
1019 default:
1020 return 0;
1021 }
1022}
1023
1024
1025static unsigned int adv7182_lbias_settings[][3] = {
1026 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1027 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1028 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1029 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1030};
1031
1032static unsigned int adv7280_lbias_settings[][3] = {
1033 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1034 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1035 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1036 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1037};
1038
1039static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1040{
1041 enum adv7182_input_type input_type;
1042 unsigned int *lbias;
1043 unsigned int i;
1044 int ret;
1045
1046 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1047 if (ret)
1048 return ret;
1049
1050
1051 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1052 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1053
1054 input_type = adv7182_get_input_type(input);
1055
1056 switch (input_type) {
1057 case ADV7182_INPUT_TYPE_CVBS:
1058 case ADV7182_INPUT_TYPE_DIFF_CVBS:
1059
1060 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1061 break;
1062 default:
1063 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1064 break;
1065 }
1066
1067 if (state->chip_info->flags & ADV7180_FLAG_V2)
1068 lbias = adv7280_lbias_settings[input_type];
1069 else
1070 lbias = adv7182_lbias_settings[input_type];
1071
1072 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1073 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1074
1075 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1076
1077 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1078 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1079 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1080 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1081 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1082 } else {
1083 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1084 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1085 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1086 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1087 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1088 }
1089
1090 return 0;
1091}
1092
1093static const struct adv7180_chip_info adv7180_info = {
1094 .flags = ADV7180_FLAG_RESET_POWERED,
1095
1096
1097
1098 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1099 BIT(ADV7180_INPUT_CVBS_AIN2) |
1100 BIT(ADV7180_INPUT_CVBS_AIN3) |
1101 BIT(ADV7180_INPUT_CVBS_AIN4) |
1102 BIT(ADV7180_INPUT_CVBS_AIN5) |
1103 BIT(ADV7180_INPUT_CVBS_AIN6) |
1104 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1105 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1106 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1107 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1108 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1109 .init = adv7180_init,
1110 .set_std = adv7180_set_std,
1111 .select_input = adv7180_select_input,
1112};
1113
1114static const struct adv7180_chip_info adv7182_info = {
1115 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1116 BIT(ADV7182_INPUT_CVBS_AIN2) |
1117 BIT(ADV7182_INPUT_CVBS_AIN3) |
1118 BIT(ADV7182_INPUT_CVBS_AIN4) |
1119 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1120 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1121 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1122 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1123 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1124 .init = adv7182_init,
1125 .set_std = adv7182_set_std,
1126 .select_input = adv7182_select_input,
1127};
1128
1129static const struct adv7180_chip_info adv7280_info = {
1130 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1131 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1132 BIT(ADV7182_INPUT_CVBS_AIN2) |
1133 BIT(ADV7182_INPUT_CVBS_AIN3) |
1134 BIT(ADV7182_INPUT_CVBS_AIN4) |
1135 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1136 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1137 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1138 .init = adv7182_init,
1139 .set_std = adv7182_set_std,
1140 .select_input = adv7182_select_input,
1141};
1142
1143static const struct adv7180_chip_info adv7280_m_info = {
1144 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1145 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1146 BIT(ADV7182_INPUT_CVBS_AIN2) |
1147 BIT(ADV7182_INPUT_CVBS_AIN3) |
1148 BIT(ADV7182_INPUT_CVBS_AIN4) |
1149 BIT(ADV7182_INPUT_CVBS_AIN5) |
1150 BIT(ADV7182_INPUT_CVBS_AIN6) |
1151 BIT(ADV7182_INPUT_CVBS_AIN7) |
1152 BIT(ADV7182_INPUT_CVBS_AIN8) |
1153 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1154 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1155 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1156 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1157 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1158 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1159 .init = adv7182_init,
1160 .set_std = adv7182_set_std,
1161 .select_input = adv7182_select_input,
1162};
1163
1164static const struct adv7180_chip_info adv7281_info = {
1165 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1166 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1167 BIT(ADV7182_INPUT_CVBS_AIN2) |
1168 BIT(ADV7182_INPUT_CVBS_AIN7) |
1169 BIT(ADV7182_INPUT_CVBS_AIN8) |
1170 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1171 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1172 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1173 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1174 .init = adv7182_init,
1175 .set_std = adv7182_set_std,
1176 .select_input = adv7182_select_input,
1177};
1178
1179static const struct adv7180_chip_info adv7281_m_info = {
1180 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1181 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1182 BIT(ADV7182_INPUT_CVBS_AIN2) |
1183 BIT(ADV7182_INPUT_CVBS_AIN3) |
1184 BIT(ADV7182_INPUT_CVBS_AIN4) |
1185 BIT(ADV7182_INPUT_CVBS_AIN7) |
1186 BIT(ADV7182_INPUT_CVBS_AIN8) |
1187 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1188 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1189 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1190 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1191 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1192 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1193 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1194 .init = adv7182_init,
1195 .set_std = adv7182_set_std,
1196 .select_input = adv7182_select_input,
1197};
1198
1199static const struct adv7180_chip_info adv7281_ma_info = {
1200 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1201 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1202 BIT(ADV7182_INPUT_CVBS_AIN2) |
1203 BIT(ADV7182_INPUT_CVBS_AIN3) |
1204 BIT(ADV7182_INPUT_CVBS_AIN4) |
1205 BIT(ADV7182_INPUT_CVBS_AIN5) |
1206 BIT(ADV7182_INPUT_CVBS_AIN6) |
1207 BIT(ADV7182_INPUT_CVBS_AIN7) |
1208 BIT(ADV7182_INPUT_CVBS_AIN8) |
1209 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1210 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1211 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1212 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1213 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1214 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1215 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1216 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1217 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1218 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1219 .init = adv7182_init,
1220 .set_std = adv7182_set_std,
1221 .select_input = adv7182_select_input,
1222};
1223
1224static const struct adv7180_chip_info adv7282_info = {
1225 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1226 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1227 BIT(ADV7182_INPUT_CVBS_AIN2) |
1228 BIT(ADV7182_INPUT_CVBS_AIN7) |
1229 BIT(ADV7182_INPUT_CVBS_AIN8) |
1230 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1231 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1232 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1233 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1234 .init = adv7182_init,
1235 .set_std = adv7182_set_std,
1236 .select_input = adv7182_select_input,
1237};
1238
1239static const struct adv7180_chip_info adv7282_m_info = {
1240 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1241 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1242 BIT(ADV7182_INPUT_CVBS_AIN2) |
1243 BIT(ADV7182_INPUT_CVBS_AIN3) |
1244 BIT(ADV7182_INPUT_CVBS_AIN4) |
1245 BIT(ADV7182_INPUT_CVBS_AIN7) |
1246 BIT(ADV7182_INPUT_CVBS_AIN8) |
1247 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1248 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1249 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1250 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1251 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1252 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1253 .init = adv7182_init,
1254 .set_std = adv7182_set_std,
1255 .select_input = adv7182_select_input,
1256};
1257
1258static int init_device(struct adv7180_state *state)
1259{
1260 int ret;
1261
1262 mutex_lock(&state->mutex);
1263
1264 adv7180_set_power_pin(state, true);
1265
1266 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1267 usleep_range(5000, 10000);
1268
1269 ret = state->chip_info->init(state);
1270 if (ret)
1271 goto out_unlock;
1272
1273 ret = adv7180_program_std(state);
1274 if (ret)
1275 goto out_unlock;
1276
1277 adv7180_set_field_mode(state);
1278
1279
1280 if (state->irq > 0) {
1281
1282 ret = adv7180_write(state, ADV7180_REG_ICONF1,
1283 ADV7180_ICONF1_ACTIVE_LOW |
1284 ADV7180_ICONF1_PSYNC_ONLY);
1285 if (ret < 0)
1286 goto out_unlock;
1287
1288 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1289 if (ret < 0)
1290 goto out_unlock;
1291
1292 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1293 if (ret < 0)
1294 goto out_unlock;
1295
1296
1297 ret = adv7180_write(state, ADV7180_REG_IMR3,
1298 ADV7180_IRQ3_AD_CHANGE);
1299 if (ret < 0)
1300 goto out_unlock;
1301
1302 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
1303 if (ret < 0)
1304 goto out_unlock;
1305 }
1306
1307out_unlock:
1308 mutex_unlock(&state->mutex);
1309
1310 return ret;
1311}
1312
1313static int adv7180_probe(struct i2c_client *client,
1314 const struct i2c_device_id *id)
1315{
1316 struct adv7180_state *state;
1317 struct v4l2_subdev *sd;
1318 int ret;
1319
1320
1321 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1322 return -EIO;
1323
1324 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1325 if (state == NULL)
1326 return -ENOMEM;
1327
1328 state->client = client;
1329 state->field = V4L2_FIELD_ALTERNATE;
1330 state->chip_info = (struct adv7180_chip_info *)id->driver_data;
1331
1332 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1333 GPIOD_OUT_HIGH);
1334 if (IS_ERR(state->pwdn_gpio)) {
1335 ret = PTR_ERR(state->pwdn_gpio);
1336 v4l_err(client, "request for power pin failed: %d\n", ret);
1337 return ret;
1338 }
1339
1340 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1341 state->csi_client = i2c_new_dummy_device(client->adapter,
1342 ADV7180_DEFAULT_CSI_I2C_ADDR);
1343 if (IS_ERR(state->csi_client))
1344 return PTR_ERR(state->csi_client);
1345 }
1346
1347 if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1348 state->vpp_client = i2c_new_dummy_device(client->adapter,
1349 ADV7180_DEFAULT_VPP_I2C_ADDR);
1350 if (IS_ERR(state->vpp_client)) {
1351 ret = PTR_ERR(state->vpp_client);
1352 goto err_unregister_csi_client;
1353 }
1354 }
1355
1356 state->irq = client->irq;
1357 mutex_init(&state->mutex);
1358 state->curr_norm = V4L2_STD_NTSC;
1359 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
1360 state->powered = true;
1361 else
1362 state->powered = false;
1363 state->input = 0;
1364 sd = &state->sd;
1365 v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1366 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1367
1368 ret = adv7180_init_controls(state);
1369 if (ret)
1370 goto err_unregister_vpp_client;
1371
1372 state->pad.flags = MEDIA_PAD_FL_SOURCE;
1373 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1374 ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1375 if (ret)
1376 goto err_free_ctrl;
1377
1378 ret = init_device(state);
1379 if (ret)
1380 goto err_media_entity_cleanup;
1381
1382 if (state->irq) {
1383 ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1384 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1385 KBUILD_MODNAME, state);
1386 if (ret)
1387 goto err_media_entity_cleanup;
1388 }
1389
1390 ret = v4l2_async_register_subdev(sd);
1391 if (ret)
1392 goto err_free_irq;
1393
1394 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1395 client->addr, client->adapter->name);
1396
1397 return 0;
1398
1399err_free_irq:
1400 if (state->irq > 0)
1401 free_irq(client->irq, state);
1402err_media_entity_cleanup:
1403 media_entity_cleanup(&sd->entity);
1404err_free_ctrl:
1405 adv7180_exit_controls(state);
1406err_unregister_vpp_client:
1407 i2c_unregister_device(state->vpp_client);
1408err_unregister_csi_client:
1409 i2c_unregister_device(state->csi_client);
1410 mutex_destroy(&state->mutex);
1411 return ret;
1412}
1413
1414static int adv7180_remove(struct i2c_client *client)
1415{
1416 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1417 struct adv7180_state *state = to_state(sd);
1418
1419 v4l2_async_unregister_subdev(sd);
1420
1421 if (state->irq > 0)
1422 free_irq(client->irq, state);
1423
1424 media_entity_cleanup(&sd->entity);
1425 adv7180_exit_controls(state);
1426
1427 i2c_unregister_device(state->vpp_client);
1428 i2c_unregister_device(state->csi_client);
1429
1430 adv7180_set_power_pin(state, false);
1431
1432 mutex_destroy(&state->mutex);
1433
1434 return 0;
1435}
1436
1437static const struct i2c_device_id adv7180_id[] = {
1438 { "adv7180", (kernel_ulong_t)&adv7180_info },
1439 { "adv7180cp", (kernel_ulong_t)&adv7180_info },
1440 { "adv7180st", (kernel_ulong_t)&adv7180_info },
1441 { "adv7182", (kernel_ulong_t)&adv7182_info },
1442 { "adv7280", (kernel_ulong_t)&adv7280_info },
1443 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
1444 { "adv7281", (kernel_ulong_t)&adv7281_info },
1445 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1446 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
1447 { "adv7282", (kernel_ulong_t)&adv7282_info },
1448 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
1449 {},
1450};
1451MODULE_DEVICE_TABLE(i2c, adv7180_id);
1452
1453#ifdef CONFIG_PM_SLEEP
1454static int adv7180_suspend(struct device *dev)
1455{
1456 struct i2c_client *client = to_i2c_client(dev);
1457 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1458 struct adv7180_state *state = to_state(sd);
1459
1460 return adv7180_set_power(state, false);
1461}
1462
1463static int adv7180_resume(struct device *dev)
1464{
1465 struct i2c_client *client = to_i2c_client(dev);
1466 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1467 struct adv7180_state *state = to_state(sd);
1468 int ret;
1469
1470 ret = init_device(state);
1471 if (ret < 0)
1472 return ret;
1473
1474 ret = adv7180_set_power(state, state->powered);
1475 if (ret)
1476 return ret;
1477
1478 return 0;
1479}
1480
1481static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1482#define ADV7180_PM_OPS (&adv7180_pm_ops)
1483
1484#else
1485#define ADV7180_PM_OPS NULL
1486#endif
1487
1488#ifdef CONFIG_OF
1489static const struct of_device_id adv7180_of_id[] = {
1490 { .compatible = "adi,adv7180", },
1491 { .compatible = "adi,adv7180cp", },
1492 { .compatible = "adi,adv7180st", },
1493 { .compatible = "adi,adv7182", },
1494 { .compatible = "adi,adv7280", },
1495 { .compatible = "adi,adv7280-m", },
1496 { .compatible = "adi,adv7281", },
1497 { .compatible = "adi,adv7281-m", },
1498 { .compatible = "adi,adv7281-ma", },
1499 { .compatible = "adi,adv7282", },
1500 { .compatible = "adi,adv7282-m", },
1501 { },
1502};
1503
1504MODULE_DEVICE_TABLE(of, adv7180_of_id);
1505#endif
1506
1507static struct i2c_driver adv7180_driver = {
1508 .driver = {
1509 .name = KBUILD_MODNAME,
1510 .pm = ADV7180_PM_OPS,
1511 .of_match_table = of_match_ptr(adv7180_of_id),
1512 },
1513 .probe = adv7180_probe,
1514 .remove = adv7180_remove,
1515 .id_table = adv7180_id,
1516};
1517
1518module_i2c_driver(adv7180_driver);
1519
1520MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1521MODULE_AUTHOR("Mocean Laboratories");
1522MODULE_LICENSE("GPL v2");
1523
