1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2012-2020, Intel Corporation. All rights reserved. 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 */ 6 7#ifndef _MEI_INTERFACE_H_ 8#define _MEI_INTERFACE_H_ 9 10#include <linux/irqreturn.h> 11#include <linux/pci.h> 12#include <linux/mei.h> 13 14#include "mei_dev.h" 15#include "client.h" 16 17/* 18 * mei_cfg - mei device configuration 19 * 20 * @fw_status: FW status 21 * @quirk_probe: device exclusion quirk 22 * @dma_size: device DMA buffers size 23 * @fw_ver_supported: is fw version retrievable from FW 24 * @hw_trc_supported: does the hw support trc register 25 */ 26struct mei_cfg { 27 const struct mei_fw_status fw_status; 28 bool (*quirk_probe)(struct pci_dev *pdev); 29 size_t dma_size[DMA_DSCR_NUM]; 30 u32 fw_ver_supported:1; 31 u32 hw_trc_supported:1; 32}; 33 34 35#define MEI_PCI_DEVICE(dev, cfg) \ 36 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ 37 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 38 .driver_data = (kernel_ulong_t)(cfg), 39 40#define MEI_ME_RPM_TIMEOUT 500 /* ms */ 41 42/** 43 * struct mei_me_hw - me hw specific data 44 * 45 * @cfg: per device generation config and ops 46 * @mem_addr: io memory address 47 * @irq: irq number 48 * @pg_state: power gating state 49 * @d0i3_supported: di03 support 50 * @hbuf_depth: depth of hardware host/write buffer in slots 51 * @read_fws: read FW status register handler 52 */ 53struct mei_me_hw { 54 const struct mei_cfg *cfg; 55 void __iomem *mem_addr; 56 int irq; 57 enum mei_pg_state pg_state; 58 bool d0i3_supported; 59 u8 hbuf_depth; 60 int (*read_fws)(const struct mei_device *dev, int where, u32 *val); 61}; 62 63#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) 64 65/** 66 * enum mei_cfg_idx - indices to platform specific configurations. 67 * 68 * Note: has to be synchronized with mei_cfg_list[] 69 * 70 * @MEI_ME_UNDEF_CFG: Lower sentinel. 71 * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices. 72 * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10 73 * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6). 74 * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7). 75 * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations 76 * with quirk for Node Manager exclusion. 77 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer 78 * client platforms. 79 * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer 80 * servers platforms with quirk for 81 * SPS firmware exclusion. 82 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer 83 * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0 84 * servers platforms with quirk for 85 * SPS firmware exclusion. 86 * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer 87 * servers platforms with quirk for 88 * SPS firmware exclusion. 89 * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer 90 * @MEI_ME_PCH15_SPS_CFG: Platform Controller Hub Gen15 and newer 91 * servers platforms with quirk for 92 * SPS firmware exclusion. 93 * @MEI_ME_NUM_CFG: Upper Sentinel. 94 */ 95enum mei_cfg_idx { 96 MEI_ME_UNDEF_CFG, 97 MEI_ME_ICH_CFG, 98 MEI_ME_ICH10_CFG, 99 MEI_ME_PCH6_CFG, 100 MEI_ME_PCH7_CFG, 101 MEI_ME_PCH_CPT_PBG_CFG, 102 MEI_ME_PCH8_CFG, 103 MEI_ME_PCH8_SPS_4_CFG, 104 MEI_ME_PCH12_CFG, 105 MEI_ME_PCH12_SPS_4_CFG, 106 MEI_ME_PCH12_SPS_CFG, 107 MEI_ME_PCH12_SPS_NODMA_CFG, 108 MEI_ME_PCH15_CFG, 109 MEI_ME_PCH15_SPS_CFG, 110 MEI_ME_NUM_CFG, 111}; 112 113const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); 114 115struct mei_device *mei_me_dev_init(struct device *parent, 116 const struct mei_cfg *cfg); 117 118int mei_me_pg_enter_sync(struct mei_device *dev); 119int mei_me_pg_exit_sync(struct mei_device *dev); 120 121irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); 122irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); 123 124#endif /* _MEI_INTERFACE_H_ */ 125