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12#include <linux/spinlock.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/mmc-sdhci-s3c.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_gpio.h>
24#include <linux/pm.h>
25#include <linux/pm_runtime.h>
26
27#include <linux/mmc/host.h>
28
29#include "sdhci.h"
30
31#define MAX_BUS_CLK (4)
32
33#define S3C_SDHCI_CONTROL2 (0x80)
34#define S3C_SDHCI_CONTROL3 (0x84)
35#define S3C64XX_SDHCI_CONTROL4 (0x8C)
36
37#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
38#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
39#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
40#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
41
42#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
43#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
44#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
45
46#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
47#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
48#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
49
50#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
51#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
52#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
53#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
54#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
55
56#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
57#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
58#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
59#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
60#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
61#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
62
63#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
64#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
65#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
66
67#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
68#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
69#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
70#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
71#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
72
73#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
74#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
75#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
76#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
77
78#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
79#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
80#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
81
82#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
83#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
84#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
85
86#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
87#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
88#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
89
90#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
91#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
92#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
93
94#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
95#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
96#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
97#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
98#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
99#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
100
101#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
102
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111
112
113struct sdhci_s3c {
114 struct sdhci_host *host;
115 struct platform_device *pdev;
116 struct resource *ioarea;
117 struct s3c_sdhci_platdata *pdata;
118 int cur_clk;
119 int ext_cd_irq;
120
121 struct clk *clk_io;
122 struct clk *clk_bus[MAX_BUS_CLK];
123 unsigned long clk_rates[MAX_BUS_CLK];
124
125 bool no_divider;
126};
127
128
129
130
131
132
133
134
135
136struct sdhci_s3c_drv_data {
137 unsigned int sdhci_quirks;
138 bool no_divider;
139};
140
141static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
142{
143 return sdhci_priv(host);
144}
145
146
147
148
149
150
151
152static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
153{
154 struct sdhci_s3c *ourhost = to_s3c(host);
155 unsigned long rate, max = 0;
156 int src;
157
158 for (src = 0; src < MAX_BUS_CLK; src++) {
159 rate = ourhost->clk_rates[src];
160 if (rate > max)
161 max = rate;
162 }
163
164 return max;
165}
166
167
168
169
170
171
172
173static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
174 unsigned int src,
175 unsigned int wanted)
176{
177 unsigned long rate;
178 struct clk *clksrc = ourhost->clk_bus[src];
179 int shift;
180
181 if (IS_ERR(clksrc))
182 return UINT_MAX;
183
184
185
186
187
188 if (ourhost->no_divider) {
189 rate = clk_round_rate(clksrc, wanted);
190 return wanted - rate;
191 }
192
193 rate = ourhost->clk_rates[src];
194
195 for (shift = 0; shift <= 8; ++shift) {
196 if ((rate >> shift) <= wanted)
197 break;
198 }
199
200 if (shift > 8) {
201 dev_dbg(&ourhost->pdev->dev,
202 "clk %d: rate %ld, min rate %lu > wanted %u\n",
203 src, rate, rate / 256, wanted);
204 return UINT_MAX;
205 }
206
207 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
208 src, rate, wanted, rate >> shift);
209
210 return wanted - (rate >> shift);
211}
212
213
214
215
216
217
218
219
220
221static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
222{
223 struct sdhci_s3c *ourhost = to_s3c(host);
224 unsigned int best = UINT_MAX;
225 unsigned int delta;
226 int best_src = 0;
227 int src;
228 u32 ctrl;
229
230 host->mmc->actual_clock = 0;
231
232
233 if (clock == 0) {
234 sdhci_set_clock(host, clock);
235 return;
236 }
237
238 for (src = 0; src < MAX_BUS_CLK; src++) {
239 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
240 if (delta < best) {
241 best = delta;
242 best_src = src;
243 }
244 }
245
246 dev_dbg(&ourhost->pdev->dev,
247 "selected source %d, clock %d, delta %d\n",
248 best_src, clock, best);
249
250
251 if (ourhost->cur_clk != best_src) {
252 struct clk *clk = ourhost->clk_bus[best_src];
253
254 clk_prepare_enable(clk);
255 if (ourhost->cur_clk >= 0)
256 clk_disable_unprepare(
257 ourhost->clk_bus[ourhost->cur_clk]);
258
259 ourhost->cur_clk = best_src;
260 host->max_clk = ourhost->clk_rates[best_src];
261 }
262
263
264 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
265
266 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
267 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
268 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
269 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
270
271
272 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
273 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
274
275 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
276 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
277 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
278 S3C_SDHCI_CTRL2_ENFBCLKRX |
279 S3C_SDHCI_CTRL2_DFCNT_NONE |
280 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
281 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
282
283
284 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
285 if (clock < 25 * 1000000)
286 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
287 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
288
289 sdhci_set_clock(host, clock);
290}
291
292
293
294
295
296
297
298
299
300
301static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
302{
303 struct sdhci_s3c *ourhost = to_s3c(host);
304 unsigned long rate, min = ULONG_MAX;
305 int src;
306
307 for (src = 0; src < MAX_BUS_CLK; src++) {
308 rate = ourhost->clk_rates[src] / 256;
309 if (!rate)
310 continue;
311 if (rate < min)
312 min = rate;
313 }
314
315 return min;
316}
317
318
319static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
320{
321 struct sdhci_s3c *ourhost = to_s3c(host);
322 unsigned long rate, max = 0;
323 int src;
324
325 for (src = 0; src < MAX_BUS_CLK; src++) {
326 struct clk *clk;
327
328 clk = ourhost->clk_bus[src];
329 if (IS_ERR(clk))
330 continue;
331
332 rate = clk_round_rate(clk, ULONG_MAX);
333 if (rate > max)
334 max = rate;
335 }
336
337 return max;
338}
339
340
341static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
342{
343 struct sdhci_s3c *ourhost = to_s3c(host);
344 unsigned long rate, min = ULONG_MAX;
345 int src;
346
347 for (src = 0; src < MAX_BUS_CLK; src++) {
348 struct clk *clk;
349
350 clk = ourhost->clk_bus[src];
351 if (IS_ERR(clk))
352 continue;
353
354 rate = clk_round_rate(clk, 0);
355 if (rate < min)
356 min = rate;
357 }
358
359 return min;
360}
361
362
363static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
364{
365 struct sdhci_s3c *ourhost = to_s3c(host);
366 struct device *dev = &ourhost->pdev->dev;
367 unsigned long timeout;
368 u16 clk = 0;
369 int ret;
370
371 host->mmc->actual_clock = 0;
372
373
374 if (clock == 0) {
375 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
376 return;
377 }
378
379 sdhci_s3c_set_clock(host, clock);
380
381
382 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
383 clk &= ~SDHCI_CLOCK_CARD_EN;
384 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
385
386 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
387 if (ret != 0) {
388 dev_err(dev, "%s: failed to set clock rate %uHz\n",
389 mmc_hostname(host->mmc), clock);
390 return;
391 }
392
393 clk = SDHCI_CLOCK_INT_EN;
394 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
395
396
397 timeout = 20;
398 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
399 & SDHCI_CLOCK_INT_STABLE)) {
400 if (timeout == 0) {
401 dev_err(dev, "%s: Internal clock never stabilised.\n",
402 mmc_hostname(host->mmc));
403 return;
404 }
405 timeout--;
406 mdelay(1);
407 }
408
409 clk |= SDHCI_CLOCK_CARD_EN;
410 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
411}
412
413static struct sdhci_ops sdhci_s3c_ops = {
414 .get_max_clock = sdhci_s3c_get_max_clk,
415 .set_clock = sdhci_s3c_set_clock,
416 .get_min_clock = sdhci_s3c_get_min_clock,
417 .set_bus_width = sdhci_set_bus_width,
418 .reset = sdhci_reset,
419 .set_uhs_signaling = sdhci_set_uhs_signaling,
420};
421
422#ifdef CONFIG_OF
423static int sdhci_s3c_parse_dt(struct device *dev,
424 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
425{
426 struct device_node *node = dev->of_node;
427 u32 max_width;
428
429
430 if (of_property_read_u32(node, "bus-width", &max_width))
431 max_width = 1;
432 pdata->max_width = max_width;
433
434
435 if (of_get_property(node, "broken-cd", NULL)) {
436 pdata->cd_type = S3C_SDHCI_CD_NONE;
437 return 0;
438 }
439
440 if (of_get_property(node, "non-removable", NULL)) {
441 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
442 return 0;
443 }
444
445 if (of_get_named_gpio(node, "cd-gpios", 0))
446 return 0;
447
448
449 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
450 return 0;
451}
452#else
453static int sdhci_s3c_parse_dt(struct device *dev,
454 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
455{
456 return -EINVAL;
457}
458#endif
459
460static const struct of_device_id sdhci_s3c_dt_match[];
461
462static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
463 struct platform_device *pdev)
464{
465#ifdef CONFIG_OF
466 if (pdev->dev.of_node) {
467 const struct of_device_id *match;
468 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
469 return (struct sdhci_s3c_drv_data *)match->data;
470 }
471#endif
472 return (struct sdhci_s3c_drv_data *)
473 platform_get_device_id(pdev)->driver_data;
474}
475
476static int sdhci_s3c_probe(struct platform_device *pdev)
477{
478 struct s3c_sdhci_platdata *pdata;
479 struct sdhci_s3c_drv_data *drv_data;
480 struct device *dev = &pdev->dev;
481 struct sdhci_host *host;
482 struct sdhci_s3c *sc;
483 int ret, irq, ptr, clks;
484
485 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
486 dev_err(dev, "no device data specified\n");
487 return -ENOENT;
488 }
489
490 irq = platform_get_irq(pdev, 0);
491 if (irq < 0)
492 return irq;
493
494 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
495 if (IS_ERR(host)) {
496 dev_err(dev, "sdhci_alloc_host() failed\n");
497 return PTR_ERR(host);
498 }
499 sc = sdhci_priv(host);
500
501 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
502 if (!pdata) {
503 ret = -ENOMEM;
504 goto err_pdata_io_clk;
505 }
506
507 if (pdev->dev.of_node) {
508 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
509 if (ret)
510 goto err_pdata_io_clk;
511 } else {
512 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
513 }
514
515 drv_data = sdhci_s3c_get_driver_data(pdev);
516
517 sc->host = host;
518 sc->pdev = pdev;
519 sc->pdata = pdata;
520 sc->cur_clk = -1;
521
522 platform_set_drvdata(pdev, host);
523
524 sc->clk_io = devm_clk_get(dev, "hsmmc");
525 if (IS_ERR(sc->clk_io)) {
526 dev_err(dev, "failed to get io clock\n");
527 ret = PTR_ERR(sc->clk_io);
528 goto err_pdata_io_clk;
529 }
530
531
532 clk_prepare_enable(sc->clk_io);
533
534 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
535 char name[14];
536
537 snprintf(name, 14, "mmc_busclk.%d", ptr);
538 sc->clk_bus[ptr] = devm_clk_get(dev, name);
539 if (IS_ERR(sc->clk_bus[ptr]))
540 continue;
541
542 clks++;
543 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
544
545 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
546 ptr, name, sc->clk_rates[ptr]);
547 }
548
549 if (clks == 0) {
550 dev_err(dev, "failed to find any bus clocks\n");
551 ret = -ENOENT;
552 goto err_no_busclks;
553 }
554
555 host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
556 if (IS_ERR(host->ioaddr)) {
557 ret = PTR_ERR(host->ioaddr);
558 goto err_req_regs;
559 }
560
561
562 if (pdata->cfg_gpio)
563 pdata->cfg_gpio(pdev, pdata->max_width);
564
565 host->hw_name = "samsung-hsmmc";
566 host->ops = &sdhci_s3c_ops;
567 host->quirks = 0;
568 host->quirks2 = 0;
569 host->irq = irq;
570
571
572 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
573 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
574 if (drv_data) {
575 host->quirks |= drv_data->sdhci_quirks;
576 sc->no_divider = drv_data->no_divider;
577 }
578
579#ifndef CONFIG_MMC_SDHCI_S3C_DMA
580
581
582
583 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
584
585#endif
586
587
588
589
590 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
591
592
593 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
594
595
596 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
597
598 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
599 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
600 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
601
602 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
603 host->mmc->caps = MMC_CAP_NONREMOVABLE;
604
605 switch (pdata->max_width) {
606 case 8:
607 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
608
609 case 4:
610 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
611 break;
612 }
613
614 if (pdata->pm_caps)
615 host->mmc->pm_caps |= pdata->pm_caps;
616
617 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
618 SDHCI_QUIRK_32BIT_DMA_SIZE);
619
620
621 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
622
623
624
625
626
627 if (sc->no_divider) {
628 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
629 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
630 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
631 }
632
633
634 if (pdata->host_caps)
635 host->mmc->caps |= pdata->host_caps;
636
637 if (pdata->host_caps2)
638 host->mmc->caps2 |= pdata->host_caps2;
639
640 pm_runtime_enable(&pdev->dev);
641 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
642 pm_runtime_use_autosuspend(&pdev->dev);
643 pm_suspend_ignore_children(&pdev->dev, 1);
644
645 ret = mmc_of_parse(host->mmc);
646 if (ret)
647 goto err_req_regs;
648
649 ret = sdhci_add_host(host);
650 if (ret)
651 goto err_req_regs;
652
653#ifdef CONFIG_PM
654 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
655 clk_disable_unprepare(sc->clk_io);
656#endif
657 return 0;
658
659 err_req_regs:
660 pm_runtime_disable(&pdev->dev);
661
662 err_no_busclks:
663 clk_disable_unprepare(sc->clk_io);
664
665 err_pdata_io_clk:
666 sdhci_free_host(host);
667
668 return ret;
669}
670
671static int sdhci_s3c_remove(struct platform_device *pdev)
672{
673 struct sdhci_host *host = platform_get_drvdata(pdev);
674 struct sdhci_s3c *sc = sdhci_priv(host);
675
676 if (sc->ext_cd_irq)
677 free_irq(sc->ext_cd_irq, sc);
678
679#ifdef CONFIG_PM
680 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
681 clk_prepare_enable(sc->clk_io);
682#endif
683 sdhci_remove_host(host, 1);
684
685 pm_runtime_dont_use_autosuspend(&pdev->dev);
686 pm_runtime_disable(&pdev->dev);
687
688 clk_disable_unprepare(sc->clk_io);
689
690 sdhci_free_host(host);
691
692 return 0;
693}
694
695#ifdef CONFIG_PM_SLEEP
696static int sdhci_s3c_suspend(struct device *dev)
697{
698 struct sdhci_host *host = dev_get_drvdata(dev);
699
700 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
701 mmc_retune_needed(host->mmc);
702
703 return sdhci_suspend_host(host);
704}
705
706static int sdhci_s3c_resume(struct device *dev)
707{
708 struct sdhci_host *host = dev_get_drvdata(dev);
709
710 return sdhci_resume_host(host);
711}
712#endif
713
714#ifdef CONFIG_PM
715static int sdhci_s3c_runtime_suspend(struct device *dev)
716{
717 struct sdhci_host *host = dev_get_drvdata(dev);
718 struct sdhci_s3c *ourhost = to_s3c(host);
719 struct clk *busclk = ourhost->clk_io;
720 int ret;
721
722 ret = sdhci_runtime_suspend_host(host);
723
724 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
725 mmc_retune_needed(host->mmc);
726
727 if (ourhost->cur_clk >= 0)
728 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
729 clk_disable_unprepare(busclk);
730 return ret;
731}
732
733static int sdhci_s3c_runtime_resume(struct device *dev)
734{
735 struct sdhci_host *host = dev_get_drvdata(dev);
736 struct sdhci_s3c *ourhost = to_s3c(host);
737 struct clk *busclk = ourhost->clk_io;
738 int ret;
739
740 clk_prepare_enable(busclk);
741 if (ourhost->cur_clk >= 0)
742 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
743 ret = sdhci_runtime_resume_host(host, 0);
744 return ret;
745}
746#endif
747
748static const struct dev_pm_ops sdhci_s3c_pmops = {
749 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
750 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
751 NULL)
752};
753
754static const struct platform_device_id sdhci_s3c_driver_ids[] = {
755 {
756 .name = "s3c-sdhci",
757 .driver_data = (kernel_ulong_t)NULL,
758 },
759 { }
760};
761MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
762
763#ifdef CONFIG_OF
764static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
765 .no_divider = true,
766};
767
768static const struct of_device_id sdhci_s3c_dt_match[] = {
769 { .compatible = "samsung,s3c6410-sdhci", },
770 { .compatible = "samsung,exynos4210-sdhci",
771 .data = &exynos4_sdhci_drv_data },
772 {},
773};
774MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
775#endif
776
777static struct platform_driver sdhci_s3c_driver = {
778 .probe = sdhci_s3c_probe,
779 .remove = sdhci_s3c_remove,
780 .id_table = sdhci_s3c_driver_ids,
781 .driver = {
782 .name = "s3c-sdhci",
783 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
784 .pm = &sdhci_s3c_pmops,
785 },
786};
787
788module_platform_driver(sdhci_s3c_driver);
789
790MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
791MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
792MODULE_LICENSE("GPL v2");
793MODULE_ALIAS("platform:s3c-sdhci");
794