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5
6#include <linux/io.h>
7#include <linux/of.h>
8#include <linux/clk.h>
9#include <linux/iopoll.h>
10#include <linux/module.h>
11#include <linux/mtd/rawnand.h>
12#include <linux/dmaengine.h>
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15
16
17#define PBUS_CMD 0
18#define PBUS_ADDR 4
19#define PBUS_DATA 8
20
21
22#define NFC_STATUS 0x00
23#define NFC_FLASH_CMD 0x04
24#define NFC_DEVICE_CFG 0x08
25#define NFC_TIMING1 0x0c
26#define NFC_TIMING2 0x10
27#define NFC_XFER_CFG 0x14
28#define NFC_PKT_0_CFG 0x18
29#define NFC_PKT_N_CFG 0x1c
30#define NFC_BB_CFG 0x20
31#define NFC_ADDR_PAGE 0x24
32#define NFC_ADDR_OFFSET 0x28
33#define NFC_XFER_STATUS 0x2c
34
35
36#define CMD_READY BIT(31)
37
38
39#define NFC_READ 1
40#define NFC_WRITE 2
41
42
43#define PAGE_IS_EMPTY BIT(16)
44
45
46#define METADATA 0x000
47#define ERROR_REPORT 0x1c0
48
49
50
51
52
53
54
55#define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f)
56#define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f)
57#define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0)
58#define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0)
59
60
61#define PBUS_CS_CTRL 0x83c
62#define PBUS_PAD_MODE 0x8f0
63
64
65#define PBUS_IORDY BIT(31)
66
67
68
69
70
71
72
73#define MODE_RAW 0
74#define MODE_NFC BIT(31)
75
76#define METADATA_SIZE 4
77#define BBM_SIZE 6
78#define FIELD_ORDER 15
79
80#define MAX_CS 4
81
82struct tango_nfc {
83 struct nand_controller hw;
84 void __iomem *reg_base;
85 void __iomem *mem_base;
86 void __iomem *pbus_base;
87 struct tango_chip *chips[MAX_CS];
88 struct dma_chan *chan;
89 int freq_kHz;
90};
91
92#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw)
93
94struct tango_chip {
95 struct nand_chip nand_chip;
96 void __iomem *base;
97 u32 timing1;
98 u32 timing2;
99 u32 xfer_cfg;
100 u32 pkt_0_cfg;
101 u32 pkt_n_cfg;
102 u32 bb_cfg;
103};
104
105#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip)
106
107#define XFER_CFG(cs, page_count, steps, metadata_size) \
108 ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size))
109
110#define PKT_CFG(size, strength) ((size) << 16 | (strength))
111
112#define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size))
113
114#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3))
115
116static void tango_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl)
117{
118 struct tango_chip *tchip = to_tango_chip(chip);
119
120 if (ctrl & NAND_CLE)
121 writeb_relaxed(dat, tchip->base + PBUS_CMD);
122
123 if (ctrl & NAND_ALE)
124 writeb_relaxed(dat, tchip->base + PBUS_ADDR);
125}
126
127static int tango_dev_ready(struct nand_chip *chip)
128{
129 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
130
131 return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY;
132}
133
134static u8 tango_read_byte(struct nand_chip *chip)
135{
136 struct tango_chip *tchip = to_tango_chip(chip);
137
138 return readb_relaxed(tchip->base + PBUS_DATA);
139}
140
141static void tango_read_buf(struct nand_chip *chip, u8 *buf, int len)
142{
143 struct tango_chip *tchip = to_tango_chip(chip);
144
145 ioread8_rep(tchip->base + PBUS_DATA, buf, len);
146}
147
148static void tango_write_buf(struct nand_chip *chip, const u8 *buf, int len)
149{
150 struct tango_chip *tchip = to_tango_chip(chip);
151
152 iowrite8_rep(tchip->base + PBUS_DATA, buf, len);
153}
154
155static void tango_select_chip(struct nand_chip *chip, int idx)
156{
157 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
158 struct tango_chip *tchip = to_tango_chip(chip);
159
160 if (idx < 0)
161 return;
162
163 writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1);
164 writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2);
165 writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG);
166 writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG);
167 writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG);
168 writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG);
169}
170
171
172
173
174
175static int check_erased_page(struct nand_chip *chip, u8 *buf)
176{
177 struct mtd_info *mtd = nand_to_mtd(chip);
178 u8 *meta = chip->oob_poi + BBM_SIZE;
179 u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE;
180 const int ecc_size = chip->ecc.bytes;
181 const int pkt_size = chip->ecc.size;
182 int i, res, meta_len, bitflips = 0;
183
184 for (i = 0; i < chip->ecc.steps; ++i) {
185 meta_len = i ? 0 : METADATA_SIZE;
186 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
187 meta, meta_len,
188 chip->ecc.strength);
189 if (res < 0)
190 mtd->ecc_stats.failed++;
191 else
192 mtd->ecc_stats.corrected += res;
193
194 bitflips = max(res, bitflips);
195 buf += pkt_size;
196 ecc += ecc_size;
197 }
198
199 return bitflips;
200}
201
202static int decode_error_report(struct nand_chip *chip)
203{
204 u32 status, res;
205 struct mtd_info *mtd = nand_to_mtd(chip);
206 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
207
208 status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS);
209 if (status & PAGE_IS_EMPTY)
210 return 0;
211
212 res = readl_relaxed(nfc->mem_base + ERROR_REPORT);
213
214 if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res))
215 return -EBADMSG;
216
217
218 mtd->ecc_stats.corrected +=
219 ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res);
220
221 return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res));
222}
223
224static void tango_dma_callback(void *arg)
225{
226 complete(arg);
227}
228
229static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd,
230 const void *buf, int len, int page)
231{
232 void __iomem *addr = nfc->reg_base + NFC_STATUS;
233 struct dma_chan *chan = nfc->chan;
234 struct dma_async_tx_descriptor *desc;
235 enum dma_transfer_direction tdir;
236 struct scatterlist sg;
237 struct completion tx_done;
238 int err = -EIO;
239 u32 res, val;
240
241 sg_init_one(&sg, buf, len);
242 if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1)
243 return -EIO;
244
245 tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
246 desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT);
247 if (!desc)
248 goto dma_unmap;
249
250 desc->callback = tango_dma_callback;
251 desc->callback_param = &tx_done;
252 init_completion(&tx_done);
253
254 writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE);
255
256 writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE);
257 writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET);
258 writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD);
259
260 dmaengine_submit(desc);
261 dma_async_issue_pending(chan);
262
263 res = wait_for_completion_timeout(&tx_done, HZ);
264 if (res > 0)
265 err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000);
266
267 writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
268
269dma_unmap:
270 dma_unmap_sg(chan->device->dev, &sg, 1, dir);
271
272 return err;
273}
274
275static int tango_read_page(struct nand_chip *chip, u8 *buf,
276 int oob_required, int page)
277{
278 struct mtd_info *mtd = nand_to_mtd(chip);
279 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
280 int err, res, len = mtd->writesize;
281
282 if (oob_required)
283 chip->ecc.read_oob(chip, page);
284
285 err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page);
286 if (err)
287 return err;
288
289 res = decode_error_report(chip);
290 if (res < 0) {
291 chip->ecc.read_oob_raw(chip, page);
292 res = check_erased_page(chip, buf);
293 }
294
295 return res;
296}
297
298static int tango_write_page(struct nand_chip *chip, const u8 *buf,
299 int oob_required, int page)
300{
301 struct mtd_info *mtd = nand_to_mtd(chip);
302 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
303 int err, status, len = mtd->writesize;
304
305
306 if (oob_required)
307 return -ENOTSUPP;
308
309 writel_relaxed(0xffffffff, nfc->mem_base + METADATA);
310 err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page);
311 if (err)
312 return err;
313
314 status = chip->legacy.waitfunc(chip);
315 if (status & NAND_STATUS_FAIL)
316 return -EIO;
317
318 return 0;
319}
320
321static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos)
322{
323 *pos += len;
324
325 if (!*buf) {
326
327 nand_change_read_column_op(chip, *pos, NULL, 0, false);
328 } else {
329 tango_read_buf(chip, *buf, len);
330 *buf += len;
331 }
332}
333
334static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos)
335{
336 *pos += len;
337
338 if (!*buf) {
339
340 nand_change_write_column_op(chip, *pos, NULL, 0, false);
341 } else {
342 tango_write_buf(chip, *buf, len);
343 *buf += len;
344 }
345}
346
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353
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356
357
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359
360
361
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363
364
365
366static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
367{
368 struct mtd_info *mtd = nand_to_mtd(chip);
369 u8 *oob_orig = oob;
370 const int page_size = mtd->writesize;
371 const int ecc_size = chip->ecc.bytes;
372 const int pkt_size = chip->ecc.size;
373 int pos = 0;
374 int rem = page_size;
375
376 if (oob)
377 oob += BBM_SIZE;
378
379 aux_read(chip, &oob, METADATA_SIZE, &pos);
380
381 while (rem > pkt_size) {
382 aux_read(chip, &buf, pkt_size, &pos);
383 aux_read(chip, &oob, ecc_size, &pos);
384 rem = page_size - pos;
385 }
386
387 aux_read(chip, &buf, rem, &pos);
388 aux_read(chip, &oob_orig, BBM_SIZE, &pos);
389 aux_read(chip, &buf, pkt_size - rem, &pos);
390 aux_read(chip, &oob, ecc_size, &pos);
391}
392
393static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
394{
395 struct mtd_info *mtd = nand_to_mtd(chip);
396 const u8 *oob_orig = oob;
397 const int page_size = mtd->writesize;
398 const int ecc_size = chip->ecc.bytes;
399 const int pkt_size = chip->ecc.size;
400 int pos = 0;
401 int rem = page_size;
402
403 if (oob)
404 oob += BBM_SIZE;
405
406 aux_write(chip, &oob, METADATA_SIZE, &pos);
407
408 while (rem > pkt_size) {
409 aux_write(chip, &buf, pkt_size, &pos);
410 aux_write(chip, &oob, ecc_size, &pos);
411 rem = page_size - pos;
412 }
413
414 aux_write(chip, &buf, rem, &pos);
415 aux_write(chip, &oob_orig, BBM_SIZE, &pos);
416 aux_write(chip, &buf, pkt_size - rem, &pos);
417 aux_write(chip, &oob, ecc_size, &pos);
418}
419
420static int tango_read_page_raw(struct nand_chip *chip, u8 *buf,
421 int oob_required, int page)
422{
423 nand_read_page_op(chip, page, 0, NULL, 0);
424 raw_read(chip, buf, chip->oob_poi);
425 return 0;
426}
427
428static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf,
429 int oob_required, int page)
430{
431 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
432 raw_write(chip, buf, chip->oob_poi);
433 return nand_prog_page_end_op(chip);
434}
435
436static int tango_read_oob(struct nand_chip *chip, int page)
437{
438 nand_read_page_op(chip, page, 0, NULL, 0);
439 raw_read(chip, NULL, chip->oob_poi);
440 return 0;
441}
442
443static int tango_write_oob(struct nand_chip *chip, int page)
444{
445 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
446 raw_write(chip, NULL, chip->oob_poi);
447 return nand_prog_page_end_op(chip);
448}
449
450static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
451{
452 struct nand_chip *chip = mtd_to_nand(mtd);
453 struct nand_ecc_ctrl *ecc = &chip->ecc;
454
455 if (idx >= ecc->steps)
456 return -ERANGE;
457
458 res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx;
459 res->length = ecc->bytes;
460
461 return 0;
462}
463
464static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
465{
466 return -ERANGE;
467}
468
469static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = {
470 .ecc = oob_ecc,
471 .free = oob_free,
472};
473
474static u32 to_ticks(int kHz, int ps)
475{
476 return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC);
477}
478
479static int tango_set_timings(struct nand_chip *chip, int csline,
480 const struct nand_data_interface *conf)
481{
482 const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
483 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
484 struct tango_chip *tchip = to_tango_chip(chip);
485 u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr;
486 int kHz = nfc->freq_kHz;
487
488 if (IS_ERR(sdr))
489 return PTR_ERR(sdr);
490
491 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
492 return 0;
493
494 Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max);
495 Textw = to_ticks(kHz, sdr->tWB_max);
496 Twc = to_ticks(kHz, sdr->tWC_min);
497 Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min);
498
499 Tacc = to_ticks(kHz, sdr->tREA_max);
500 Thold = to_ticks(kHz, sdr->tREH_min);
501 Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min);
502 Textr = to_ticks(kHz, sdr->tRHZ_max);
503
504 tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw);
505 tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr);
506
507 return 0;
508}
509
510static int tango_attach_chip(struct nand_chip *chip)
511{
512 struct nand_ecc_ctrl *ecc = &chip->ecc;
513
514 ecc->mode = NAND_ECC_HW;
515 ecc->algo = NAND_ECC_BCH;
516 ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
517
518 ecc->read_page_raw = tango_read_page_raw;
519 ecc->write_page_raw = tango_write_page_raw;
520 ecc->read_page = tango_read_page;
521 ecc->write_page = tango_write_page;
522 ecc->read_oob = tango_read_oob;
523 ecc->write_oob = tango_write_oob;
524
525 return 0;
526}
527
528static const struct nand_controller_ops tango_controller_ops = {
529 .attach_chip = tango_attach_chip,
530 .setup_data_interface = tango_set_timings,
531};
532
533static int chip_init(struct device *dev, struct device_node *np)
534{
535 u32 cs;
536 int err, res;
537 struct mtd_info *mtd;
538 struct nand_chip *chip;
539 struct tango_chip *tchip;
540 struct nand_ecc_ctrl *ecc;
541 struct tango_nfc *nfc = dev_get_drvdata(dev);
542
543 tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL);
544 if (!tchip)
545 return -ENOMEM;
546
547 res = of_property_count_u32_elems(np, "reg");
548 if (res < 0)
549 return res;
550
551 if (res != 1)
552 return -ENOTSUPP;
553
554 err = of_property_read_u32_index(np, "reg", 0, &cs);
555 if (err)
556 return err;
557
558 if (cs >= MAX_CS)
559 return -EINVAL;
560
561 chip = &tchip->nand_chip;
562 ecc = &chip->ecc;
563 mtd = nand_to_mtd(chip);
564
565 chip->legacy.read_byte = tango_read_byte;
566 chip->legacy.write_buf = tango_write_buf;
567 chip->legacy.read_buf = tango_read_buf;
568 chip->legacy.select_chip = tango_select_chip;
569 chip->legacy.cmd_ctrl = tango_cmd_ctrl;
570 chip->legacy.dev_ready = tango_dev_ready;
571 chip->options = NAND_USES_DMA |
572 NAND_NO_SUBPAGE_WRITE |
573 NAND_WAIT_TCCS;
574 chip->controller = &nfc->hw;
575 tchip->base = nfc->pbus_base + (cs * 256);
576
577 nand_set_flash_node(chip, np);
578 mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops);
579 mtd->dev.parent = dev;
580
581 err = nand_scan(chip, 1);
582 if (err)
583 return err;
584
585 tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE);
586 tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength);
587 tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength);
588 tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE);
589
590 err = mtd_device_register(mtd, NULL, 0);
591 if (err) {
592 nand_cleanup(chip);
593 return err;
594 }
595
596 nfc->chips[cs] = tchip;
597
598 return 0;
599}
600
601static int tango_nand_remove(struct platform_device *pdev)
602{
603 struct tango_nfc *nfc = platform_get_drvdata(pdev);
604 struct nand_chip *chip;
605 int cs, ret;
606
607 dma_release_channel(nfc->chan);
608
609 for (cs = 0; cs < MAX_CS; ++cs) {
610 if (nfc->chips[cs]) {
611 chip = &nfc->chips[cs]->nand_chip;
612 ret = mtd_device_unregister(nand_to_mtd(chip));
613 WARN_ON(ret);
614 nand_cleanup(chip);
615 }
616 }
617
618 return 0;
619}
620
621static int tango_nand_probe(struct platform_device *pdev)
622{
623 int err;
624 struct clk *clk;
625 struct resource *res;
626 struct tango_nfc *nfc;
627 struct device_node *np;
628
629 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
630 if (!nfc)
631 return -ENOMEM;
632
633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
634 nfc->reg_base = devm_ioremap_resource(&pdev->dev, res);
635 if (IS_ERR(nfc->reg_base))
636 return PTR_ERR(nfc->reg_base);
637
638 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
639 nfc->mem_base = devm_ioremap_resource(&pdev->dev, res);
640 if (IS_ERR(nfc->mem_base))
641 return PTR_ERR(nfc->mem_base);
642
643 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
644 nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res);
645 if (IS_ERR(nfc->pbus_base))
646 return PTR_ERR(nfc->pbus_base);
647
648 writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
649
650 clk = devm_clk_get(&pdev->dev, NULL);
651 if (IS_ERR(clk))
652 return PTR_ERR(clk);
653
654 nfc->chan = dma_request_chan(&pdev->dev, "rxtx");
655 if (IS_ERR(nfc->chan))
656 return PTR_ERR(nfc->chan);
657
658 platform_set_drvdata(pdev, nfc);
659 nand_controller_init(&nfc->hw);
660 nfc->hw.ops = &tango_controller_ops;
661 nfc->freq_kHz = clk_get_rate(clk) / 1000;
662
663 for_each_child_of_node(pdev->dev.of_node, np) {
664 err = chip_init(&pdev->dev, np);
665 if (err) {
666 tango_nand_remove(pdev);
667 of_node_put(np);
668 return err;
669 }
670 }
671
672 return 0;
673}
674
675static const struct of_device_id tango_nand_ids[] = {
676 { .compatible = "sigma,smp8758-nand" },
677 { }
678};
679MODULE_DEVICE_TABLE(of, tango_nand_ids);
680
681static struct platform_driver tango_nand_driver = {
682 .probe = tango_nand_probe,
683 .remove = tango_nand_remove,
684 .driver = {
685 .name = "tango-nand",
686 .of_match_table = tango_nand_ids,
687 },
688};
689
690module_platform_driver(tango_nand_driver);
691
692MODULE_LICENSE("GPL");
693MODULE_AUTHOR("Sigma Designs");
694MODULE_DESCRIPTION("Tango4 NAND Flash controller driver");
695
