LXR linux/drivers/net/can/m_can/m

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* CAN bus driver for Bosch M_CAN controller
   3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4 */
   5
   6#ifndef _CAN_M_CAN_H_
   7#define _CAN_M_CAN_H_
   8
   9#include <linux/can/core.h>
  10#include <linux/can/led.h>
  11#include <linux/completion.h>
  12#include <linux/device.h>
  13#include <linux/dma-mapping.h>
  14#include <linux/freezer.h>
  15#include <linux/slab.h>
  16#include <linux/uaccess.h>
  17#include <linux/clk.h>
  18#include <linux/delay.h>
  19#include <linux/interrupt.h>
  20#include <linux/io.h>
  21#include <linux/kernel.h>
  22#include <linux/module.h>
  23#include <linux/netdevice.h>
  24#include <linux/of.h>
  25#include <linux/of_device.h>
  26#include <linux/pm_runtime.h>
  27#include <linux/iopoll.h>
  28#include <linux/can/dev.h>
  29#include <linux/pinctrl/consumer.h>
  30
  31/* m_can lec values */
  32enum m_can_lec_type {
  33        LEC_NO_ERROR = 0,
  34        LEC_STUFF_ERROR,
  35        LEC_FORM_ERROR,
  36        LEC_ACK_ERROR,
  37        LEC_BIT1_ERROR,
  38        LEC_BIT0_ERROR,
  39        LEC_CRC_ERROR,
  40        LEC_UNUSED,
  41};
  42
  43enum m_can_mram_cfg {
  44        MRAM_SIDF = 0,
  45        MRAM_XIDF,
  46        MRAM_RXF0,
  47        MRAM_RXF1,
  48        MRAM_RXB,
  49        MRAM_TXE,
  50        MRAM_TXB,
  51        MRAM_CFG_NUM,
  52};
  53
  54/* address offset and element number for each FIFO/Buffer in the Message RAM */
  55struct mram_cfg {
  56        u16 off;
  57        u8  num;
  58};
  59
  60struct m_can_classdev;
  61struct m_can_ops {
  62        /* Device specific call backs */
  63        int (*clear_interrupts)(struct m_can_classdev *cdev);
  64        u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
  65        int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
  66        u32 (*read_fifo)(struct m_can_classdev *cdev, int addr_offset);
  67        int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
  68                          int val);
  69        int (*init)(struct m_can_classdev *cdev);
  70};
  71
  72struct m_can_classdev {
  73        struct can_priv can;
  74        struct napi_struct napi;
  75        struct net_device *net;
  76        struct device *dev;
  77        struct clk *hclk;
  78        struct clk *cclk;
  79
  80        struct workqueue_struct *tx_wq;
  81        struct work_struct tx_work;
  82        struct sk_buff *tx_skb;
  83
  84        struct can_bittiming_const *bit_timing;
  85        struct can_bittiming_const *data_timing;
  86
  87        struct m_can_ops *ops;
  88
  89        void *device_data;
  90
  91        int version;
  92        int freq;
  93        u32 irqstatus;
  94
  95        int pm_clock_support;
  96        int is_peripheral;
  97
  98        struct mram_cfg mcfg[MRAM_CFG_NUM];
  99};
 100
 101struct m_can_classdev *m_can_class_allocate_dev(struct device *dev);
 102int m_can_class_register(struct m_can_classdev *cdev);
 103void m_can_class_unregister(struct m_can_classdev *cdev);
 104int m_can_class_get_clocks(struct m_can_classdev *cdev);
 105void m_can_init_ram(struct m_can_classdev *priv);
 106void m_can_config_endisable(struct m_can_classdev *priv, bool enable);
 107
 108int m_can_class_suspend(struct device *dev);
 109int m_can_class_resume(struct device *dev);
 110#endif  /* _CAN_M_H_ */
 111