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35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
48#include <linux/vmalloc.h>
49#include <linux/rhashtable.h>
50#include <linux/etherdevice.h>
51#include <linux/net_tstamp.h>
52#include <linux/ptp_clock_kernel.h>
53#include <linux/ptp_classify.h>
54#include <linux/crash_dump.h>
55#include <linux/thermal.h>
56#include <asm/io.h>
57#include "t4_chip_type.h"
58#include "cxgb4_uld.h"
59#include "t4fw_api.h"
60
61#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
62extern struct list_head adapter_list;
63extern struct list_head uld_list;
64extern struct mutex uld_mutex;
65
66
67
68
69
70#define ETHTXQ_STOP_THRES \
71 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
72
73#define FW_PARAM_DEV(param) \
74 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
75 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
76
77#define FW_PARAM_PFVF(param) \
78 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
79 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
80 FW_PARAMS_PARAM_Y_V(0) | \
81 FW_PARAMS_PARAM_Z_V(0))
82
83enum {
84 MAX_NPORTS = 4,
85 SERNUM_LEN = 24,
86 EC_LEN = 16,
87 ID_LEN = 16,
88 PN_LEN = 16,
89 MACADDR_LEN = 12,
90};
91
92enum {
93 T4_REGMAP_SIZE = (160 * 1024),
94 T5_REGMAP_SIZE = (332 * 1024),
95};
96
97enum {
98 MEM_EDC0,
99 MEM_EDC1,
100 MEM_MC,
101 MEM_MC0 = MEM_MC,
102 MEM_MC1,
103 MEM_HMA,
104};
105
106enum {
107 MEMWIN0_APERTURE = 2048,
108 MEMWIN0_BASE = 0x1b800,
109 MEMWIN1_APERTURE = 32768,
110 MEMWIN1_BASE = 0x28000,
111 MEMWIN1_BASE_T5 = 0x52000,
112 MEMWIN2_APERTURE = 65536,
113 MEMWIN2_BASE = 0x30000,
114 MEMWIN2_APERTURE_T5 = 131072,
115 MEMWIN2_BASE_T5 = 0x60000,
116};
117
118enum dev_master {
119 MASTER_CANT,
120 MASTER_MAY,
121 MASTER_MUST
122};
123
124enum dev_state {
125 DEV_STATE_UNINIT,
126 DEV_STATE_INIT,
127 DEV_STATE_ERR
128};
129
130enum cc_pause {
131 PAUSE_RX = 1 << 0,
132 PAUSE_TX = 1 << 1,
133 PAUSE_AUTONEG = 1 << 2
134};
135
136enum cc_fec {
137 FEC_AUTO = 1 << 0,
138 FEC_RS = 1 << 1,
139 FEC_BASER_RS = 1 << 2
140};
141
142struct port_stats {
143 u64 tx_octets;
144 u64 tx_frames;
145 u64 tx_bcast_frames;
146 u64 tx_mcast_frames;
147 u64 tx_ucast_frames;
148 u64 tx_error_frames;
149
150 u64 tx_frames_64;
151 u64 tx_frames_65_127;
152 u64 tx_frames_128_255;
153 u64 tx_frames_256_511;
154 u64 tx_frames_512_1023;
155 u64 tx_frames_1024_1518;
156 u64 tx_frames_1519_max;
157
158 u64 tx_drop;
159 u64 tx_pause;
160 u64 tx_ppp0;
161 u64 tx_ppp1;
162 u64 tx_ppp2;
163 u64 tx_ppp3;
164 u64 tx_ppp4;
165 u64 tx_ppp5;
166 u64 tx_ppp6;
167 u64 tx_ppp7;
168
169 u64 rx_octets;
170 u64 rx_frames;
171 u64 rx_bcast_frames;
172 u64 rx_mcast_frames;
173 u64 rx_ucast_frames;
174 u64 rx_too_long;
175 u64 rx_jabber;
176 u64 rx_fcs_err;
177 u64 rx_len_err;
178 u64 rx_symbol_err;
179 u64 rx_runt;
180
181 u64 rx_frames_64;
182 u64 rx_frames_65_127;
183 u64 rx_frames_128_255;
184 u64 rx_frames_256_511;
185 u64 rx_frames_512_1023;
186 u64 rx_frames_1024_1518;
187 u64 rx_frames_1519_max;
188
189 u64 rx_pause;
190 u64 rx_ppp0;
191 u64 rx_ppp1;
192 u64 rx_ppp2;
193 u64 rx_ppp3;
194 u64 rx_ppp4;
195 u64 rx_ppp5;
196 u64 rx_ppp6;
197 u64 rx_ppp7;
198
199 u64 rx_ovflow0;
200 u64 rx_ovflow1;
201 u64 rx_ovflow2;
202 u64 rx_ovflow3;
203 u64 rx_trunc0;
204 u64 rx_trunc1;
205 u64 rx_trunc2;
206 u64 rx_trunc3;
207};
208
209struct lb_port_stats {
210 u64 octets;
211 u64 frames;
212 u64 bcast_frames;
213 u64 mcast_frames;
214 u64 ucast_frames;
215 u64 error_frames;
216
217 u64 frames_64;
218 u64 frames_65_127;
219 u64 frames_128_255;
220 u64 frames_256_511;
221 u64 frames_512_1023;
222 u64 frames_1024_1518;
223 u64 frames_1519_max;
224
225 u64 drop;
226
227 u64 ovflow0;
228 u64 ovflow1;
229 u64 ovflow2;
230 u64 ovflow3;
231 u64 trunc0;
232 u64 trunc1;
233 u64 trunc2;
234 u64 trunc3;
235};
236
237struct tp_tcp_stats {
238 u32 tcp_out_rsts;
239 u64 tcp_in_segs;
240 u64 tcp_out_segs;
241 u64 tcp_retrans_segs;
242};
243
244struct tp_usm_stats {
245 u32 frames;
246 u32 drops;
247 u64 octets;
248};
249
250struct tp_fcoe_stats {
251 u32 frames_ddp;
252 u32 frames_drop;
253 u64 octets_ddp;
254};
255
256struct tp_err_stats {
257 u32 mac_in_errs[4];
258 u32 hdr_in_errs[4];
259 u32 tcp_in_errs[4];
260 u32 tnl_cong_drops[4];
261 u32 ofld_chan_drops[4];
262 u32 tnl_tx_drops[4];
263 u32 ofld_vlan_drops[4];
264 u32 tcp6_in_errs[4];
265 u32 ofld_no_neigh;
266 u32 ofld_cong_defer;
267};
268
269struct tp_cpl_stats {
270 u32 req[4];
271 u32 rsp[4];
272};
273
274struct tp_rdma_stats {
275 u32 rqe_dfr_pkt;
276 u32 rqe_dfr_mod;
277};
278
279struct sge_params {
280 u32 hps;
281 u32 eq_qpp;
282 u32 iq_qpp;
283};
284
285struct tp_params {
286 unsigned int tre;
287 unsigned int la_mask;
288 unsigned short tx_modq_map;
289
290
291 uint32_t dack_re;
292 unsigned short tx_modq[NCHAN];
293
294 u32 vlan_pri_map;
295 u32 filter_mask;
296 u32 ingress_config;
297
298
299
300
301 int rx_pkt_encap;
302
303
304
305
306
307
308
309
310
311
312
313
314 int fcoe_shift;
315 int port_shift;
316 int vnic_shift;
317 int vlan_shift;
318 int tos_shift;
319 int protocol_shift;
320 int ethertype_shift;
321 int macmatch_shift;
322 int matchtype_shift;
323 int frag_shift;
324
325 u64 hash_filter_mask;
326};
327
328struct vpd_params {
329 unsigned int cclk;
330 u8 ec[EC_LEN + 1];
331 u8 sn[SERNUM_LEN + 1];
332 u8 id[ID_LEN + 1];
333 u8 pn[PN_LEN + 1];
334 u8 na[MACADDR_LEN + 1];
335};
336
337
338
339struct pf_resources {
340 unsigned int nvi;
341 unsigned int neq;
342 unsigned int nethctrl;
343 unsigned int niqflint;
344 unsigned int niq;
345 unsigned int tc;
346 unsigned int pmask;
347 unsigned int nexactf;
348 unsigned int r_caps;
349 unsigned int wx_caps;
350};
351
352struct pci_params {
353 unsigned int vpd_cap_addr;
354 unsigned char speed;
355 unsigned char width;
356};
357
358struct devlog_params {
359 u32 memtype;
360 u32 start;
361 u32 size;
362};
363
364
365struct arch_specific_params {
366 u8 nchan;
367 u8 pm_stats_cnt;
368 u8 cng_ch_bits_log;
369 u16 mps_rplc_size;
370 u16 vfcount;
371 u32 sge_fl_db;
372 u16 mps_tcam_size;
373};
374
375struct adapter_params {
376 struct sge_params sge;
377 struct tp_params tp;
378 struct vpd_params vpd;
379 struct pf_resources pfres;
380 struct pci_params pci;
381 struct devlog_params devlog;
382 enum pcie_memwin drv_memwin;
383
384 unsigned int cim_la_size;
385
386 unsigned int sf_size;
387 unsigned int sf_nsec;
388
389 unsigned int fw_vers;
390 unsigned int bs_vers;
391 unsigned int tp_vers;
392 unsigned int er_vers;
393 unsigned int scfg_vers;
394 unsigned int vpd_vers;
395 u8 api_vers[7];
396
397 unsigned short mtus[NMTUS];
398 unsigned short a_wnd[NCCTRL_WIN];
399 unsigned short b_wnd[NCCTRL_WIN];
400
401 unsigned char nports;
402 unsigned char portvec;
403 enum chip_type chip;
404 struct arch_specific_params arch;
405 unsigned char offload;
406 unsigned char crypto;
407 unsigned char ethofld;
408
409 unsigned char bypass;
410 unsigned char hash_filter;
411
412 unsigned int ofldq_wr_cred;
413 bool ulptx_memwrite_dsgl;
414
415 unsigned int nsched_cls;
416 unsigned int max_ordird_qp;
417 unsigned int max_ird_adapter;
418 bool fr_nsmr_tpte_wr_support;
419 u8 fw_caps_support;
420 bool filter2_wr_support;
421 unsigned int viid_smt_extn_support:1;
422
423
424
425
426 u8 mps_bg_map[MAX_NPORTS];
427 bool write_w_imm_support;
428 bool write_cmpl_support;
429};
430
431
432
433
434struct sge_idma_monitor_state {
435 unsigned int idma_1s_thresh;
436 unsigned int idma_stalled[2];
437 unsigned int idma_state[2];
438 unsigned int idma_qid[2];
439 unsigned int idma_warn[2];
440};
441
442
443
444
445
446struct mbox_cmd {
447 u64 cmd[MBOX_LEN / 8];
448 u64 timestamp;
449 u32 seqno;
450 s16 access;
451 s16 execute;
452};
453
454struct mbox_cmd_log {
455 unsigned int size;
456 unsigned int cursor;
457 u32 seqno;
458
459};
460
461
462
463
464static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
465 unsigned int entry_idx)
466{
467 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
468}
469
470#define FW_VERSION(chip) ( \
471 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
472 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
473 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
474 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
475#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
476
477struct fw_info {
478 u8 chip;
479 char *fs_name;
480 char *fw_mod_name;
481 struct fw_hdr fw_hdr;
482};
483
484struct trace_params {
485 u32 data[TRACE_LEN / 4];
486 u32 mask[TRACE_LEN / 4];
487 unsigned short snap_len;
488 unsigned short min_len;
489 unsigned char skip_ofst;
490 unsigned char skip_len;
491 unsigned char invert;
492 unsigned char port;
493};
494
495
496
497typedef u16 fw_port_cap16_t;
498typedef u32 fw_port_cap32_t;
499
500enum fw_caps {
501 FW_CAPS_UNKNOWN = 0,
502 FW_CAPS16 = 1,
503 FW_CAPS32 = 2,
504};
505
506struct link_config {
507 fw_port_cap32_t pcaps;
508 fw_port_cap32_t def_acaps;
509 fw_port_cap32_t acaps;
510 fw_port_cap32_t lpacaps;
511
512 fw_port_cap32_t speed_caps;
513 unsigned int speed;
514
515 enum cc_pause requested_fc;
516 enum cc_pause fc;
517 enum cc_pause advertised_fc;
518
519 enum cc_fec requested_fec;
520 enum cc_fec fec;
521
522 unsigned char autoneg;
523
524 unsigned char link_ok;
525 unsigned char link_down_rc;
526
527 bool new_module;
528 bool redo_l1cfg;
529};
530
531#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
532
533enum {
534 MAX_ETH_QSETS = 32,
535 MAX_OFLD_QSETS = 16,
536 MAX_CTRL_QUEUES = NCHAN,
537};
538
539enum {
540 MAX_TXQ_ENTRIES = 16384,
541 MAX_CTRL_TXQ_ENTRIES = 1024,
542 MAX_RSPQ_ENTRIES = 16384,
543 MAX_RX_BUFFERS = 16384,
544 MIN_TXQ_ENTRIES = 32,
545 MIN_CTRL_TXQ_ENTRIES = 32,
546 MIN_RSPQ_ENTRIES = 128,
547 MIN_FL_ENTRIES = 16
548};
549
550enum {
551 MAX_TXQ_DESC_SIZE = 64,
552 MAX_RXQ_DESC_SIZE = 128,
553 MAX_FL_DESC_SIZE = 8,
554 MAX_CTRL_TXQ_DESC_SIZE = 64,
555};
556
557enum {
558 INGQ_EXTRAS = 2,
559
560 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
561};
562
563enum {
564 PRIV_FLAG_PORT_TX_VM_BIT,
565};
566
567#define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
568
569#define PRIV_FLAGS_ADAP 0
570#define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
571
572struct adapter;
573struct sge_rspq;
574
575#include "cxgb4_dcb.h"
576
577#ifdef CONFIG_CHELSIO_T4_FCOE
578#include "cxgb4_fcoe.h"
579#endif
580
581struct port_info {
582 struct adapter *adapter;
583 u16 viid;
584 int xact_addr_filt;
585 u16 rss_size;
586 s8 mdio_addr;
587 enum fw_port_type port_type;
588 u8 mod_type;
589 u8 port_id;
590 u8 tx_chan;
591 u8 lport;
592 u8 nqsets;
593 u8 first_qset;
594 u8 rss_mode;
595 struct link_config link_cfg;
596 u16 *rss;
597 struct port_stats stats_base;
598#ifdef CONFIG_CHELSIO_T4_DCB
599 struct port_dcb_info dcb;
600#endif
601#ifdef CONFIG_CHELSIO_T4_FCOE
602 struct cxgb_fcoe fcoe;
603#endif
604 bool rxtstamp;
605 struct hwtstamp_config tstamp_config;
606 bool ptp_enable;
607 struct sched_table *sched_tbl;
608 u32 eth_flags;
609
610
611
612
613 u8 vin;
614 u8 vivld;
615 u8 smt_idx;
616 u8 rx_cchan;
617
618 bool tc_block_shared;
619};
620
621struct dentry;
622struct work_struct;
623
624enum {
625 CXGB4_FULL_INIT_DONE = (1 << 0),
626 CXGB4_DEV_ENABLED = (1 << 1),
627 CXGB4_USING_MSI = (1 << 2),
628 CXGB4_USING_MSIX = (1 << 3),
629 CXGB4_FW_OK = (1 << 4),
630 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
631 CXGB4_USING_SOFT_PARAMS = (1 << 6),
632 CXGB4_MASTER_PF = (1 << 7),
633 CXGB4_FW_OFLD_CONN = (1 << 9),
634 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
635 CXGB4_SHUTTING_DOWN = (1 << 11),
636 CXGB4_SGE_DBQ_TIMER = (1 << 12),
637};
638
639enum {
640 ULP_CRYPTO_LOOKASIDE = 1 << 0,
641 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
642 ULP_CRYPTO_KTLS_INLINE = 1 << 3,
643};
644
645struct rx_sw_desc;
646
647struct sge_fl {
648 unsigned int avail;
649 unsigned int pend_cred;
650 unsigned int cidx;
651 unsigned int pidx;
652 unsigned long alloc_failed;
653 unsigned long large_alloc_failed;
654 unsigned long mapping_err;
655 unsigned long low;
656 unsigned long starving;
657
658 unsigned int cntxt_id;
659 unsigned int size;
660 struct rx_sw_desc *sdesc;
661 __be64 *desc;
662 dma_addr_t addr;
663 void __iomem *bar2_addr;
664 unsigned int bar2_qid;
665};
666
667
668struct pkt_gl {
669 u64 sgetstamp;
670 struct page_frag frags[MAX_SKB_FRAGS];
671 void *va;
672 unsigned int nfrags;
673 unsigned int tot_len;
674};
675
676typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
677 const struct pkt_gl *gl);
678typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
679
680struct t4_lro_mgr {
681#define MAX_LRO_SESSIONS 64
682 u8 lro_session_cnt;
683 unsigned long lro_pkts;
684 unsigned long lro_merged;
685 struct sk_buff_head lroq;
686};
687
688struct sge_rspq {
689 struct napi_struct napi;
690 const __be64 *cur_desc;
691 unsigned int cidx;
692 u8 gen;
693 u8 intr_params;
694 u8 next_intr_params;
695 u8 adaptive_rx;
696 u8 pktcnt_idx;
697 u8 uld;
698 u8 idx;
699 int offset;
700 u16 cntxt_id;
701 u16 abs_id;
702 __be64 *desc;
703 dma_addr_t phys_addr;
704 void __iomem *bar2_addr;
705 unsigned int bar2_qid;
706 unsigned int iqe_len;
707 unsigned int size;
708 struct adapter *adap;
709 struct net_device *netdev;
710 rspq_handler_t handler;
711 rspq_flush_handler_t flush_handler;
712 struct t4_lro_mgr lro_mgr;
713};
714
715struct sge_eth_stats {
716 unsigned long pkts;
717 unsigned long lro_pkts;
718 unsigned long lro_merged;
719 unsigned long rx_cso;
720 unsigned long vlan_ex;
721 unsigned long rx_drops;
722 unsigned long bad_rx_pkts;
723};
724
725struct sge_eth_rxq {
726 struct sge_rspq rspq;
727 struct sge_fl fl;
728 struct sge_eth_stats stats;
729 struct msix_info *msix;
730} ____cacheline_aligned_in_smp;
731
732struct sge_ofld_stats {
733 unsigned long pkts;
734 unsigned long imm;
735 unsigned long an;
736 unsigned long nomem;
737};
738
739struct sge_ofld_rxq {
740 struct sge_rspq rspq;
741 struct sge_fl fl;
742 struct sge_ofld_stats stats;
743 struct msix_info *msix;
744} ____cacheline_aligned_in_smp;
745
746struct tx_desc {
747 __be64 flit[8];
748};
749
750struct ulptx_sgl;
751
752struct tx_sw_desc {
753 struct sk_buff *skb;
754 dma_addr_t addr[MAX_SKB_FRAGS + 1];
755};
756
757struct sge_txq {
758 unsigned int in_use;
759 unsigned int q_type;
760 unsigned int size;
761 unsigned int cidx;
762 unsigned int pidx;
763 unsigned long stops;
764 unsigned long restarts;
765 unsigned int cntxt_id;
766 struct tx_desc *desc;
767 struct tx_sw_desc *sdesc;
768 struct sge_qstat *stat;
769 dma_addr_t phys_addr;
770 spinlock_t db_lock;
771 int db_disabled;
772 unsigned short db_pidx;
773 unsigned short db_pidx_inc;
774 void __iomem *bar2_addr;
775 unsigned int bar2_qid;
776};
777
778struct sge_eth_txq {
779 struct sge_txq q;
780 struct netdev_queue *txq;
781#ifdef CONFIG_CHELSIO_T4_DCB
782 u8 dcb_prio;
783#endif
784 u8 dbqt;
785 unsigned int dbqtimerix;
786 unsigned long tso;
787 unsigned long uso;
788 unsigned long tx_cso;
789 unsigned long vlan_ins;
790 unsigned long mapping_err;
791} ____cacheline_aligned_in_smp;
792
793struct sge_uld_txq {
794 struct sge_txq q;
795 struct adapter *adap;
796 struct sk_buff_head sendq;
797 struct tasklet_struct qresume_tsk;
798 bool service_ofldq_running;
799 u8 full;
800 unsigned long mapping_err;
801} ____cacheline_aligned_in_smp;
802
803struct sge_ctrl_txq {
804 struct sge_txq q;
805 struct adapter *adap;
806 struct sk_buff_head sendq;
807 struct tasklet_struct qresume_tsk;
808 u8 full;
809} ____cacheline_aligned_in_smp;
810
811struct sge_uld_rxq_info {
812 char name[IFNAMSIZ];
813 struct sge_ofld_rxq *uldrxq;
814 u16 *rspq_id;
815 u16 nrxq;
816 u16 nciq;
817 u8 uld;
818};
819
820struct sge_uld_txq_info {
821 struct sge_uld_txq *uldtxq;
822 atomic_t users;
823 u16 ntxq;
824};
825
826
827struct cxgb4_uld_list {
828 struct cxgb4_uld_info uld_info;
829 struct list_head list_node;
830 enum cxgb4_uld uld_type;
831};
832
833enum sge_eosw_state {
834 CXGB4_EO_STATE_CLOSED = 0,
835 CXGB4_EO_STATE_FLOWC_OPEN_SEND,
836 CXGB4_EO_STATE_FLOWC_OPEN_REPLY,
837 CXGB4_EO_STATE_ACTIVE,
838 CXGB4_EO_STATE_FLOWC_CLOSE_SEND,
839 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY,
840};
841
842struct sge_eosw_txq {
843 spinlock_t lock;
844 enum sge_eosw_state state;
845 struct tx_sw_desc *desc;
846 u32 ndesc;
847 u32 pidx;
848 u32 last_pidx;
849 u32 cidx;
850 u32 last_cidx;
851 u32 flowc_idx;
852 u32 inuse;
853
854 u32 cred;
855 u32 ncompl;
856 u32 last_compl;
857
858 u32 eotid;
859 u32 hwtid;
860
861 u32 hwqid;
862 struct net_device *netdev;
863 struct tasklet_struct qresume_tsk;
864 struct completion completion;
865};
866
867struct sge_eohw_txq {
868 spinlock_t lock;
869 struct sge_txq q;
870 struct adapter *adap;
871 unsigned long tso;
872 unsigned long uso;
873 unsigned long tx_cso;
874 unsigned long vlan_ins;
875 unsigned long mapping_err;
876};
877
878struct sge {
879 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
880 struct sge_eth_txq ptptxq;
881 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
882
883 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
884 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
885 struct sge_uld_rxq_info **uld_rxq_info;
886 struct sge_uld_txq_info **uld_txq_info;
887
888 struct sge_rspq intrq ____cacheline_aligned_in_smp;
889 spinlock_t intrq_lock;
890
891 struct sge_eohw_txq *eohw_txq;
892 struct sge_ofld_rxq *eohw_rxq;
893
894 u16 max_ethqsets;
895 u16 ethqsets;
896 u16 ethtxq_rover;
897 u16 ofldqsets;
898 u16 nqs_per_uld;
899 u16 eoqsets;
900
901 u16 timer_val[SGE_NTIMERS];
902 u8 counter_val[SGE_NCOUNTERS];
903 u16 dbqtimer_tick;
904 u16 dbqtimer_val[SGE_NDBQTIMERS];
905 u32 fl_pg_order;
906 u32 stat_len;
907 u32 pktshift;
908 u32 fl_align;
909 u32 fl_starve_thres;
910
911 struct sge_idma_monitor_state idma_monitor;
912 unsigned int egr_start;
913 unsigned int egr_sz;
914 unsigned int ingr_start;
915 unsigned int ingr_sz;
916 void **egr_map;
917 struct sge_rspq **ingr_map;
918 unsigned long *starving_fl;
919 unsigned long *txq_maperr;
920 unsigned long *blocked_fl;
921 struct timer_list rx_timer;
922 struct timer_list tx_timer;
923
924 int fwevtq_msix_idx;
925 int nd_msix_idx;
926};
927
928#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
929#define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
930
931struct l2t_data;
932
933#ifdef CONFIG_PCI_IOV
934
935
936
937
938
939#define NUM_OF_PF_WITH_SRIOV 4
940
941#endif
942
943struct doorbell_stats {
944 u32 db_drop;
945 u32 db_empty;
946 u32 db_full;
947};
948
949struct hash_mac_addr {
950 struct list_head list;
951 u8 addr[ETH_ALEN];
952 unsigned int iface_mac;
953};
954
955struct msix_bmap {
956 unsigned long *msix_bmap;
957 unsigned int mapsize;
958 spinlock_t lock;
959};
960
961struct msix_info {
962 unsigned short vec;
963 char desc[IFNAMSIZ + 10];
964 unsigned int idx;
965 cpumask_var_t aff_mask;
966};
967
968struct vf_info {
969 unsigned char vf_mac_addr[ETH_ALEN];
970 unsigned int tx_rate;
971 bool pf_set_mac;
972 u16 vlan;
973 int link_state;
974};
975
976enum {
977 HMA_DMA_MAPPED_FLAG = 1
978};
979
980struct hma_data {
981 unsigned char flags;
982 struct sg_table *sgt;
983 dma_addr_t *phy_addr;
984};
985
986struct mbox_list {
987 struct list_head list;
988};
989
990#if IS_ENABLED(CONFIG_THERMAL)
991struct ch_thermal {
992 struct thermal_zone_device *tzdev;
993 int trip_temp;
994 int trip_type;
995};
996#endif
997
998struct mps_entries_ref {
999 struct list_head list;
1000 u8 addr[ETH_ALEN];
1001 u8 mask[ETH_ALEN];
1002 u16 idx;
1003 refcount_t refcnt;
1004};
1005
1006struct adapter {
1007 void __iomem *regs;
1008 void __iomem *bar2;
1009 u32 t4_bar0;
1010 struct pci_dev *pdev;
1011 struct device *pdev_dev;
1012 const char *name;
1013 unsigned int mbox;
1014 unsigned int pf;
1015 unsigned int flags;
1016 unsigned int adap_idx;
1017 enum chip_type chip;
1018 u32 eth_flags;
1019
1020 int msg_enable;
1021 __be16 vxlan_port;
1022 u8 vxlan_port_cnt;
1023 __be16 geneve_port;
1024 u8 geneve_port_cnt;
1025
1026 struct adapter_params params;
1027 struct cxgb4_virt_res vres;
1028 unsigned int swintr;
1029
1030
1031 struct msix_info *msix_info;
1032 struct msix_bmap msix_bmap;
1033
1034 struct doorbell_stats db_stats;
1035 struct sge sge;
1036
1037 struct net_device *port[MAX_NPORTS];
1038 u8 chan_map[NCHAN];
1039
1040 struct vf_info *vfinfo;
1041 u8 num_vfs;
1042
1043 u32 filter_mode;
1044 unsigned int l2t_start;
1045 unsigned int l2t_end;
1046 struct l2t_data *l2t;
1047 unsigned int clipt_start;
1048 unsigned int clipt_end;
1049 struct clip_tbl *clipt;
1050 unsigned int rawf_start;
1051 unsigned int rawf_cnt;
1052 struct smt_data *smt;
1053 struct cxgb4_uld_info *uld;
1054 void *uld_handle[CXGB4_ULD_MAX];
1055 unsigned int num_uld;
1056 unsigned int num_ofld_uld;
1057 struct list_head list_node;
1058 struct list_head rcu_node;
1059 struct list_head mac_hlist;
1060 struct list_head mps_ref;
1061 spinlock_t mps_ref_lock;
1062
1063 void *iscsi_ppm;
1064
1065 struct tid_info tids;
1066 void **tid_release_head;
1067 spinlock_t tid_release_lock;
1068 struct workqueue_struct *workq;
1069 struct work_struct tid_release_task;
1070 struct work_struct db_full_task;
1071 struct work_struct db_drop_task;
1072 struct work_struct fatal_err_notify_task;
1073 bool tid_release_task_busy;
1074
1075
1076 spinlock_t mbox_lock;
1077 struct mbox_list mlist;
1078
1079
1080#define T4_OS_LOG_MBOX_CMDS 256
1081 struct mbox_cmd_log *mbox_log;
1082
1083 struct mutex uld_mutex;
1084
1085 struct dentry *debugfs_root;
1086 bool use_bd;
1087 bool trace_rss;
1088
1089
1090
1091
1092 struct ptp_clock *ptp_clock;
1093 struct ptp_clock_info ptp_clock_info;
1094 struct sk_buff *ptp_tx_skb;
1095
1096 spinlock_t ptp_lock;
1097 spinlock_t stats_lock;
1098 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1099
1100
1101 struct cxgb4_tc_u32_table *tc_u32;
1102 struct chcr_ktls chcr_ktls;
1103 struct chcr_stats_debug chcr_stats;
1104
1105
1106 bool tc_flower_initialized;
1107 struct rhashtable flower_tbl;
1108 struct rhashtable_params flower_ht_params;
1109 struct timer_list flower_stats_timer;
1110 struct work_struct flower_stats_work;
1111
1112
1113 struct ethtool_dump eth_dump;
1114
1115
1116 struct hma_data hma;
1117
1118 struct srq_data *srq;
1119
1120
1121 struct vmcoredd_data vmcoredd;
1122#if IS_ENABLED(CONFIG_THERMAL)
1123 struct ch_thermal ch_thermal;
1124#endif
1125
1126
1127 struct cxgb4_tc_mqprio *tc_mqprio;
1128
1129
1130 struct cxgb4_tc_matchall *tc_matchall;
1131};
1132
1133
1134
1135
1136struct ch_sched_params {
1137 u8 type;
1138 union {
1139 struct {
1140 u8 level;
1141 u8 mode;
1142 u8 rateunit;
1143 u8 ratemode;
1144 u8 channel;
1145 u8 class;
1146 u32 minrate;
1147 u32 maxrate;
1148 u16 weight;
1149 u16 pktsize;
1150 u16 burstsize;
1151 } params;
1152 } u;
1153};
1154
1155enum {
1156 SCHED_CLASS_TYPE_PACKET = 0,
1157};
1158
1159enum {
1160 SCHED_CLASS_LEVEL_CL_RL = 0,
1161 SCHED_CLASS_LEVEL_CH_RL = 2,
1162};
1163
1164enum {
1165 SCHED_CLASS_MODE_CLASS = 0,
1166 SCHED_CLASS_MODE_FLOW,
1167};
1168
1169enum {
1170 SCHED_CLASS_RATEUNIT_BITS = 0,
1171};
1172
1173enum {
1174 SCHED_CLASS_RATEMODE_ABS = 1,
1175};
1176
1177
1178
1179
1180struct ch_sched_queue {
1181 s8 queue;
1182 s8 class;
1183};
1184
1185
1186
1187
1188struct ch_sched_flowc {
1189 s32 tid;
1190 s8 class;
1191};
1192
1193
1194
1195#define ETHTYPE_BITWIDTH 16
1196#define FRAG_BITWIDTH 1
1197#define MACIDX_BITWIDTH 9
1198#define FCOE_BITWIDTH 1
1199#define IPORT_BITWIDTH 3
1200#define MATCHTYPE_BITWIDTH 3
1201#define PROTO_BITWIDTH 8
1202#define TOS_BITWIDTH 8
1203#define PF_BITWIDTH 8
1204#define VF_BITWIDTH 8
1205#define IVLAN_BITWIDTH 16
1206#define OVLAN_BITWIDTH 16
1207#define ENCAP_VNI_BITWIDTH 24
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226struct ch_filter_tuple {
1227
1228
1229
1230
1231
1232
1233 uint32_t ethtype:ETHTYPE_BITWIDTH;
1234 uint32_t frag:FRAG_BITWIDTH;
1235 uint32_t ivlan_vld:1;
1236 uint32_t ovlan_vld:1;
1237 uint32_t pfvf_vld:1;
1238 uint32_t encap_vld:1;
1239 uint32_t macidx:MACIDX_BITWIDTH;
1240 uint32_t fcoe:FCOE_BITWIDTH;
1241 uint32_t iport:IPORT_BITWIDTH;
1242 uint32_t matchtype:MATCHTYPE_BITWIDTH;
1243 uint32_t proto:PROTO_BITWIDTH;
1244 uint32_t tos:TOS_BITWIDTH;
1245 uint32_t pf:PF_BITWIDTH;
1246 uint32_t vf:VF_BITWIDTH;
1247 uint32_t ivlan:IVLAN_BITWIDTH;
1248 uint32_t ovlan:OVLAN_BITWIDTH;
1249 uint32_t vni:ENCAP_VNI_BITWIDTH;
1250
1251
1252
1253
1254 uint8_t lip[16];
1255 uint8_t fip[16];
1256 uint16_t lport;
1257 uint16_t fport;
1258};
1259
1260
1261
1262struct ch_filter_specification {
1263
1264
1265 uint32_t hitcnts:1;
1266 uint32_t prio:1;
1267
1268
1269
1270
1271 uint32_t type:1;
1272 u32 hash:1;
1273
1274
1275
1276
1277
1278 uint32_t action:2;
1279
1280 uint32_t rpttid:1;
1281
1282 uint32_t dirsteer:1;
1283 uint32_t iq:10;
1284
1285 uint32_t maskhash:1;
1286 uint32_t dirsteerhash:1;
1287
1288
1289
1290
1291
1292
1293 uint32_t eport:2;
1294 uint32_t newdmac:1;
1295 uint32_t newsmac:1;
1296 uint32_t newvlan:2;
1297 uint32_t nat_mode:3;
1298 uint8_t dmac[ETH_ALEN];
1299 uint8_t smac[ETH_ALEN];
1300 uint16_t vlan;
1301
1302 u8 nat_lip[16];
1303 u8 nat_fip[16];
1304 u16 nat_lport;
1305 u16 nat_fport;
1306
1307 u32 tc_prio;
1308 u64 tc_cookie;
1309
1310
1311 u8 rsvd[12];
1312
1313
1314
1315 struct ch_filter_tuple val;
1316 struct ch_filter_tuple mask;
1317};
1318
1319enum {
1320 FILTER_PASS = 0,
1321 FILTER_DROP,
1322 FILTER_SWITCH
1323};
1324
1325enum {
1326 VLAN_NOCHANGE = 0,
1327 VLAN_REMOVE,
1328 VLAN_INSERT,
1329 VLAN_REWRITE
1330};
1331
1332enum {
1333 NAT_MODE_NONE = 0,
1334 NAT_MODE_DIP,
1335 NAT_MODE_DIP_DP,
1336 NAT_MODE_DIP_DP_SIP,
1337 NAT_MODE_DIP_DP_SP,
1338 NAT_MODE_SIP_SP,
1339 NAT_MODE_DIP_SIP_SP,
1340 NAT_MODE_ALL
1341};
1342
1343
1344
1345
1346
1347
1348
1349struct filter_entry {
1350
1351 u32 valid:1;
1352 u32 locked:1;
1353
1354 u32 pending:1;
1355 struct filter_ctx *ctx;
1356 struct l2t_entry *l2t;
1357 struct smt_entry *smt;
1358 struct net_device *dev;
1359 u32 tid;
1360
1361
1362
1363
1364
1365
1366 struct ch_filter_specification fs;
1367};
1368
1369static inline int is_offload(const struct adapter *adap)
1370{
1371 return adap->params.offload;
1372}
1373
1374static inline int is_hashfilter(const struct adapter *adap)
1375{
1376 return adap->params.hash_filter;
1377}
1378
1379static inline int is_pci_uld(const struct adapter *adap)
1380{
1381 return adap->params.crypto;
1382}
1383
1384static inline int is_uld(const struct adapter *adap)
1385{
1386 return (adap->params.offload || adap->params.crypto);
1387}
1388
1389static inline int is_ethofld(const struct adapter *adap)
1390{
1391 return adap->params.ethofld;
1392}
1393
1394static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1395{
1396 return readl(adap->regs + reg_addr);
1397}
1398
1399static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1400{
1401 writel(val, adap->regs + reg_addr);
1402}
1403
1404#ifndef readq
1405static inline u64 readq(const volatile void __iomem *addr)
1406{
1407 return readl(addr) + ((u64)readl(addr + 4) << 32);
1408}
1409
1410static inline void writeq(u64 val, volatile void __iomem *addr)
1411{
1412 writel(val, addr);
1413 writel(val >> 32, addr + 4);
1414}
1415#endif
1416
1417static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1418{
1419 return readq(adap->regs + reg_addr);
1420}
1421
1422static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1423{
1424 writeq(val, adap->regs + reg_addr);
1425}
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1437 u8 hw_addr[])
1438{
1439 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1440 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1441}
1442
1443
1444
1445
1446
1447
1448
1449static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1450{
1451 return netdev_priv(dev);
1452}
1453
1454
1455
1456
1457
1458
1459
1460
1461static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1462{
1463 return netdev_priv(adap->port[idx]);
1464}
1465
1466
1467
1468
1469
1470
1471
1472static inline struct adapter *netdev2adap(const struct net_device *dev)
1473{
1474 return netdev2pinfo(dev)->adapter;
1475}
1476
1477
1478
1479
1480
1481
1482static inline unsigned int mk_adap_vers(struct adapter *ap)
1483{
1484 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1485 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1486}
1487
1488
1489static inline unsigned int qtimer_val(const struct adapter *adap,
1490 const struct sge_rspq *q)
1491{
1492 unsigned int idx = q->intr_params >> 1;
1493
1494 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1495}
1496
1497
1498extern char cxgb4_driver_name[];
1499
1500void t4_os_portmod_changed(struct adapter *adap, int port_id);
1501void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1502
1503void t4_free_sge_resources(struct adapter *adap);
1504void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1505irq_handler_t t4_intr_handler(struct adapter *adap);
1506netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1507int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1508 const struct pkt_gl *gl);
1509int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1510int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1511int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1512 struct net_device *dev, int intr_idx,
1513 struct sge_fl *fl, rspq_handler_t hnd,
1514 rspq_flush_handler_t flush_handler, int cong);
1515int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1516 struct net_device *dev, struct netdev_queue *netdevq,
1517 unsigned int iqid, u8 dbqt);
1518int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1519 struct net_device *dev, unsigned int iqid,
1520 unsigned int cmplqid);
1521int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1522 unsigned int cmplqid);
1523int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1524 struct net_device *dev, unsigned int iqid,
1525 unsigned int uld_type);
1526int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
1527 struct net_device *dev, u32 iqid);
1528void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq);
1529irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1530int t4_sge_init(struct adapter *adap);
1531void t4_sge_start(struct adapter *adap);
1532void t4_sge_stop(struct adapter *adap);
1533int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1534 int maxreclaim);
1535void cxgb4_set_ethtool_ops(struct net_device *netdev);
1536int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1537enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1538extern int dbfifo_int_thresh;
1539
1540#define for_each_port(adapter, iter) \
1541 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1542
1543static inline int is_bypass(struct adapter *adap)
1544{
1545 return adap->params.bypass;
1546}
1547
1548static inline int is_bypass_device(int device)
1549{
1550
1551 switch (device) {
1552 case 0x440b:
1553 case 0x440c:
1554 return 1;
1555 default:
1556 return 0;
1557 }
1558}
1559
1560static inline int is_10gbt_device(int device)
1561{
1562
1563 switch (device) {
1564 case 0x4409:
1565 case 0x4486:
1566 return 1;
1567
1568 default:
1569 return 0;
1570 }
1571}
1572
1573static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1574{
1575 return adap->params.vpd.cclk / 1000;
1576}
1577
1578static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1579 unsigned int us)
1580{
1581 return (us * adap->params.vpd.cclk) / 1000;
1582}
1583
1584static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1585 unsigned int ticks)
1586{
1587
1588 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1589 adapter->params.vpd.cclk);
1590}
1591
1592static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1593 unsigned int ticks)
1594{
1595 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1596}
1597
1598void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1599 u32 val);
1600
1601int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1602 int size, void *rpl, bool sleep_ok, int timeout);
1603int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1604 void *rpl, bool sleep_ok);
1605
1606static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1607 const void *cmd, int size, void *rpl,
1608 int timeout)
1609{
1610 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1611 timeout);
1612}
1613
1614static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1615 int size, void *rpl)
1616{
1617 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1618}
1619
1620static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1621 int size, void *rpl)
1622{
1623 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1624}
1625
1626
1627
1628
1629
1630
1631
1632
1633static inline int hash_mac_addr(const u8 *addr)
1634{
1635 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1636 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1637
1638 a ^= b;
1639 a ^= (a >> 12);
1640 a ^= (a >> 6);
1641 return a & 0x3f;
1642}
1643
1644int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1645 unsigned int cnt);
1646static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1647 unsigned int us, unsigned int cnt,
1648 unsigned int size, unsigned int iqe_size)
1649{
1650 q->adap = adap;
1651 cxgb4_set_rspq_intr_params(q, us, cnt);
1652 q->iqe_len = iqe_size;
1653 q->size = size;
1654}
1655
1656
1657
1658
1659
1660
1661
1662
1663static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1664{
1665 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1666 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1667 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1668 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1669}
1670
1671void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1672 unsigned int data_reg, const u32 *vals,
1673 unsigned int nregs, unsigned int start_idx);
1674void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1675 unsigned int data_reg, u32 *vals, unsigned int nregs,
1676 unsigned int start_idx);
1677void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1678
1679struct fw_filter_wr;
1680
1681void t4_intr_enable(struct adapter *adapter);
1682void t4_intr_disable(struct adapter *adapter);
1683int t4_slow_intr_handler(struct adapter *adapter);
1684
1685int t4_wait_dev_ready(void __iomem *regs);
1686
1687fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1688 struct link_config *lc);
1689int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1690 unsigned int port, struct link_config *lc,
1691 u8 sleep_ok, int timeout);
1692
1693static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1694 unsigned int port, struct link_config *lc)
1695{
1696 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1697 true, FW_CMD_MAX_TIMEOUT);
1698}
1699
1700static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1701 unsigned int port, struct link_config *lc)
1702{
1703 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1704 false, FW_CMD_MAX_TIMEOUT);
1705}
1706
1707int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1708
1709u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1710u32 t4_get_util_window(struct adapter *adap);
1711void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1712
1713int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1714 u32 *mem_base, u32 *mem_aperture);
1715void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1716void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1717 int dir);
1718#define T4_MEMORY_WRITE 0
1719#define T4_MEMORY_READ 1
1720int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1721 void *buf, int dir);
1722static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1723 u32 len, __be32 *buf)
1724{
1725 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1726}
1727
1728unsigned int t4_get_regs_len(struct adapter *adapter);
1729void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1730
1731int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1732int t4_seeprom_wp(struct adapter *adapter, bool enable);
1733int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1734int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1735int t4_get_pfres(struct adapter *adapter);
1736int t4_read_flash(struct adapter *adapter, unsigned int addr,
1737 unsigned int nwords, u32 *data, int byte_oriented);
1738int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1739int t4_load_phy_fw(struct adapter *adap,
1740 int win, spinlock_t *lock,
1741 int (*phy_fw_version)(const u8 *, size_t),
1742 const u8 *phy_fw_data, size_t phy_fw_size);
1743int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1744int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1745int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1746 const u8 *fw_data, unsigned int size, int force);
1747int t4_fl_pkt_align(struct adapter *adap);
1748unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1749int t4_check_fw_version(struct adapter *adap);
1750int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1751int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1752int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1753int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1754int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1755int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1756int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1757int t4_get_version_info(struct adapter *adapter);
1758void t4_dump_version_info(struct adapter *adapter);
1759int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1760 const u8 *fw_data, unsigned int fw_size,
1761 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1762int t4_prep_adapter(struct adapter *adapter);
1763int t4_shutdown_adapter(struct adapter *adapter);
1764
1765enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1766int t4_bar2_sge_qregs(struct adapter *adapter,
1767 unsigned int qid,
1768 enum t4_bar2_qtype qtype,
1769 int user,
1770 u64 *pbar2_qoffset,
1771 unsigned int *pbar2_qid);
1772
1773unsigned int qtimer_val(const struct adapter *adap,
1774 const struct sge_rspq *q);
1775
1776int t4_init_devlog_params(struct adapter *adapter);
1777int t4_init_sge_params(struct adapter *adapter);
1778int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1779int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1780int t4_init_rss_mode(struct adapter *adap, int mbox);
1781int t4_init_portinfo(struct port_info *pi, int mbox,
1782 int port, int pf, int vf, u8 mac[]);
1783int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1784void t4_fatal_err(struct adapter *adapter);
1785unsigned int t4_chip_rss_size(struct adapter *adapter);
1786int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1787 int start, int n, const u16 *rspq, unsigned int nrspq);
1788int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1789 unsigned int flags);
1790int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1791 unsigned int flags, unsigned int defq);
1792int t4_read_rss(struct adapter *adapter, u16 *entries);
1793void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1794void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1795 bool sleep_ok);
1796void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1797 u32 *valp, bool sleep_ok);
1798void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1799 u32 *vfl, u32 *vfh, bool sleep_ok);
1800u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1801u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1802
1803unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1804unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1805void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1806void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1807int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1808 size_t n);
1809int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1810 size_t n);
1811int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1812 unsigned int *valp);
1813int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1814 const unsigned int *valp);
1815int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1816void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1817 unsigned int *pif_req_wrptr,
1818 unsigned int *pif_rsp_wrptr);
1819void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1820void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1821const char *t4_get_port_type_description(enum fw_port_type port_type);
1822void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1823void t4_get_port_stats_offset(struct adapter *adap, int idx,
1824 struct port_stats *stats,
1825 struct port_stats *offset);
1826void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1827void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1828void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1829void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1830 unsigned int mask, unsigned int val);
1831void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1832void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1833 bool sleep_ok);
1834void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1835 bool sleep_ok);
1836void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1837 bool sleep_ok);
1838void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1839 bool sleep_ok);
1840void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1841 struct tp_tcp_stats *v6, bool sleep_ok);
1842void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1843 struct tp_fcoe_stats *st, bool sleep_ok);
1844void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1845 const unsigned short *alpha, const unsigned short *beta);
1846
1847void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1848
1849void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1850void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1851
1852void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1853 const u8 *addr);
1854int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1855 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1856
1857int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1858 enum dev_master master, enum dev_state *state);
1859int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1860int t4_early_init(struct adapter *adap, unsigned int mbox);
1861int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1862int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1863 unsigned int cache_line_size);
1864int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1865int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1866 unsigned int vf, unsigned int nparams, const u32 *params,
1867 u32 *val);
1868int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1869 unsigned int vf, unsigned int nparams, const u32 *params,
1870 u32 *val);
1871int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1872 unsigned int vf, unsigned int nparams, const u32 *params,
1873 u32 *val, int rw, bool sleep_ok);
1874int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1875 unsigned int pf, unsigned int vf,
1876 unsigned int nparams, const u32 *params,
1877 const u32 *val, int timeout);
1878int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1879 unsigned int vf, unsigned int nparams, const u32 *params,
1880 const u32 *val);
1881int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1882 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1883 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1884 unsigned int vi, unsigned int cmask, unsigned int pmask,
1885 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1886int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1887 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1888 unsigned int *rss_size, u8 *vivld, u8 *vin);
1889int t4_free_vi(struct adapter *adap, unsigned int mbox,
1890 unsigned int pf, unsigned int vf,
1891 unsigned int viid);
1892int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1893 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1894 bool sleep_ok);
1895int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1896 const u8 *addr, const u8 *mask, unsigned int idx,
1897 u8 lookup_type, u8 port_id, bool sleep_ok);
1898int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1899 bool sleep_ok);
1900int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1901 const u8 *addr, const u8 *mask, unsigned int vni,
1902 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1903 bool sleep_ok);
1904int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1905 const u8 *addr, const u8 *mask, unsigned int idx,
1906 u8 lookup_type, u8 port_id, bool sleep_ok);
1907int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1908 unsigned int viid, bool free, unsigned int naddr,
1909 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1910int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1911 unsigned int viid, unsigned int naddr,
1912 const u8 **addr, bool sleep_ok);
1913int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1914 int idx, const u8 *addr, bool persist, u8 *smt_idx);
1915int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1916 bool ucast, u64 vec, bool sleep_ok);
1917int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1918 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1919int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1920 struct port_info *pi,
1921 bool rx_en, bool tx_en, bool dcb_en);
1922int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1923 bool rx_en, bool tx_en);
1924int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1925 unsigned int nblinks);
1926int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1927 unsigned int mmd, unsigned int reg, u16 *valp);
1928int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1929 unsigned int mmd, unsigned int reg, u16 val);
1930int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1931 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1932 unsigned int fl0id, unsigned int fl1id);
1933int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1934 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1935 unsigned int fl0id, unsigned int fl1id);
1936int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1937 unsigned int vf, unsigned int eqid);
1938int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1939 unsigned int vf, unsigned int eqid);
1940int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1941 unsigned int vf, unsigned int eqid);
1942int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1943int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
1944 u16 *dbqtimers);
1945void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1946int t4_update_port_info(struct port_info *pi);
1947int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1948 unsigned int *speedp, unsigned int *mtup);
1949int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1950void t4_db_full(struct adapter *adapter);
1951void t4_db_dropped(struct adapter *adapter);
1952int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1953 int filter_index, int enable);
1954void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1955 int filter_index, int *enabled);
1956int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1957 u32 addr, u32 val);
1958void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1959void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1960 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1961int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1962 enum ctxt_type ctype, u32 *data);
1963int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1964 enum ctxt_type ctype, u32 *data);
1965int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
1966 u8 rateunit, u8 ratemode, u8 channel, u8 class,
1967 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
1968 u16 burstsize);
1969void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1970void t4_idma_monitor_init(struct adapter *adapter,
1971 struct sge_idma_monitor_state *idma);
1972void t4_idma_monitor(struct adapter *adapter,
1973 struct sge_idma_monitor_state *idma,
1974 int hz, int ticks);
1975int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1976 unsigned int naddr, u8 *addr);
1977void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1978 u32 start_index, bool sleep_ok);
1979void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1980 u32 start_index, bool sleep_ok);
1981void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1982 u32 start_index, bool sleep_ok);
1983
1984void t4_uld_mem_free(struct adapter *adap);
1985int t4_uld_mem_alloc(struct adapter *adap);
1986void t4_uld_clean_up(struct adapter *adap);
1987void t4_register_netevent_notifier(void);
1988int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1989 unsigned int devid, unsigned int offset,
1990 unsigned int len, u8 *buf);
1991void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1992void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1993 unsigned int n, bool unmap);
1994void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq,
1995 u32 ndesc);
1996int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc);
1997void cxgb4_ethofld_restart(unsigned long data);
1998int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp,
1999 const struct pkt_gl *si);
2000void free_txq(struct adapter *adap, struct sge_txq *q);
2001void cxgb4_reclaim_completed_tx(struct adapter *adap,
2002 struct sge_txq *q, bool unmap);
2003int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
2004 dma_addr_t *addr);
2005void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
2006 void *pos);
2007void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
2008 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
2009 const dma_addr_t *addr);
2010void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
2011int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
2012 u16 vlan);
2013int cxgb4_dcb_enabled(const struct net_device *dev);
2014
2015int cxgb4_thermal_init(struct adapter *adap);
2016int cxgb4_thermal_remove(struct adapter *adap);
2017int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
2018 cpumask_var_t *aff_mask, int idx);
2019void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
2020
2021int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
2022 int *tcam_idx, const u8 *addr,
2023 bool persistent, u8 *smt_idx);
2024
2025int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
2026 bool free, unsigned int naddr,
2027 const u8 **addr, u16 *idx,
2028 u64 *hash, bool sleep_ok);
2029int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
2030 unsigned int naddr, const u8 **addr, bool sleep_ok);
2031int cxgb4_init_mps_ref_entries(struct adapter *adap);
2032void cxgb4_free_mps_ref_entries(struct adapter *adap);
2033int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
2034 const u8 *addr, const u8 *mask,
2035 unsigned int vni, unsigned int vni_mask,
2036 u8 dip_hit, u8 lookup_type, bool sleep_ok);
2037int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
2038 int idx, bool sleep_ok);
2039int cxgb4_free_raw_mac_filt(struct adapter *adap,
2040 unsigned int viid,
2041 const u8 *addr,
2042 const u8 *mask,
2043 unsigned int idx,
2044 u8 lookup_type,
2045 u8 port_id,
2046 bool sleep_ok);
2047int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
2048 unsigned int viid,
2049 const u8 *addr,
2050 const u8 *mask,
2051 unsigned int idx,
2052 u8 lookup_type,
2053 u8 port_id,
2054 bool sleep_ok);
2055int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
2056 int *tcam_idx, const u8 *addr,
2057 bool persistent, u8 *smt_idx);
2058int cxgb4_get_msix_idx_from_bmap(struct adapter *adap);
2059void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx);
2060int cxgb_open(struct net_device *dev);
2061int cxgb_close(struct net_device *dev);
2062void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q);
2063void cxgb4_quiesce_rx(struct sge_rspq *q);
2064#ifdef CONFIG_CHELSIO_TLS_DEVICE
2065int cxgb4_set_ktls_feature(struct adapter *adap, bool enable);
2066#endif
2067#endif
2068