1
2
3
4#ifndef _ICE_TYPE_H_
5#define _ICE_TYPE_H_
6
7#define ICE_BYTES_PER_WORD 2
8#define ICE_BYTES_PER_DWORD 4
9
10#include "ice_status.h"
11#include "ice_hw_autogen.h"
12#include "ice_osdep.h"
13#include "ice_controlq.h"
14#include "ice_lan_tx_rx.h"
15#include "ice_flex_type.h"
16#include "ice_protocol_type.h"
17
18static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
19{
20 return test_bit(tc, &bitmap);
21}
22
23static inline u64 round_up_64bit(u64 a, u32 b)
24{
25 return div64_long(((a) + (b) / 2), (b));
26}
27
28static inline u32 ice_round_to_num(u32 N, u32 R)
29{
30 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
31 ((((N) + (R) - 1) / (R)) * (R)));
32}
33
34
35#define ICE_MAIN_VSI_HANDLE 0
36
37
38#define ICE_DBG_INIT BIT_ULL(1)
39#define ICE_DBG_FW_LOG BIT_ULL(3)
40#define ICE_DBG_LINK BIT_ULL(4)
41#define ICE_DBG_PHY BIT_ULL(5)
42#define ICE_DBG_QCTX BIT_ULL(6)
43#define ICE_DBG_NVM BIT_ULL(7)
44#define ICE_DBG_LAN BIT_ULL(8)
45#define ICE_DBG_FLOW BIT_ULL(9)
46#define ICE_DBG_SW BIT_ULL(13)
47#define ICE_DBG_SCHED BIT_ULL(14)
48#define ICE_DBG_PKG BIT_ULL(16)
49#define ICE_DBG_RES BIT_ULL(17)
50#define ICE_DBG_AQ_MSG BIT_ULL(24)
51#define ICE_DBG_AQ_DESC BIT_ULL(25)
52#define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
53#define ICE_DBG_AQ_CMD BIT_ULL(27)
54#define ICE_DBG_USER BIT_ULL(31)
55
56enum ice_aq_res_ids {
57 ICE_NVM_RES_ID = 1,
58 ICE_SPD_RES_ID,
59 ICE_CHANGE_LOCK_RES_ID,
60 ICE_GLOBAL_CFG_LOCK_RES_ID
61};
62
63
64#define ICE_NVM_TIMEOUT 180000
65#define ICE_CHANGE_LOCK_TIMEOUT 1000
66#define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
67
68enum ice_aq_res_access_type {
69 ICE_RES_READ = 1,
70 ICE_RES_WRITE
71};
72
73struct ice_driver_ver {
74 u8 major_ver;
75 u8 minor_ver;
76 u8 build_ver;
77 u8 subbuild_ver;
78 u8 driver_string[32];
79};
80
81enum ice_fc_mode {
82 ICE_FC_NONE = 0,
83 ICE_FC_RX_PAUSE,
84 ICE_FC_TX_PAUSE,
85 ICE_FC_FULL,
86 ICE_FC_PFC,
87 ICE_FC_DFLT
88};
89
90enum ice_fec_mode {
91 ICE_FEC_NONE = 0,
92 ICE_FEC_RS,
93 ICE_FEC_BASER,
94 ICE_FEC_AUTO
95};
96
97enum ice_set_fc_aq_failures {
98 ICE_SET_FC_AQ_FAIL_NONE = 0,
99 ICE_SET_FC_AQ_FAIL_GET,
100 ICE_SET_FC_AQ_FAIL_SET,
101 ICE_SET_FC_AQ_FAIL_UPDATE
102};
103
104
105enum ice_mac_type {
106 ICE_MAC_UNKNOWN = 0,
107 ICE_MAC_GENERIC,
108};
109
110
111enum ice_media_type {
112 ICE_MEDIA_UNKNOWN = 0,
113 ICE_MEDIA_FIBER,
114 ICE_MEDIA_BASET,
115 ICE_MEDIA_BACKPLANE,
116 ICE_MEDIA_DA,
117};
118
119enum ice_vsi_type {
120 ICE_VSI_PF = 0,
121 ICE_VSI_VF = 1,
122 ICE_VSI_CTRL = 3,
123 ICE_VSI_LB = 6,
124};
125
126struct ice_link_status {
127
128 u64 phy_type_low;
129 u64 phy_type_high;
130 u8 topo_media_conflict;
131 u16 max_frame_size;
132 u16 link_speed;
133 u16 req_speeds;
134 u8 lse_ena;
135 u8 link_info;
136 u8 an_info;
137 u8 ext_info;
138 u8 fec_info;
139 u8 pacing;
140
141
142
143 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
144};
145
146
147
148
149enum ice_disq_rst_src {
150 ICE_NO_RESET = 0,
151 ICE_VM_RESET,
152 ICE_VF_RESET,
153};
154
155
156struct ice_phy_info {
157 struct ice_link_status link_info;
158 struct ice_link_status link_info_old;
159 u64 phy_type_low;
160 u64 phy_type_high;
161 enum ice_media_type media_type;
162 u8 get_link_info;
163};
164
165
166enum ice_fltr_ptype {
167
168 ICE_FLTR_PTYPE_NONF_NONE = 0,
169 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
170 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
171 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
172 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
173 ICE_FLTR_PTYPE_FRAG_IPV4,
174 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
175 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
176 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
177 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
178 ICE_FLTR_PTYPE_MAX,
179};
180
181enum ice_fd_hw_seg {
182 ICE_FD_HW_SEG_NON_TUN = 0,
183 ICE_FD_HW_SEG_TUN,
184 ICE_FD_HW_SEG_MAX,
185};
186
187
188#define ICE_MAX_FDIR_VSI_PER_FILTER 2
189
190struct ice_fd_hw_prof {
191 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
192 int cnt;
193 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
194 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
195};
196
197
198struct ice_hw_common_caps {
199 u32 valid_functions;
200
201 u32 active_tc_bitmap;
202 u32 maxtc;
203
204
205 u16 num_rxq;
206 u16 rxq_first_id;
207 u16 num_txq;
208 u16 txq_first_id;
209
210
211 u16 num_msix_vectors;
212 u16 msix_vector_first_id;
213
214
215 u16 max_mtu;
216
217
218 u8 sr_iov_1_1;
219
220
221 u16 rss_table_size;
222 u8 rss_table_entry_width;
223
224 u8 dcb;
225};
226
227
228struct ice_hw_func_caps {
229 struct ice_hw_common_caps common_cap;
230 u32 num_allocd_vfs;
231 u32 vf_base_id;
232 u32 guar_num_vsi;
233 u32 fd_fltr_guar;
234 u32 fd_fltr_best_effort;
235};
236
237
238struct ice_hw_dev_caps {
239 struct ice_hw_common_caps common_cap;
240 u32 num_vfs_exposed;
241 u32 num_vsi_allocd_to_host;
242 u32 num_flow_director_fltr;
243 u32 num_funcs;
244};
245
246
247struct ice_mac_info {
248 u8 lan_addr[ETH_ALEN];
249 u8 perm_addr[ETH_ALEN];
250};
251
252
253
254
255
256
257enum ice_reset_req {
258 ICE_RESET_POR = 0,
259 ICE_RESET_INVAL = 0,
260 ICE_RESET_CORER = 1,
261 ICE_RESET_GLOBR = 2,
262 ICE_RESET_EMPR = 3,
263 ICE_RESET_PFR = 4,
264};
265
266
267struct ice_bus_info {
268 u16 device;
269 u8 func;
270};
271
272
273struct ice_fc_info {
274 enum ice_fc_mode current_mode;
275 enum ice_fc_mode req_mode;
276};
277
278
279struct ice_orom_info {
280 u8 major;
281 u8 patch;
282 u16 build;
283};
284
285
286struct ice_nvm_info {
287 struct ice_orom_info orom;
288 u32 eetrack;
289 u16 sr_words;
290 u32 flash_size;
291 u8 major_ver;
292 u8 minor_ver;
293 u8 blank_nvm_mode;
294};
295
296#define ICE_NVM_VER_LEN 32
297
298
299struct ice_netlist_ver_info {
300 u32 major;
301 u32 minor;
302 u32 type;
303 u32 rev;
304 u32 hash;
305 u16 cust_ver;
306};
307
308
309#define ICE_MAX_TRAFFIC_CLASS 8
310#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
311
312#define ice_for_each_traffic_class(_i) \
313 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
314
315#define ICE_INVAL_TEID 0xFFFFFFFF
316
317struct ice_sched_node {
318 struct ice_sched_node *parent;
319 struct ice_sched_node *sibling;
320 struct ice_sched_node **children;
321 struct ice_aqc_txsched_elem_data info;
322 u32 agg_id;
323 u16 vsi_handle;
324 u8 in_use;
325 u8 tx_sched_layer;
326 u8 num_children;
327 u8 tc_num;
328 u8 owner;
329#define ICE_SCHED_NODE_OWNER_LAN 0
330};
331
332
333#define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
334
335
336
337
338enum ice_agg_type {
339 ICE_AGG_TYPE_UNKNOWN = 0,
340 ICE_AGG_TYPE_VSI,
341 ICE_AGG_TYPE_AGG,
342 ICE_AGG_TYPE_Q,
343 ICE_AGG_TYPE_QG
344};
345
346
347enum ice_rl_type {
348 ICE_UNKNOWN_BW = 0,
349 ICE_MIN_BW,
350 ICE_MAX_BW,
351 ICE_SHARED_BW
352};
353
354#define ICE_SCHED_MIN_BW 500
355#define ICE_SCHED_MAX_BW 100000000
356#define ICE_SCHED_DFLT_BW 0xFFFFFFFF
357#define ICE_SCHED_DFLT_RL_PROF_ID 0
358#define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
359#define ICE_SCHED_DFLT_BW_WT 1
360#define ICE_SCHED_INVAL_PROF_ID 0xFFFF
361#define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024)
362
363
364enum ice_bw_type {
365 ICE_BW_TYPE_PRIO,
366 ICE_BW_TYPE_CIR,
367 ICE_BW_TYPE_CIR_WT,
368 ICE_BW_TYPE_EIR,
369 ICE_BW_TYPE_EIR_WT,
370 ICE_BW_TYPE_SHARED,
371 ICE_BW_TYPE_CNT
372};
373
374struct ice_bw {
375 u32 bw;
376 u16 bw_alloc;
377};
378
379struct ice_bw_type_info {
380 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
381 u8 generic;
382 struct ice_bw cir_bw;
383 struct ice_bw eir_bw;
384 u32 shared_bw;
385};
386
387
388struct ice_q_ctx {
389 u16 q_handle;
390 u32 q_teid;
391
392 struct ice_bw_type_info bw_t_info;
393};
394
395
396struct ice_sched_vsi_info {
397 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
398 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
399 struct list_head list_entry;
400 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
401};
402
403
404struct ice_sched_tx_policy {
405 u16 max_num_vsis;
406 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
407 u8 rdma_ena;
408};
409
410
411struct ice_dcb_ets_cfg {
412 u8 willing;
413 u8 cbs;
414 u8 maxtcs;
415 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
416 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
417 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
418};
419
420
421struct ice_dcb_pfc_cfg {
422 u8 willing;
423 u8 mbc;
424 u8 pfccap;
425 u8 pfcena;
426};
427
428
429struct ice_dcb_app_priority_table {
430 u16 prot_id;
431 u8 priority;
432 u8 selector;
433};
434
435#define ICE_MAX_USER_PRIORITY 8
436#define ICE_DCBX_MAX_APPS 32
437#define ICE_LLDPDU_SIZE 1500
438#define ICE_TLV_STATUS_OPER 0x1
439#define ICE_TLV_STATUS_SYNC 0x2
440#define ICE_TLV_STATUS_ERR 0x4
441#define ICE_APP_PROT_ID_FCOE 0x8906
442#define ICE_APP_PROT_ID_ISCSI 0x0cbc
443#define ICE_APP_PROT_ID_FIP 0x8914
444#define ICE_APP_SEL_ETHTYPE 0x1
445#define ICE_APP_SEL_TCPIP 0x2
446#define ICE_CEE_APP_SEL_ETHTYPE 0x0
447#define ICE_CEE_APP_SEL_TCPIP 0x1
448
449struct ice_dcbx_cfg {
450 u32 numapps;
451 u32 tlv_status;
452 struct ice_dcb_ets_cfg etscfg;
453 struct ice_dcb_ets_cfg etsrec;
454 struct ice_dcb_pfc_cfg pfc;
455 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
456 u8 dcbx_mode;
457#define ICE_DCBX_MODE_CEE 0x1
458#define ICE_DCBX_MODE_IEEE 0x2
459 u8 app_mode;
460#define ICE_DCBX_APPS_NON_WILLING 0x1
461};
462
463struct ice_port_info {
464 struct ice_sched_node *root;
465 struct ice_hw *hw;
466 u32 last_node_teid;
467 u16 sw_id;
468 u16 pf_vf_num;
469 u8 port_state;
470#define ICE_SCHED_PORT_STATE_INIT 0x0
471#define ICE_SCHED_PORT_STATE_READY 0x1
472 u8 lport;
473#define ICE_LPORT_MASK 0xff
474 u16 dflt_tx_vsi_rule_id;
475 u16 dflt_tx_vsi_num;
476 u16 dflt_rx_vsi_rule_id;
477 u16 dflt_rx_vsi_num;
478 struct ice_fc_info fc;
479 struct ice_mac_info mac;
480 struct ice_phy_info phy;
481 struct mutex sched_lock;
482 struct ice_sched_node *
483 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
484
485 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
486 struct ice_dcbx_cfg local_dcbx_cfg;
487
488 struct ice_dcbx_cfg remote_dcbx_cfg;
489 struct ice_dcbx_cfg desired_dcbx_cfg;
490
491 u8 dcbx_status:3;
492 u8 is_sw_lldp:1;
493 u8 is_vf:1;
494};
495
496struct ice_switch_info {
497 struct list_head vsi_list_map_head;
498 struct ice_sw_recipe *recp_list;
499};
500
501
502struct ice_fw_log_evnt {
503 u8 cfg : 4;
504 u8 cur : 4;
505};
506
507struct ice_fw_log_cfg {
508 u8 cq_en : 1;
509 u8 uart_en : 1;
510 u8 actv_evnts;
511
512#define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
513#define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
514#define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
515#define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
516 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
517};
518
519
520struct ice_hw {
521 u8 __iomem *hw_addr;
522 void *back;
523 struct ice_aqc_layer_props *layer_info;
524 struct ice_port_info *port_info;
525 u64 debug_mask;
526 enum ice_mac_type mac_type;
527
528 u16 fd_ctr_base;
529
530
531 u16 device_id;
532 u16 vendor_id;
533 u16 subsystem_device_id;
534 u16 subsystem_vendor_id;
535 u8 revision_id;
536
537 u8 pf_id;
538
539 u16 max_burst_size;
540
541
542 u8 num_tx_sched_layers;
543 u8 num_tx_sched_phys_layers;
544 u8 flattened_layers;
545 u8 max_cgds;
546 u8 sw_entry_point_layer;
547 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
548 struct list_head agg_list;
549
550 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
551 u8 evb_veb;
552 u8 reset_ongoing;
553 struct ice_bus_info bus;
554 struct ice_nvm_info nvm;
555 struct ice_hw_dev_caps dev_caps;
556 struct ice_hw_func_caps func_caps;
557 struct ice_netlist_ver_info netlist_ver;
558
559 struct ice_switch_info *switch_info;
560
561
562 struct ice_ctl_q_info adminq;
563 struct ice_ctl_q_info mailboxq;
564
565 u8 api_branch;
566 u8 api_maj_ver;
567 u8 api_min_ver;
568 u8 api_patch;
569 u8 fw_branch;
570 u8 fw_maj_ver;
571 u8 fw_min_ver;
572 u8 fw_patch;
573 u32 fw_build;
574
575 struct ice_fw_log_cfg fw_log;
576
577
578
579
580
581#define ICE_MAX_AGG_BW_200G 0x0
582#define ICE_MAX_AGG_BW_100G 0X1
583#define ICE_MAX_AGG_BW_50G 0x2
584#define ICE_MAX_AGG_BW_25G 0x3
585
586#define ICE_ITR_GRAN_ABOVE_25 2
587#define ICE_ITR_GRAN_MAX_25 4
588
589 u8 itr_gran;
590
591#define ICE_INTRL_GRAN_ABOVE_25 4
592#define ICE_INTRL_GRAN_MAX_25 8
593
594 u8 intrl_gran;
595
596 u8 ucast_shared;
597
598
599 struct ice_pkg_ver active_pkg_ver;
600 u32 active_track_id;
601 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
602 u8 active_pkg_in_nvm;
603
604 enum ice_aq_err pkg_dwnld_status;
605
606
607 struct ice_pkg_ver pkg_ver;
608 u8 pkg_name[ICE_PKG_NAME_SIZE];
609
610
611 struct ice_pkg_ver ice_pkg_ver;
612 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
613
614
615 struct ice_seg *seg;
616
617
618 u8 *pkg_copy;
619 u32 pkg_size;
620
621
622 struct mutex tnl_lock;
623 struct ice_tunnel_table tnl;
624
625
626 struct ice_blk_info blk[ICE_BLK_COUNT];
627 struct mutex fl_profs_locks[ICE_BLK_COUNT];
628 struct list_head fl_profs[ICE_BLK_COUNT];
629
630
631 int fdir_active_fltr;
632
633 struct mutex fdir_fltr_lock;
634 struct list_head fdir_list_head;
635
636
637
638
639
640 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
641
642 struct ice_fd_hw_prof **fdir_prof;
643 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
644 struct mutex rss_locks;
645 struct list_head rss_list_head;
646};
647
648
649struct ice_eth_stats {
650 u64 rx_bytes;
651 u64 rx_unicast;
652 u64 rx_multicast;
653 u64 rx_broadcast;
654 u64 rx_discards;
655 u64 rx_unknown_protocol;
656 u64 tx_bytes;
657 u64 tx_unicast;
658 u64 tx_multicast;
659 u64 tx_broadcast;
660 u64 tx_discards;
661 u64 tx_errors;
662};
663
664#define ICE_MAX_UP 8
665
666
667struct ice_hw_port_stats {
668
669 struct ice_eth_stats eth;
670
671 u64 tx_dropped_link_down;
672 u64 crc_errors;
673 u64 illegal_bytes;
674 u64 error_bytes;
675 u64 mac_local_faults;
676 u64 mac_remote_faults;
677 u64 rx_len_errors;
678 u64 link_xon_rx;
679 u64 link_xoff_rx;
680 u64 link_xon_tx;
681 u64 link_xoff_tx;
682 u64 priority_xon_rx[8];
683 u64 priority_xoff_rx[8];
684 u64 priority_xon_tx[8];
685 u64 priority_xoff_tx[8];
686 u64 priority_xon_2_xoff[8];
687 u64 rx_size_64;
688 u64 rx_size_127;
689 u64 rx_size_255;
690 u64 rx_size_511;
691 u64 rx_size_1023;
692 u64 rx_size_1522;
693 u64 rx_size_big;
694 u64 rx_undersize;
695 u64 rx_fragments;
696 u64 rx_oversize;
697 u64 rx_jabber;
698 u64 tx_size_64;
699 u64 tx_size_127;
700 u64 tx_size_255;
701 u64 tx_size_511;
702 u64 tx_size_1023;
703 u64 tx_size_1522;
704 u64 tx_size_big;
705
706 u32 fd_sb_status;
707 u64 fd_sb_match;
708};
709
710
711#define ICE_SR_BOOT_CFG_PTR 0x132
712#define ICE_NVM_OROM_VER_OFF 0x02
713#define ICE_SR_PBA_BLOCK_PTR 0x16
714#define ICE_SR_NVM_DEV_STARTER_VER 0x18
715#define ICE_SR_NVM_EETRACK_LO 0x2D
716#define ICE_SR_NVM_EETRACK_HI 0x2E
717#define ICE_NVM_VER_LO_SHIFT 0
718#define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
719#define ICE_NVM_VER_HI_SHIFT 12
720#define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
721#define ICE_OROM_VER_PATCH_SHIFT 0
722#define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
723#define ICE_OROM_VER_BUILD_SHIFT 8
724#define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
725#define ICE_OROM_VER_SHIFT 24
726#define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
727#define ICE_SR_PFA_PTR 0x40
728#define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
729#define ICE_SR_WORDS_IN_1KB 512
730
731
732#define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
733
734#endif
735