linux/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/* Marvell OcteonTx2 RVU Admin Function driver
   3 *
   4 * Copyright (C) 2018 Marvell International Ltd.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#include <linux/bitfield.h>
  12#include <linux/module.h>
  13#include <linux/pci.h>
  14
  15#include "rvu_struct.h"
  16#include "rvu_reg.h"
  17#include "rvu.h"
  18#include "npc.h"
  19#include "cgx.h"
  20#include "npc_profile.h"
  21
  22#define RSVD_MCAM_ENTRIES_PER_PF        2 /* Bcast & Promisc */
  23#define RSVD_MCAM_ENTRIES_PER_NIXLF     1 /* Ucast for LFs */
  24
  25#define NIXLF_UCAST_ENTRY       0
  26#define NIXLF_BCAST_ENTRY       1
  27#define NIXLF_PROMISC_ENTRY     2
  28
  29#define NPC_PARSE_RESULT_DMAC_OFFSET    8
  30
  31static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
  32                                      int blkaddr, u16 pcifunc);
  33static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
  34                                       u16 pcifunc);
  35
  36void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
  37{
  38        int blkaddr;
  39        u64 val = 0;
  40
  41        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
  42        if (blkaddr < 0)
  43                return;
  44
  45        /* Config CPI base for the PKIND */
  46        val = pkind | 1ULL << 62;
  47        rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
  48}
  49
  50int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
  51{
  52        struct npc_pkind *pkind = &rvu->hw->pkind;
  53        u32 map;
  54        int i;
  55
  56        for (i = 0; i < pkind->rsrc.max; i++) {
  57                map = pkind->pfchan_map[i];
  58                if (((map >> 16) & 0x3F) == pf)
  59                        return i;
  60        }
  61        return -1;
  62}
  63
  64static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
  65                                    u16 pcifunc, int nixlf, int type)
  66{
  67        int pf = rvu_get_pf(pcifunc);
  68        int index;
  69
  70        /* Check if this is for a PF */
  71        if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
  72                /* Reserved entries exclude PF0 */
  73                pf--;
  74                index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
  75                /* Broadcast address matching entry should be first so
  76                 * that the packet can be replicated to all VFs.
  77                 */
  78                if (type == NIXLF_BCAST_ENTRY)
  79                        return index;
  80                else if (type == NIXLF_PROMISC_ENTRY)
  81                        return index + 1;
  82        }
  83
  84        return (mcam->nixlf_offset + (nixlf * RSVD_MCAM_ENTRIES_PER_NIXLF));
  85}
  86
  87static int npc_get_bank(struct npc_mcam *mcam, int index)
  88{
  89        int bank = index / mcam->banksize;
  90
  91        /* 0,1 & 2,3 banks are combined for this keysize */
  92        if (mcam->keysize == NPC_MCAM_KEY_X2)
  93                return bank ? 2 : 0;
  94
  95        return bank;
  96}
  97
  98static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
  99                                  int blkaddr, int index)
 100{
 101        int bank = npc_get_bank(mcam, index);
 102        u64 cfg;
 103
 104        index &= (mcam->banksize - 1);
 105        cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
 106        return (cfg & 1);
 107}
 108
 109static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 110                                  int blkaddr, int index, bool enable)
 111{
 112        int bank = npc_get_bank(mcam, index);
 113        int actbank = bank;
 114
 115        index &= (mcam->banksize - 1);
 116        for (; bank < (actbank + mcam->banks_per_entry); bank++) {
 117                rvu_write64(rvu, blkaddr,
 118                            NPC_AF_MCAMEX_BANKX_CFG(index, bank),
 119                            enable ? 1 : 0);
 120        }
 121}
 122
 123static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 124                                 int blkaddr, int index)
 125{
 126        int bank = npc_get_bank(mcam, index);
 127        int actbank = bank;
 128
 129        index &= (mcam->banksize - 1);
 130        for (; bank < (actbank + mcam->banks_per_entry); bank++) {
 131                rvu_write64(rvu, blkaddr,
 132                            NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
 133                rvu_write64(rvu, blkaddr,
 134                            NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
 135
 136                rvu_write64(rvu, blkaddr,
 137                            NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
 138                rvu_write64(rvu, blkaddr,
 139                            NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
 140
 141                rvu_write64(rvu, blkaddr,
 142                            NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
 143                rvu_write64(rvu, blkaddr,
 144                            NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
 145        }
 146}
 147
 148static void npc_get_keyword(struct mcam_entry *entry, int idx,
 149                            u64 *cam0, u64 *cam1)
 150{
 151        u64 kw_mask = 0x00;
 152
 153#define CAM_MASK(n)     (BIT_ULL(n) - 1)
 154
 155        /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
 156         * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
 157         *
 158         * Also, only 48 bits of BANKX_CAMX_W1 are valid.
 159         */
 160        switch (idx) {
 161        case 0:
 162                /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
 163                *cam1 = entry->kw[0];
 164                kw_mask = entry->kw_mask[0];
 165                break;
 166        case 1:
 167                /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
 168                *cam1 = entry->kw[1] & CAM_MASK(48);
 169                kw_mask = entry->kw_mask[1] & CAM_MASK(48);
 170                break;
 171        case 2:
 172                /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
 173                 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
 174                 */
 175                *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
 176                *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
 177                kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
 178                kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
 179                break;
 180        case 3:
 181                /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
 182                 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
 183                 */
 184                *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
 185                *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
 186                kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
 187                kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
 188                break;
 189        case 4:
 190                /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
 191                 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
 192                 */
 193                *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
 194                *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
 195                kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
 196                kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
 197                break;
 198        case 5:
 199                /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
 200                 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
 201                 */
 202                *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
 203                *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
 204                kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
 205                kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
 206                break;
 207        case 6:
 208                /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
 209                 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
 210                 */
 211                *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
 212                *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
 213                kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
 214                kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
 215                break;
 216        case 7:
 217                /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
 218                *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
 219                kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
 220                break;
 221        }
 222
 223        *cam1 &= kw_mask;
 224        *cam0 = ~*cam1 & kw_mask;
 225}
 226
 227static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 228                                  int blkaddr, int index, u8 intf,
 229                                  struct mcam_entry *entry, bool enable)
 230{
 231        int bank = npc_get_bank(mcam, index);
 232        int kw = 0, actbank, actindex;
 233        u64 cam0, cam1;
 234
 235        actbank = bank; /* Save bank id, to set action later on */
 236        actindex = index;
 237        index &= (mcam->banksize - 1);
 238
 239        /* Disable before mcam entry update */
 240        npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
 241
 242        /* Clear mcam entry to avoid writes being suppressed by NPC */
 243        npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
 244
 245        /* CAM1 takes the comparison value and
 246         * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
 247         * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
 248         * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
 249         * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
 250         */
 251        for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
 252                /* Interface should be set in all banks */
 253                rvu_write64(rvu, blkaddr,
 254                            NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
 255                            intf);
 256                rvu_write64(rvu, blkaddr,
 257                            NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
 258                            ~intf & 0x3);
 259
 260                /* Set the match key */
 261                npc_get_keyword(entry, kw, &cam0, &cam1);
 262                rvu_write64(rvu, blkaddr,
 263                            NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
 264                rvu_write64(rvu, blkaddr,
 265                            NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
 266
 267                npc_get_keyword(entry, kw + 1, &cam0, &cam1);
 268                rvu_write64(rvu, blkaddr,
 269                            NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
 270                rvu_write64(rvu, blkaddr,
 271                            NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
 272        }
 273
 274        /* Set 'action' */
 275        rvu_write64(rvu, blkaddr,
 276                    NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
 277
 278        /* Set TAG 'action' */
 279        rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
 280                    entry->vtag_action);
 281
 282        /* Enable the entry */
 283        if (enable)
 284                npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
 285}
 286
 287static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 288                                int blkaddr, u16 src, u16 dest)
 289{
 290        int dbank = npc_get_bank(mcam, dest);
 291        int sbank = npc_get_bank(mcam, src);
 292        u64 cfg, sreg, dreg;
 293        int bank, i;
 294
 295        src &= (mcam->banksize - 1);
 296        dest &= (mcam->banksize - 1);
 297
 298        /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */
 299        for (bank = 0; bank < mcam->banks_per_entry; bank++) {
 300                sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);
 301                dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);
 302                for (i = 0; i < 6; i++) {
 303                        cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8));
 304                        rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg);
 305                }
 306        }
 307
 308        /* Copy action */
 309        cfg = rvu_read64(rvu, blkaddr,
 310                         NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
 311        rvu_write64(rvu, blkaddr,
 312                    NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg);
 313
 314        /* Copy TAG action */
 315        cfg = rvu_read64(rvu, blkaddr,
 316                         NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
 317        rvu_write64(rvu, blkaddr,
 318                    NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg);
 319
 320        /* Enable or disable */
 321        cfg = rvu_read64(rvu, blkaddr,
 322                         NPC_AF_MCAMEX_BANKX_CFG(src, sbank));
 323        rvu_write64(rvu, blkaddr,
 324                    NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);
 325}
 326
 327static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
 328                               int blkaddr, int index)
 329{
 330        int bank = npc_get_bank(mcam, index);
 331
 332        index &= (mcam->banksize - 1);
 333        return rvu_read64(rvu, blkaddr,
 334                          NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
 335}
 336
 337void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
 338                                 int nixlf, u64 chan, u8 *mac_addr)
 339{
 340        struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
 341        struct npc_mcam *mcam = &rvu->hw->mcam;
 342        struct mcam_entry entry = { {0} };
 343        struct nix_rx_action action;
 344        int blkaddr, index, kwi;
 345        u64 mac = 0;
 346
 347        /* AF's VFs work in promiscuous mode */
 348        if (is_afvf(pcifunc))
 349                return;
 350
 351        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 352        if (blkaddr < 0)
 353                return;
 354
 355        for (index = ETH_ALEN - 1; index >= 0; index--)
 356                mac |= ((u64)*mac_addr++) << (8 * index);
 357
 358        index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 359                                         nixlf, NIXLF_UCAST_ENTRY);
 360
 361        /* Match ingress channel and DMAC */
 362        entry.kw[0] = chan;
 363        entry.kw_mask[0] = 0xFFFULL;
 364
 365        kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64);
 366        entry.kw[kwi] = mac;
 367        entry.kw_mask[kwi] = BIT_ULL(48) - 1;
 368
 369        /* Don't change the action if entry is already enabled
 370         * Otherwise RSS action may get overwritten.
 371         */
 372        if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
 373                *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
 374                                                      blkaddr, index);
 375        } else {
 376                *(u64 *)&action = 0x00;
 377                action.op = NIX_RX_ACTIONOP_UCAST;
 378                action.pf_func = pcifunc;
 379        }
 380
 381        entry.action = *(u64 *)&action;
 382        npc_config_mcam_entry(rvu, mcam, blkaddr, index,
 383                              NIX_INTF_RX, &entry, true);
 384
 385        /* add VLAN matching, setup action and save entry back for later */
 386        entry.kw[0] |= (NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG) << 20;
 387        entry.kw_mask[0] |= (NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG) << 20;
 388
 389        entry.vtag_action = VTAG0_VALID_BIT |
 390                            FIELD_PREP(VTAG0_TYPE_MASK, 0) |
 391                            FIELD_PREP(VTAG0_LID_MASK, NPC_LID_LA) |
 392                            FIELD_PREP(VTAG0_RELPTR_MASK, 12);
 393
 394        memcpy(&pfvf->entry, &entry, sizeof(entry));
 395}
 396
 397void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
 398                                   int nixlf, u64 chan, bool allmulti)
 399{
 400        struct npc_mcam *mcam = &rvu->hw->mcam;
 401        int blkaddr, ucast_idx, index, kwi;
 402        struct mcam_entry entry = { {0} };
 403        struct nix_rx_action action = { };
 404
 405        /* Only PF or AF VF can add a promiscuous entry */
 406        if ((pcifunc & RVU_PFVF_FUNC_MASK) && !is_afvf(pcifunc))
 407                return;
 408
 409        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 410        if (blkaddr < 0)
 411                return;
 412
 413        index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 414                                         nixlf, NIXLF_PROMISC_ENTRY);
 415
 416        entry.kw[0] = chan;
 417        entry.kw_mask[0] = 0xFFFULL;
 418
 419        if (allmulti) {
 420                kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64);
 421                entry.kw[kwi] = BIT_ULL(40); /* LSB bit of 1st byte in DMAC */
 422                entry.kw_mask[kwi] = BIT_ULL(40);
 423        }
 424
 425        ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
 426                                             nixlf, NIXLF_UCAST_ENTRY);
 427
 428        /* If the corresponding PF's ucast action is RSS,
 429         * use the same action for promisc also
 430         */
 431        if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
 432                *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
 433                                                        blkaddr, ucast_idx);
 434
 435        if (action.op != NIX_RX_ACTIONOP_RSS) {
 436                *(u64 *)&action = 0x00;
 437                action.op = NIX_RX_ACTIONOP_UCAST;
 438                action.pf_func = pcifunc;
 439        }
 440
 441        entry.action = *(u64 *)&action;
 442        npc_config_mcam_entry(rvu, mcam, blkaddr, index,
 443                              NIX_INTF_RX, &entry, true);
 444}
 445
 446static void npc_enadis_promisc_entry(struct rvu *rvu, u16 pcifunc,
 447                                     int nixlf, bool enable)
 448{
 449        struct npc_mcam *mcam = &rvu->hw->mcam;
 450        int blkaddr, index;
 451
 452        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 453        if (blkaddr < 0)
 454                return;
 455
 456        /* Only PF's have a promiscuous entry */
 457        if (pcifunc & RVU_PFVF_FUNC_MASK)
 458                return;
 459
 460        index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 461                                         nixlf, NIXLF_PROMISC_ENTRY);
 462        npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
 463}
 464
 465void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
 466{
 467        npc_enadis_promisc_entry(rvu, pcifunc, nixlf, false);
 468}
 469
 470void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
 471{
 472        npc_enadis_promisc_entry(rvu, pcifunc, nixlf, true);
 473}
 474
 475void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
 476                                       int nixlf, u64 chan)
 477{
 478        struct npc_mcam *mcam = &rvu->hw->mcam;
 479        struct mcam_entry entry = { {0} };
 480        struct rvu_hwinfo *hw = rvu->hw;
 481        struct nix_rx_action action;
 482        struct rvu_pfvf *pfvf;
 483        int blkaddr, index;
 484
 485        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 486        if (blkaddr < 0)
 487                return;
 488
 489        /* Skip LBK VFs */
 490        if (is_afvf(pcifunc))
 491                return;
 492
 493        /* If pkt replication is not supported,
 494         * then only PF is allowed to add a bcast match entry.
 495         */
 496        if (!hw->cap.nix_rx_multicast && pcifunc & RVU_PFVF_FUNC_MASK)
 497                return;
 498
 499        /* Get 'pcifunc' of PF device */
 500        pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 501        index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 502                                         nixlf, NIXLF_BCAST_ENTRY);
 503
 504        /* Match ingress channel */
 505        entry.kw[0] = chan;
 506        entry.kw_mask[0] = 0xfffull;
 507
 508        /* Match broadcast MAC address.
 509         * DMAC is extracted at 0th bit of PARSE_KEX::KW1
 510         */
 511        entry.kw[1] = 0xffffffffffffull;
 512        entry.kw_mask[1] = 0xffffffffffffull;
 513
 514        *(u64 *)&action = 0x00;
 515        if (!hw->cap.nix_rx_multicast) {
 516                /* Early silicon doesn't support pkt replication,
 517                 * so install entry with UCAST action, so that PF
 518                 * receives all broadcast packets.
 519                 */
 520                action.op = NIX_RX_ACTIONOP_UCAST;
 521                action.pf_func = pcifunc;
 522        } else {
 523                pfvf = rvu_get_pfvf(rvu, pcifunc);
 524                action.index = pfvf->bcast_mce_idx;
 525                action.op = NIX_RX_ACTIONOP_MCAST;
 526        }
 527
 528        entry.action = *(u64 *)&action;
 529        npc_config_mcam_entry(rvu, mcam, blkaddr, index,
 530                              NIX_INTF_RX, &entry, true);
 531}
 532
 533void rvu_npc_disable_bcast_entry(struct rvu *rvu, u16 pcifunc)
 534{
 535        struct npc_mcam *mcam = &rvu->hw->mcam;
 536        int blkaddr, index;
 537
 538        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 539        if (blkaddr < 0)
 540                return;
 541
 542        /* Get 'pcifunc' of PF device */
 543        pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 544
 545        index = npc_get_nixlf_mcam_index(mcam, pcifunc, 0, NIXLF_BCAST_ENTRY);
 546        npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
 547}
 548
 549void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
 550                                    int group, int alg_idx, int mcam_index)
 551{
 552        struct npc_mcam *mcam = &rvu->hw->mcam;
 553        struct nix_rx_action action;
 554        int blkaddr, index, bank;
 555
 556        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 557        if (blkaddr < 0)
 558                return;
 559
 560        /* Check if this is for reserved default entry */
 561        if (mcam_index < 0) {
 562                if (group != DEFAULT_RSS_CONTEXT_GROUP)
 563                        return;
 564                index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 565                                                 nixlf, NIXLF_UCAST_ENTRY);
 566        } else {
 567                /* TODO: validate this mcam index */
 568                index = mcam_index;
 569        }
 570
 571        if (index >= mcam->total_entries)
 572                return;
 573
 574        bank = npc_get_bank(mcam, index);
 575        index &= (mcam->banksize - 1);
 576
 577        *(u64 *)&action = rvu_read64(rvu, blkaddr,
 578                                     NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
 579        /* Ignore if no action was set earlier */
 580        if (!*(u64 *)&action)
 581                return;
 582
 583        action.op = NIX_RX_ACTIONOP_RSS;
 584        action.pf_func = pcifunc;
 585        action.index = group;
 586        action.flow_key_alg = alg_idx;
 587
 588        rvu_write64(rvu, blkaddr,
 589                    NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
 590
 591        index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 592                                         nixlf, NIXLF_PROMISC_ENTRY);
 593
 594        /* If PF's promiscuous entry is enabled,
 595         * Set RSS action for that entry as well
 596         */
 597        if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
 598                bank = npc_get_bank(mcam, index);
 599                index &= (mcam->banksize - 1);
 600
 601                rvu_write64(rvu, blkaddr,
 602                            NPC_AF_MCAMEX_BANKX_ACTION(index, bank),
 603                            *(u64 *)&action);
 604        }
 605
 606        rvu_npc_update_rxvlan(rvu, pcifunc, nixlf);
 607}
 608
 609static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,
 610                                       int nixlf, bool enable)
 611{
 612        struct npc_mcam *mcam = &rvu->hw->mcam;
 613        struct nix_rx_action action;
 614        int index, bank, blkaddr;
 615
 616        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 617        if (blkaddr < 0)
 618                return;
 619
 620        /* Ucast MCAM match entry of this PF/VF */
 621        index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 622                                         nixlf, NIXLF_UCAST_ENTRY);
 623        npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
 624
 625        /* For PF, ena/dis promisc and bcast MCAM match entries */
 626        if (pcifunc & RVU_PFVF_FUNC_MASK)
 627                return;
 628
 629        /* For bcast, enable/disable only if it's action is not
 630         * packet replication, incase if action is replication
 631         * then this PF's nixlf is removed from bcast replication
 632         * list.
 633         */
 634        index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 635                                         nixlf, NIXLF_BCAST_ENTRY);
 636        bank = npc_get_bank(mcam, index);
 637        *(u64 *)&action = rvu_read64(rvu, blkaddr,
 638             NPC_AF_MCAMEX_BANKX_ACTION(index & (mcam->banksize - 1), bank));
 639        if (action.op != NIX_RX_ACTIONOP_MCAST)
 640                npc_enable_mcam_entry(rvu, mcam,
 641                                      blkaddr, index, enable);
 642        if (enable)
 643                rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf);
 644        else
 645                rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf);
 646
 647        rvu_npc_update_rxvlan(rvu, pcifunc, nixlf);
 648}
 649
 650void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
 651{
 652        npc_enadis_default_entries(rvu, pcifunc, nixlf, false);
 653}
 654
 655void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
 656{
 657        npc_enadis_default_entries(rvu, pcifunc, nixlf, true);
 658}
 659
 660void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
 661{
 662        struct npc_mcam *mcam = &rvu->hw->mcam;
 663        int blkaddr;
 664
 665        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 666        if (blkaddr < 0)
 667                return;
 668
 669        mutex_lock(&mcam->lock);
 670
 671        /* Disable and free all MCAM entries mapped to this 'pcifunc' */
 672        npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
 673
 674        /* Free all MCAM counters mapped to this 'pcifunc' */
 675        npc_mcam_free_all_counters(rvu, mcam, pcifunc);
 676
 677        mutex_unlock(&mcam->lock);
 678
 679        rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
 680}
 681
 682#define SET_KEX_LD(intf, lid, ltype, ld, cfg)   \
 683        rvu_write64(rvu, blkaddr,                       \
 684                NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
 685
 686#define SET_KEX_LDFLAGS(intf, ld, flags, cfg)   \
 687        rvu_write64(rvu, blkaddr,                       \
 688                NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
 689
 690#define KEX_LD_CFG(bytesm1, hdr_ofs, ena, flags_ena, key_ofs)           \
 691                        (((bytesm1) << 16) | ((hdr_ofs) << 8) | ((ena) << 7) | \
 692                         ((flags_ena) << 6) | ((key_ofs) & 0x3F))
 693
 694static void npc_config_ldata_extract(struct rvu *rvu, int blkaddr)
 695{
 696        struct npc_mcam *mcam = &rvu->hw->mcam;
 697        int lid, ltype;
 698        int lid_count;
 699        u64 cfg;
 700
 701        cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
 702        lid_count = (cfg >> 4) & 0xF;
 703
 704        /* First clear any existing config i.e
 705         * disable LDATA and FLAGS extraction.
 706         */
 707        for (lid = 0; lid < lid_count; lid++) {
 708                for (ltype = 0; ltype < 16; ltype++) {
 709                        SET_KEX_LD(NIX_INTF_RX, lid, ltype, 0, 0ULL);
 710                        SET_KEX_LD(NIX_INTF_RX, lid, ltype, 1, 0ULL);
 711                        SET_KEX_LD(NIX_INTF_TX, lid, ltype, 0, 0ULL);
 712                        SET_KEX_LD(NIX_INTF_TX, lid, ltype, 1, 0ULL);
 713
 714                        SET_KEX_LDFLAGS(NIX_INTF_RX, 0, ltype, 0ULL);
 715                        SET_KEX_LDFLAGS(NIX_INTF_RX, 1, ltype, 0ULL);
 716                        SET_KEX_LDFLAGS(NIX_INTF_TX, 0, ltype, 0ULL);
 717                        SET_KEX_LDFLAGS(NIX_INTF_TX, 1, ltype, 0ULL);
 718                }
 719        }
 720
 721        if (mcam->keysize != NPC_MCAM_KEY_X2)
 722                return;
 723
 724        /* Default MCAM KEX profile */
 725        /* Layer A: Ethernet: */
 726
 727        /* DMAC: 6 bytes, KW1[47:0] */
 728        cfg = KEX_LD_CFG(0x05, 0x0, 0x1, 0x0, NPC_PARSE_RESULT_DMAC_OFFSET);
 729        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LA, NPC_LT_LA_ETHER, 0, cfg);
 730
 731        /* Ethertype: 2 bytes, KW0[47:32] */
 732        cfg = KEX_LD_CFG(0x01, 0xc, 0x1, 0x0, 0x4);
 733        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LA, NPC_LT_LA_ETHER, 1, cfg);
 734
 735        /* Layer B: Single VLAN (CTAG) */
 736        /* CTAG VLAN[2..3] + Ethertype, 4 bytes, KW0[63:32] */
 737        cfg = KEX_LD_CFG(0x03, 0x0, 0x1, 0x0, 0x4);
 738        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LB, NPC_LT_LB_CTAG, 0, cfg);
 739
 740        /* Layer B: Stacked VLAN (STAG|QinQ) */
 741        /* CTAG VLAN[2..3] + Ethertype, 4 bytes, KW0[63:32] */
 742        cfg = KEX_LD_CFG(0x03, 0x4, 0x1, 0x0, 0x4);
 743        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 0, cfg);
 744
 745        /* Layer C: IPv4 */
 746        /* SIP+DIP: 8 bytes, KW2[63:0] */
 747        cfg = KEX_LD_CFG(0x07, 0xc, 0x1, 0x0, 0x10);
 748        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LC, NPC_LT_LC_IP, 0, cfg);
 749        /* TOS: 1 byte, KW1[63:56] */
 750        cfg = KEX_LD_CFG(0x0, 0x1, 0x1, 0x0, 0xf);
 751        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LC, NPC_LT_LC_IP, 1, cfg);
 752
 753        /* Layer D:UDP */
 754        /* SPORT: 2 bytes, KW3[15:0] */
 755        cfg = KEX_LD_CFG(0x1, 0x0, 0x1, 0x0, 0x18);
 756        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_UDP, 0, cfg);
 757        /* DPORT: 2 bytes, KW3[31:16] */
 758        cfg = KEX_LD_CFG(0x1, 0x2, 0x1, 0x0, 0x1a);
 759        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_UDP, 1, cfg);
 760
 761        /* Layer D:TCP */
 762        /* SPORT: 2 bytes, KW3[15:0] */
 763        cfg = KEX_LD_CFG(0x1, 0x0, 0x1, 0x0, 0x18);
 764        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_TCP, 0, cfg);
 765        /* DPORT: 2 bytes, KW3[31:16] */
 766        cfg = KEX_LD_CFG(0x1, 0x2, 0x1, 0x0, 0x1a);
 767        SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_TCP, 1, cfg);
 768}
 769
 770static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr,
 771                                     struct npc_mcam_kex *mkex)
 772{
 773        int lid, lt, ld, fl;
 774
 775        rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX),
 776                    mkex->keyx_cfg[NIX_INTF_RX]);
 777        rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX),
 778                    mkex->keyx_cfg[NIX_INTF_TX]);
 779
 780        for (ld = 0; ld < NPC_MAX_LD; ld++)
 781                rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld),
 782                            mkex->kex_ld_flags[ld]);
 783
 784        for (lid = 0; lid < NPC_MAX_LID; lid++) {
 785                for (lt = 0; lt < NPC_MAX_LT; lt++) {
 786                        for (ld = 0; ld < NPC_MAX_LD; ld++) {
 787                                SET_KEX_LD(NIX_INTF_RX, lid, lt, ld,
 788                                           mkex->intf_lid_lt_ld[NIX_INTF_RX]
 789                                           [lid][lt][ld]);
 790
 791                                SET_KEX_LD(NIX_INTF_TX, lid, lt, ld,
 792                                           mkex->intf_lid_lt_ld[NIX_INTF_TX]
 793                                           [lid][lt][ld]);
 794                        }
 795                }
 796        }
 797
 798        for (ld = 0; ld < NPC_MAX_LD; ld++) {
 799                for (fl = 0; fl < NPC_MAX_LFL; fl++) {
 800                        SET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl,
 801                                        mkex->intf_ld_flags[NIX_INTF_RX]
 802                                        [ld][fl]);
 803
 804                        SET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl,
 805                                        mkex->intf_ld_flags[NIX_INTF_TX]
 806                                        [ld][fl]);
 807                }
 808        }
 809}
 810
 811/* strtoull of "mkexprof" with base:36 */
 812#define MKEX_SIGN      0x19bbfdbd15f
 813#define MKEX_END_SIGN  0xdeadbeef
 814
 815static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr)
 816{
 817        const char *mkex_profile = rvu->mkex_pfl_name;
 818        struct device *dev = &rvu->pdev->dev;
 819        void __iomem *mkex_prfl_addr = NULL;
 820        struct npc_mcam_kex *mcam_kex;
 821        u64 prfl_addr;
 822        u64 prfl_sz;
 823
 824        /* If user not selected mkex profile */
 825        if (!strncmp(mkex_profile, "default", MKEX_NAME_LEN))
 826                goto load_default;
 827
 828        if (!rvu->fwdata)
 829                goto load_default;
 830        prfl_addr = rvu->fwdata->mcam_addr;
 831        prfl_sz = rvu->fwdata->mcam_sz;
 832
 833        if (!prfl_addr || !prfl_sz)
 834                goto load_default;
 835
 836        mkex_prfl_addr = ioremap_wc(prfl_addr, prfl_sz);
 837        if (!mkex_prfl_addr)
 838                goto load_default;
 839
 840        mcam_kex = (struct npc_mcam_kex *)mkex_prfl_addr;
 841
 842        while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) {
 843                /* Compare with mkex mod_param name string */
 844                if (mcam_kex->mkex_sign == MKEX_SIGN &&
 845                    !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) {
 846                        /* Due to an errata (35786) in A0/B0 pass silicon,
 847                         * parse nibble enable configuration has to be
 848                         * identical for both Rx and Tx interfaces.
 849                         */
 850                        if (is_rvu_96xx_B0(rvu) &&
 851                            mcam_kex->keyx_cfg[NIX_INTF_RX] !=
 852                            mcam_kex->keyx_cfg[NIX_INTF_TX])
 853                                goto load_default;
 854
 855                        /* Program selected mkex profile */
 856                        npc_program_mkex_profile(rvu, blkaddr, mcam_kex);
 857
 858                        goto unmap;
 859                }
 860
 861                mcam_kex++;
 862                prfl_sz -= sizeof(struct npc_mcam_kex);
 863        }
 864        dev_warn(dev, "Failed to load requested profile: %s\n",
 865                 rvu->mkex_pfl_name);
 866
 867load_default:
 868        dev_info(rvu->dev, "Using default mkex profile\n");
 869        /* Config packet data and flags extraction into PARSE result */
 870        npc_config_ldata_extract(rvu, blkaddr);
 871
 872unmap:
 873        if (mkex_prfl_addr)
 874                iounmap(mkex_prfl_addr);
 875}
 876
 877static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
 878                                 struct npc_kpu_profile_action *kpuaction,
 879                                 int kpu, int entry, bool pkind)
 880{
 881        struct npc_kpu_action0 action0 = {0};
 882        struct npc_kpu_action1 action1 = {0};
 883        u64 reg;
 884
 885        action1.errlev = kpuaction->errlev;
 886        action1.errcode = kpuaction->errcode;
 887        action1.dp0_offset = kpuaction->dp0_offset;
 888        action1.dp1_offset = kpuaction->dp1_offset;
 889        action1.dp2_offset = kpuaction->dp2_offset;
 890
 891        if (pkind)
 892                reg = NPC_AF_PKINDX_ACTION1(entry);
 893        else
 894                reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
 895
 896        rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
 897
 898        action0.byp_count = kpuaction->bypass_count;
 899        action0.capture_ena = kpuaction->cap_ena;
 900        action0.parse_done = kpuaction->parse_done;
 901        action0.next_state = kpuaction->next_state;
 902        action0.capture_lid = kpuaction->lid;
 903        action0.capture_ltype = kpuaction->ltype;
 904        action0.capture_flags = kpuaction->flags;
 905        action0.ptr_advance = kpuaction->ptr_advance;
 906        action0.var_len_offset = kpuaction->offset;
 907        action0.var_len_mask = kpuaction->mask;
 908        action0.var_len_right = kpuaction->right;
 909        action0.var_len_shift = kpuaction->shift;
 910
 911        if (pkind)
 912                reg = NPC_AF_PKINDX_ACTION0(entry);
 913        else
 914                reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
 915
 916        rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
 917}
 918
 919static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
 920                              struct npc_kpu_profile_cam *kpucam,
 921                              int kpu, int entry)
 922{
 923        struct npc_kpu_cam cam0 = {0};
 924        struct npc_kpu_cam cam1 = {0};
 925
 926        cam1.state = kpucam->state & kpucam->state_mask;
 927        cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
 928        cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
 929        cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
 930
 931        cam0.state = ~kpucam->state & kpucam->state_mask;
 932        cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
 933        cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
 934        cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
 935
 936        rvu_write64(rvu, blkaddr,
 937                    NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
 938        rvu_write64(rvu, blkaddr,
 939                    NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
 940}
 941
 942static inline u64 enable_mask(int count)
 943{
 944        return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
 945}
 946
 947static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
 948                                    struct npc_kpu_profile *profile)
 949{
 950        int entry, num_entries, max_entries;
 951
 952        if (profile->cam_entries != profile->action_entries) {
 953                dev_err(rvu->dev,
 954                        "KPU%d: CAM and action entries [%d != %d] not equal\n",
 955                        kpu, profile->cam_entries, profile->action_entries);
 956        }
 957
 958        max_entries = rvu_read64(rvu, blkaddr, NPC_AF_CONST1) & 0xFFF;
 959
 960        /* Program CAM match entries for previous KPU extracted data */
 961        num_entries = min_t(int, profile->cam_entries, max_entries);
 962        for (entry = 0; entry < num_entries; entry++)
 963                npc_config_kpucam(rvu, blkaddr,
 964                                  &profile->cam[entry], kpu, entry);
 965
 966        /* Program this KPU's actions */
 967        num_entries = min_t(int, profile->action_entries, max_entries);
 968        for (entry = 0; entry < num_entries; entry++)
 969                npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
 970                                     kpu, entry, false);
 971
 972        /* Enable all programmed entries */
 973        num_entries = min_t(int, profile->action_entries, profile->cam_entries);
 974        rvu_write64(rvu, blkaddr,
 975                    NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries));
 976        if (num_entries > 64) {
 977                rvu_write64(rvu, blkaddr,
 978                            NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
 979                            enable_mask(num_entries - 64));
 980        }
 981
 982        /* Enable this KPU */
 983        rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
 984}
 985
 986static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
 987{
 988        struct rvu_hwinfo *hw = rvu->hw;
 989        int num_pkinds, num_kpus, idx;
 990        struct npc_pkind *pkind;
 991
 992        /* Get HW limits */
 993        hw->npc_kpus = (rvu_read64(rvu, blkaddr, NPC_AF_CONST) >> 8) & 0x1F;
 994
 995        /* Disable all KPUs and their entries */
 996        for (idx = 0; idx < hw->npc_kpus; idx++) {
 997                rvu_write64(rvu, blkaddr,
 998                            NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
 999                rvu_write64(rvu, blkaddr,
1000                            NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
1001                rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
1002        }
1003
1004        /* First program IKPU profile i.e PKIND configs.
1005         * Check HW max count to avoid configuring junk or
1006         * writing to unsupported CSR addresses.
1007         */
1008        pkind = &hw->pkind;
1009        num_pkinds = ARRAY_SIZE(ikpu_action_entries);
1010        num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds);
1011
1012        for (idx = 0; idx < num_pkinds; idx++)
1013                npc_config_kpuaction(rvu, blkaddr,
1014                                     &ikpu_action_entries[idx], 0, idx, true);
1015
1016        /* Program KPU CAM and Action profiles */
1017        num_kpus = ARRAY_SIZE(npc_kpu_profiles);
1018        num_kpus = min_t(int, hw->npc_kpus, num_kpus);
1019
1020        for (idx = 0; idx < num_kpus; idx++)
1021                npc_program_kpu_profile(rvu, blkaddr,
1022                                        idx, &npc_kpu_profiles[idx]);
1023}
1024
1025static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
1026{
1027        int nixlf_count = rvu_get_nixlf_count(rvu);
1028        struct npc_mcam *mcam = &rvu->hw->mcam;
1029        int rsvd, err;
1030        u64 cfg;
1031
1032        /* Get HW limits */
1033        cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1034        mcam->banks = (cfg >> 44) & 0xF;
1035        mcam->banksize = (cfg >> 28) & 0xFFFF;
1036        mcam->counters.max = (cfg >> 48) & 0xFFFF;
1037
1038        /* Actual number of MCAM entries vary by entry size */
1039        cfg = (rvu_read64(rvu, blkaddr,
1040                          NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
1041        mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
1042        mcam->keysize = cfg;
1043
1044        /* Number of banks combined per MCAM entry */
1045        if (cfg == NPC_MCAM_KEY_X4)
1046                mcam->banks_per_entry = 4;
1047        else if (cfg == NPC_MCAM_KEY_X2)
1048                mcam->banks_per_entry = 2;
1049        else
1050                mcam->banks_per_entry = 1;
1051
1052        /* Reserve one MCAM entry for each of the NIX LF to
1053         * guarantee space to install default matching DMAC rule.
1054         * Also reserve 2 MCAM entries for each PF for default
1055         * channel based matching or 'bcast & promisc' matching to
1056         * support BCAST and PROMISC modes of operation for PFs.
1057         * PF0 is excluded.
1058         */
1059        rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
1060                ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
1061        if (mcam->total_entries <= rsvd) {
1062                dev_warn(rvu->dev,
1063                         "Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
1064                         mcam->total_entries);
1065                return -ENOMEM;
1066        }
1067
1068        mcam->bmap_entries = mcam->total_entries - rsvd;
1069        mcam->nixlf_offset = mcam->bmap_entries;
1070        mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
1071
1072        /* Allocate bitmaps for managing MCAM entries */
1073        mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries),
1074                                  sizeof(long), GFP_KERNEL);
1075        if (!mcam->bmap)
1076                return -ENOMEM;
1077
1078        mcam->bmap_reverse = devm_kcalloc(rvu->dev,
1079                                          BITS_TO_LONGS(mcam->bmap_entries),
1080                                          sizeof(long), GFP_KERNEL);
1081        if (!mcam->bmap_reverse)
1082                return -ENOMEM;
1083
1084        mcam->bmap_fcnt = mcam->bmap_entries;
1085
1086        /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
1087        mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1088                                            sizeof(u16), GFP_KERNEL);
1089        if (!mcam->entry2pfvf_map)
1090                return -ENOMEM;
1091
1092        /* Reserve 1/8th of MCAM entries at the bottom for low priority
1093         * allocations and another 1/8th at the top for high priority
1094         * allocations.
1095         */
1096        mcam->lprio_count = mcam->bmap_entries / 8;
1097        if (mcam->lprio_count > BITS_PER_LONG)
1098                mcam->lprio_count = round_down(mcam->lprio_count,
1099                                               BITS_PER_LONG);
1100        mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;
1101        mcam->hprio_count = mcam->lprio_count;
1102        mcam->hprio_end = mcam->hprio_count;
1103
1104        /* Reserve last counter for MCAM RX miss action which is set to
1105         * drop pkt. This way we will know how many pkts didn't match
1106         * any MCAM entry.
1107         */
1108        mcam->counters.max--;
1109        mcam->rx_miss_act_cntr = mcam->counters.max;
1110
1111        /* Allocate bitmap for managing MCAM counters and memory
1112         * for saving counter to RVU PFFUNC allocation mapping.
1113         */
1114        err = rvu_alloc_bitmap(&mcam->counters);
1115        if (err)
1116                return err;
1117
1118        mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max,
1119                                           sizeof(u16), GFP_KERNEL);
1120        if (!mcam->cntr2pfvf_map)
1121                goto free_mem;
1122
1123        /* Alloc memory for MCAM entry to counter mapping and for tracking
1124         * counter's reference count.
1125         */
1126        mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1127                                            sizeof(u16), GFP_KERNEL);
1128        if (!mcam->entry2cntr_map)
1129                goto free_mem;
1130
1131        mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max,
1132                                         sizeof(u16), GFP_KERNEL);
1133        if (!mcam->cntr_refcnt)
1134                goto free_mem;
1135
1136        mutex_init(&mcam->lock);
1137
1138        return 0;
1139
1140free_mem:
1141        kfree(mcam->counters.bmap);
1142        return -ENOMEM;
1143}
1144
1145int rvu_npc_init(struct rvu *rvu)
1146{
1147        struct npc_pkind *pkind = &rvu->hw->pkind;
1148        struct npc_mcam *mcam = &rvu->hw->mcam;
1149        u64 keyz = NPC_MCAM_KEY_X2;
1150        int blkaddr, entry, bank, err;
1151        u64 cfg, nibble_ena;
1152
1153        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1154        if (blkaddr < 0) {
1155                dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
1156                return -ENODEV;
1157        }
1158
1159        /* First disable all MCAM entries, to stop traffic towards NIXLFs */
1160        cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1161        for (bank = 0; bank < ((cfg >> 44) & 0xF); bank++) {
1162                for (entry = 0; entry < ((cfg >> 28) & 0xFFFF); entry++)
1163                        rvu_write64(rvu, blkaddr,
1164                                    NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);
1165        }
1166
1167        /* Allocate resource bimap for pkind*/
1168        pkind->rsrc.max = (rvu_read64(rvu, blkaddr,
1169                                      NPC_AF_CONST1) >> 12) & 0xFF;
1170        err = rvu_alloc_bitmap(&pkind->rsrc);
1171        if (err)
1172                return err;
1173
1174        /* Allocate mem for pkind to PF and channel mapping info */
1175        pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
1176                                         sizeof(u32), GFP_KERNEL);
1177        if (!pkind->pfchan_map)
1178                return -ENOMEM;
1179
1180        /* Configure KPU profile */
1181        npc_parser_profile_init(rvu, blkaddr);
1182
1183        /* Config Outer L2, IPv4's NPC layer info */
1184        rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
1185                    (NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F);
1186        rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
1187                    (NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F);
1188
1189        /* Config Inner IPV4 NPC layer info */
1190        rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4,
1191                    (NPC_LID_LG << 8) | (NPC_LT_LG_TU_IP << 4) | 0x0F);
1192
1193        /* Enable below for Rx pkts.
1194         * - Outer IPv4 header checksum validation.
1195         * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M].
1196         * - Inner IPv4 header checksum validation.
1197         * - Set non zero checksum error code value
1198         */
1199        rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
1200                    rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
1201                    BIT_ULL(32) | BIT_ULL(24) | BIT_ULL(6) |
1202                    BIT_ULL(2) | BIT_ULL(1));
1203
1204        /* Set RX and TX side MCAM search key size.
1205         * LA..LD (ltype only) + Channel
1206         */
1207        nibble_ena = 0x49247;
1208        rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX),
1209                        ((keyz & 0x3) << 32) | nibble_ena);
1210        /* Due to an errata (35786) in A0 pass silicon, parse nibble enable
1211         * configuration has to be identical for both Rx and Tx interfaces.
1212         */
1213        if (!is_rvu_96xx_B0(rvu))
1214                nibble_ena = (1ULL << 19) - 1;
1215        rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX),
1216                        ((keyz & 0x3) << 32) | nibble_ena);
1217
1218        err = npc_mcam_rsrcs_init(rvu, blkaddr);
1219        if (err)
1220                return err;
1221
1222        /* Configure MKEX profile */
1223        npc_load_mkex_profile(rvu, blkaddr);
1224
1225        /* Set TX miss action to UCAST_DEFAULT i.e
1226         * transmit the packet on NIX LF SQ's default channel.
1227         */
1228        rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_TX),
1229                    NIX_TX_ACTIONOP_UCAST_DEFAULT);
1230
1231        /* If MCAM lookup doesn't result in a match, drop the received packet.
1232         * And map this action to a counter to count dropped pkts.
1233         */
1234        rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_RX),
1235                    NIX_RX_ACTIONOP_DROP);
1236        rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_STAT_ACT(NIX_INTF_RX),
1237                    BIT_ULL(9) | mcam->rx_miss_act_cntr);
1238
1239        return 0;
1240}
1241
1242void rvu_npc_freemem(struct rvu *rvu)
1243{
1244        struct npc_pkind *pkind = &rvu->hw->pkind;
1245        struct npc_mcam *mcam = &rvu->hw->mcam;
1246
1247        kfree(pkind->rsrc.bmap);
1248        kfree(mcam->counters.bmap);
1249        mutex_destroy(&mcam->lock);
1250}
1251
1252void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
1253                                       int blkaddr, int *alloc_cnt,
1254                                       int *enable_cnt)
1255{
1256        struct npc_mcam *mcam = &rvu->hw->mcam;
1257        int entry;
1258
1259        *alloc_cnt = 0;
1260        *enable_cnt = 0;
1261
1262        for (entry = 0; entry < mcam->bmap_entries; entry++) {
1263                if (mcam->entry2pfvf_map[entry] == pcifunc) {
1264                        (*alloc_cnt)++;
1265                        if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry))
1266                                (*enable_cnt)++;
1267                }
1268        }
1269}
1270
1271void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
1272                                         int blkaddr, int *alloc_cnt,
1273                                         int *enable_cnt)
1274{
1275        struct npc_mcam *mcam = &rvu->hw->mcam;
1276        int cntr;
1277
1278        *alloc_cnt = 0;
1279        *enable_cnt = 0;
1280
1281        for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1282                if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1283                        (*alloc_cnt)++;
1284                        if (mcam->cntr_refcnt[cntr])
1285                                (*enable_cnt)++;
1286                }
1287        }
1288}
1289
1290static int npc_mcam_verify_entry(struct npc_mcam *mcam,
1291                                 u16 pcifunc, int entry)
1292{
1293        /* Verify if entry is valid and if it is indeed
1294         * allocated to the requesting PFFUNC.
1295         */
1296        if (entry >= mcam->bmap_entries)
1297                return NPC_MCAM_INVALID_REQ;
1298
1299        if (pcifunc != mcam->entry2pfvf_map[entry])
1300                return NPC_MCAM_PERM_DENIED;
1301
1302        return 0;
1303}
1304
1305static int npc_mcam_verify_counter(struct npc_mcam *mcam,
1306                                   u16 pcifunc, int cntr)
1307{
1308        /* Verify if counter is valid and if it is indeed
1309         * allocated to the requesting PFFUNC.
1310         */
1311        if (cntr >= mcam->counters.max)
1312                return NPC_MCAM_INVALID_REQ;
1313
1314        if (pcifunc != mcam->cntr2pfvf_map[cntr])
1315                return NPC_MCAM_PERM_DENIED;
1316
1317        return 0;
1318}
1319
1320static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam,
1321                                        int blkaddr, u16 entry, u16 cntr)
1322{
1323        u16 index = entry & (mcam->banksize - 1);
1324        u16 bank = npc_get_bank(mcam, entry);
1325
1326        /* Set mapping and increment counter's refcnt */
1327        mcam->entry2cntr_map[entry] = cntr;
1328        mcam->cntr_refcnt[cntr]++;
1329        /* Enable stats */
1330        rvu_write64(rvu, blkaddr,
1331                    NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),
1332                    BIT_ULL(9) | cntr);
1333}
1334
1335static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu,
1336                                          struct npc_mcam *mcam,
1337                                          int blkaddr, u16 entry, u16 cntr)
1338{
1339        u16 index = entry & (mcam->banksize - 1);
1340        u16 bank = npc_get_bank(mcam, entry);
1341
1342        /* Remove mapping and reduce counter's refcnt */
1343        mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP;
1344        mcam->cntr_refcnt[cntr]--;
1345        /* Disable stats */
1346        rvu_write64(rvu, blkaddr,
1347                    NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);
1348}
1349
1350/* Sets MCAM entry in bitmap as used. Update
1351 * reverse bitmap too. Should be called with
1352 * 'mcam->lock' held.
1353 */
1354static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index)
1355{
1356        u16 entry, rentry;
1357
1358        entry = index;
1359        rentry = mcam->bmap_entries - index - 1;
1360
1361        __set_bit(entry, mcam->bmap);
1362        __set_bit(rentry, mcam->bmap_reverse);
1363        mcam->bmap_fcnt--;
1364}
1365
1366/* Sets MCAM entry in bitmap as free. Update
1367 * reverse bitmap too. Should be called with
1368 * 'mcam->lock' held.
1369 */
1370static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index)
1371{
1372        u16 entry, rentry;
1373
1374        entry = index;
1375        rentry = mcam->bmap_entries - index - 1;
1376
1377        __clear_bit(entry, mcam->bmap);
1378        __clear_bit(rentry, mcam->bmap_reverse);
1379        mcam->bmap_fcnt++;
1380}
1381
1382static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
1383                                      int blkaddr, u16 pcifunc)
1384{
1385        u16 index, cntr;
1386
1387        /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */
1388        for (index = 0; index < mcam->bmap_entries; index++) {
1389                if (mcam->entry2pfvf_map[index] == pcifunc) {
1390                        mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
1391                        /* Free the entry in bitmap */
1392                        npc_mcam_clear_bit(mcam, index);
1393                        /* Disable the entry */
1394                        npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
1395
1396                        /* Update entry2counter mapping */
1397                        cntr = mcam->entry2cntr_map[index];
1398                        if (cntr != NPC_MCAM_INVALID_MAP)
1399                                npc_unmap_mcam_entry_and_cntr(rvu, mcam,
1400                                                              blkaddr, index,
1401                                                              cntr);
1402                }
1403        }
1404}
1405
1406static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
1407                                       u16 pcifunc)
1408{
1409        u16 cntr;
1410
1411        /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */
1412        for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1413                if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1414                        mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
1415                        mcam->cntr_refcnt[cntr] = 0;
1416                        rvu_free_rsrc(&mcam->counters, cntr);
1417                        /* This API is expected to be called after freeing
1418                         * MCAM entries, which inturn will remove
1419                         * 'entry to counter' mapping.
1420                         * No need to do it again.
1421                         */
1422                }
1423        }
1424}
1425
1426/* Find area of contiguous free entries of size 'nr'.
1427 * If not found return max contiguous free entries available.
1428 */
1429static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start,
1430                                   u16 nr, u16 *max_area)
1431{
1432        u16 max_area_start = 0;
1433        u16 index, next, end;
1434
1435        *max_area = 0;
1436
1437again:
1438        index = find_next_zero_bit(map, size, start);
1439        if (index >= size)
1440                return max_area_start;
1441
1442        end = ((index + nr) >= size) ? size : index + nr;
1443        next = find_next_bit(map, end, index);
1444        if (*max_area < (next - index)) {
1445                *max_area = next - index;
1446                max_area_start = index;
1447        }
1448
1449        if (next < end) {
1450                start = next + 1;
1451                goto again;
1452        }
1453
1454        return max_area_start;
1455}
1456
1457/* Find number of free MCAM entries available
1458 * within range i.e in between 'start' and 'end'.
1459 */
1460static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end)
1461{
1462        u16 index, next;
1463        u16 fcnt = 0;
1464
1465again:
1466        if (start >= end)
1467                return fcnt;
1468
1469        index = find_next_zero_bit(map, end, start);
1470        if (index >= end)
1471                return fcnt;
1472
1473        next = find_next_bit(map, end, index);
1474        if (next <= end) {
1475                fcnt += next - index;
1476                start = next + 1;
1477                goto again;
1478        }
1479
1480        fcnt += end - index;
1481        return fcnt;
1482}
1483
1484static void
1485npc_get_mcam_search_range_priority(struct npc_mcam *mcam,
1486                                   struct npc_mcam_alloc_entry_req *req,
1487                                   u16 *start, u16 *end, bool *reverse)
1488{
1489        u16 fcnt;
1490
1491        if (req->priority == NPC_MCAM_HIGHER_PRIO)
1492                goto hprio;
1493
1494        /* For a low priority entry allocation
1495         * - If reference entry is not in hprio zone then
1496         *      search range: ref_entry to end.
1497         * - If reference entry is in hprio zone and if
1498         *   request can be accomodated in non-hprio zone then
1499         *      search range: 'start of middle zone' to 'end'
1500         * - else search in reverse, so that less number of hprio
1501         *   zone entries are allocated.
1502         */
1503
1504        *reverse = false;
1505        *start = req->ref_entry + 1;
1506        *end = mcam->bmap_entries;
1507
1508        if (req->ref_entry >= mcam->hprio_end)
1509                return;
1510
1511        fcnt = npc_mcam_get_free_count(mcam->bmap,
1512                                       mcam->hprio_end, mcam->bmap_entries);
1513        if (fcnt > req->count)
1514                *start = mcam->hprio_end;
1515        else
1516                *reverse = true;
1517        return;
1518
1519hprio:
1520        /* For a high priority entry allocation, search is always
1521         * in reverse to preserve hprio zone entries.
1522         * - If reference entry is not in lprio zone then
1523         *      search range: 0 to ref_entry.
1524         * - If reference entry is in lprio zone and if
1525         *   request can be accomodated in middle zone then
1526         *      search range: 'hprio_end' to 'lprio_start'
1527         */
1528
1529        *reverse = true;
1530        *start = 0;
1531        *end = req->ref_entry;
1532
1533        if (req->ref_entry <= mcam->lprio_start)
1534                return;
1535
1536        fcnt = npc_mcam_get_free_count(mcam->bmap,
1537                                       mcam->hprio_end, mcam->lprio_start);
1538        if (fcnt < req->count)
1539                return;
1540        *start = mcam->hprio_end;
1541        *end = mcam->lprio_start;
1542}
1543
1544static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc,
1545                                  struct npc_mcam_alloc_entry_req *req,
1546                                  struct npc_mcam_alloc_entry_rsp *rsp)
1547{
1548        u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1549        u16 fcnt, hp_fcnt, lp_fcnt;
1550        u16 start, end, index;
1551        int entry, next_start;
1552        bool reverse = false;
1553        unsigned long *bmap;
1554        u16 max_contig;
1555
1556        mutex_lock(&mcam->lock);
1557
1558        /* Check if there are any free entries */
1559        if (!mcam->bmap_fcnt) {
1560                mutex_unlock(&mcam->lock);
1561                return NPC_MCAM_ALLOC_FAILED;
1562        }
1563
1564        /* MCAM entries are divided into high priority, middle and
1565         * low priority zones. Idea is to not allocate top and lower
1566         * most entries as much as possible, this is to increase
1567         * probability of honouring priority allocation requests.
1568         *
1569         * Two bitmaps are used for mcam entry management,
1570         * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'.
1571         * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'.
1572         *
1573         * Reverse bitmap is used to allocate entries
1574         * - when a higher priority entry is requested
1575         * - when available free entries are less.
1576         * Lower priority ones out of avaialble free entries are always
1577         * chosen when 'high vs low' question arises.
1578         */
1579
1580        /* Get the search range for priority allocation request */
1581        if (req->priority) {
1582                npc_get_mcam_search_range_priority(mcam, req,
1583                                                   &start, &end, &reverse);
1584                goto alloc;
1585        }
1586
1587        /* Find out the search range for non-priority allocation request
1588         *
1589         * Get MCAM free entry count in middle zone.
1590         */
1591        lp_fcnt = npc_mcam_get_free_count(mcam->bmap,
1592                                          mcam->lprio_start,
1593                                          mcam->bmap_entries);
1594        hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end);
1595        fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt;
1596
1597        /* Check if request can be accomodated in the middle zone */
1598        if (fcnt > req->count) {
1599                start = mcam->hprio_end;
1600                end = mcam->lprio_start;
1601        } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) {
1602                /* Expand search zone from half of hprio zone to
1603                 * half of lprio zone.
1604                 */
1605                start = mcam->hprio_end / 2;
1606                end = mcam->bmap_entries - (mcam->lprio_count / 2);
1607                reverse = true;
1608        } else {
1609                /* Not enough free entries, search all entries in reverse,
1610                 * so that low priority ones will get used up.
1611                 */
1612                reverse = true;
1613                start = 0;
1614                end = mcam->bmap_entries;
1615        }
1616
1617alloc:
1618        if (reverse) {
1619                bmap = mcam->bmap_reverse;
1620                start = mcam->bmap_entries - start;
1621                end = mcam->bmap_entries - end;
1622                index = start;
1623                start = end;
1624                end = index;
1625        } else {
1626                bmap = mcam->bmap;
1627        }
1628
1629        if (req->contig) {
1630                /* Allocate requested number of contiguous entries, if
1631                 * unsuccessful find max contiguous entries available.
1632                 */
1633                index = npc_mcam_find_zero_area(bmap, end, start,
1634                                                req->count, &max_contig);
1635                rsp->count = max_contig;
1636                if (reverse)
1637                        rsp->entry = mcam->bmap_entries - index - max_contig;
1638                else
1639                        rsp->entry = index;
1640        } else {
1641                /* Allocate requested number of non-contiguous entries,
1642                 * if unsuccessful allocate as many as possible.
1643                 */
1644                rsp->count = 0;
1645                next_start = start;
1646                for (entry = 0; entry < req->count; entry++) {
1647                        index = find_next_zero_bit(bmap, end, next_start);
1648                        if (index >= end)
1649                                break;
1650
1651                        next_start = start + (index - start) + 1;
1652
1653                        /* Save the entry's index */
1654                        if (reverse)
1655                                index = mcam->bmap_entries - index - 1;
1656                        entry_list[entry] = index;
1657                        rsp->count++;
1658                }
1659        }
1660
1661        /* If allocating requested no of entries is unsucessful,
1662         * expand the search range to full bitmap length and retry.
1663         */
1664        if (!req->priority && (rsp->count < req->count) &&
1665            ((end - start) != mcam->bmap_entries)) {
1666                reverse = true;
1667                start = 0;
1668                end = mcam->bmap_entries;
1669                goto alloc;
1670        }
1671
1672        /* For priority entry allocation requests, if allocation is
1673         * failed then expand search to max possible range and retry.
1674         */
1675        if (req->priority && rsp->count < req->count) {
1676                if (req->priority == NPC_MCAM_LOWER_PRIO &&
1677                    (start != (req->ref_entry + 1))) {
1678                        start = req->ref_entry + 1;
1679                        end = mcam->bmap_entries;
1680                        reverse = false;
1681                        goto alloc;
1682                } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) &&
1683                           ((end - start) != req->ref_entry)) {
1684                        start = 0;
1685                        end = req->ref_entry;
1686                        reverse = true;
1687                        goto alloc;
1688                }
1689        }
1690
1691        /* Copy MCAM entry indices into mbox response entry_list.
1692         * Requester always expects indices in ascending order, so
1693         * so reverse the list if reverse bitmap is used for allocation.
1694         */
1695        if (!req->contig && rsp->count) {
1696                index = 0;
1697                for (entry = rsp->count - 1; entry >= 0; entry--) {
1698                        if (reverse)
1699                                rsp->entry_list[index++] = entry_list[entry];
1700                        else
1701                                rsp->entry_list[entry] = entry_list[entry];
1702                }
1703        }
1704
1705        /* Mark the allocated entries as used and set nixlf mapping */
1706        for (entry = 0; entry < rsp->count; entry++) {
1707                index = req->contig ?
1708                        (rsp->entry + entry) : rsp->entry_list[entry];
1709                npc_mcam_set_bit(mcam, index);
1710                mcam->entry2pfvf_map[index] = pcifunc;
1711                mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
1712        }
1713
1714        /* Update available free count in mbox response */
1715        rsp->free_count = mcam->bmap_fcnt;
1716
1717        mutex_unlock(&mcam->lock);
1718        return 0;
1719}
1720
1721int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
1722                                          struct npc_mcam_alloc_entry_req *req,
1723                                          struct npc_mcam_alloc_entry_rsp *rsp)
1724{
1725        struct npc_mcam *mcam = &rvu->hw->mcam;
1726        u16 pcifunc = req->hdr.pcifunc;
1727        int blkaddr;
1728
1729        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1730        if (blkaddr < 0)
1731                return NPC_MCAM_INVALID_REQ;
1732
1733        rsp->entry = NPC_MCAM_ENTRY_INVALID;
1734        rsp->free_count = 0;
1735
1736        /* Check if ref_entry is within range */
1737        if (req->priority && req->ref_entry >= mcam->bmap_entries)
1738                return NPC_MCAM_INVALID_REQ;
1739
1740        /* ref_entry can't be '0' if requested priority is high.
1741         * Can't be last entry if requested priority is low.
1742         */
1743        if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) ||
1744            ((req->ref_entry == (mcam->bmap_entries - 1)) &&
1745             req->priority == NPC_MCAM_LOWER_PRIO))
1746                return NPC_MCAM_INVALID_REQ;
1747
1748        /* Since list of allocated indices needs to be sent to requester,
1749         * max number of non-contiguous entries per mbox msg is limited.
1750         */
1751        if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES)
1752                return NPC_MCAM_INVALID_REQ;
1753
1754        /* Alloc request from PFFUNC with no NIXLF attached should be denied */
1755        if (!is_nixlf_attached(rvu, pcifunc))
1756                return NPC_MCAM_ALLOC_DENIED;
1757
1758        return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
1759}
1760
1761int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
1762                                         struct npc_mcam_free_entry_req *req,
1763                                         struct msg_rsp *rsp)
1764{
1765        struct npc_mcam *mcam = &rvu->hw->mcam;
1766        u16 pcifunc = req->hdr.pcifunc;
1767        int blkaddr, rc = 0;
1768        u16 cntr;
1769
1770        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1771        if (blkaddr < 0)
1772                return NPC_MCAM_INVALID_REQ;
1773
1774        /* Free request from PFFUNC with no NIXLF attached, ignore */
1775        if (!is_nixlf_attached(rvu, pcifunc))
1776                return NPC_MCAM_INVALID_REQ;
1777
1778        mutex_lock(&mcam->lock);
1779
1780        if (req->all)
1781                goto free_all;
1782
1783        rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1784        if (rc)
1785                goto exit;
1786
1787        mcam->entry2pfvf_map[req->entry] = 0;
1788        npc_mcam_clear_bit(mcam, req->entry);
1789        npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
1790
1791        /* Update entry2counter mapping */
1792        cntr = mcam->entry2cntr_map[req->entry];
1793        if (cntr != NPC_MCAM_INVALID_MAP)
1794                npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1795                                              req->entry, cntr);
1796
1797        goto exit;
1798
1799free_all:
1800        /* Free up all entries allocated to requesting PFFUNC */
1801        npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
1802exit:
1803        mutex_unlock(&mcam->lock);
1804        return rc;
1805}
1806
1807int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
1808                                          struct npc_mcam_write_entry_req *req,
1809                                          struct msg_rsp *rsp)
1810{
1811        struct npc_mcam *mcam = &rvu->hw->mcam;
1812        u16 pcifunc = req->hdr.pcifunc;
1813        int blkaddr, rc;
1814
1815        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1816        if (blkaddr < 0)
1817                return NPC_MCAM_INVALID_REQ;
1818
1819        mutex_lock(&mcam->lock);
1820        rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1821        if (rc)
1822                goto exit;
1823
1824        if (req->set_cntr &&
1825            npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) {
1826                rc = NPC_MCAM_INVALID_REQ;
1827                goto exit;
1828        }
1829
1830        if (req->intf != NIX_INTF_RX && req->intf != NIX_INTF_TX) {
1831                rc = NPC_MCAM_INVALID_REQ;
1832                goto exit;
1833        }
1834
1835        npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, req->intf,
1836                              &req->entry_data, req->enable_entry);
1837
1838        if (req->set_cntr)
1839                npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1840                                            req->entry, req->cntr);
1841
1842        rc = 0;
1843exit:
1844        mutex_unlock(&mcam->lock);
1845        return rc;
1846}
1847
1848int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
1849                                        struct npc_mcam_ena_dis_entry_req *req,
1850                                        struct msg_rsp *rsp)
1851{
1852        struct npc_mcam *mcam = &rvu->hw->mcam;
1853        u16 pcifunc = req->hdr.pcifunc;
1854        int blkaddr, rc;
1855
1856        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1857        if (blkaddr < 0)
1858                return NPC_MCAM_INVALID_REQ;
1859
1860        mutex_lock(&mcam->lock);
1861        rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1862        mutex_unlock(&mcam->lock);
1863        if (rc)
1864                return rc;
1865
1866        npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true);
1867
1868        return 0;
1869}
1870
1871int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
1872                                        struct npc_mcam_ena_dis_entry_req *req,
1873                                        struct msg_rsp *rsp)
1874{
1875        struct npc_mcam *mcam = &rvu->hw->mcam;
1876        u16 pcifunc = req->hdr.pcifunc;
1877        int blkaddr, rc;
1878
1879        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1880        if (blkaddr < 0)
1881                return NPC_MCAM_INVALID_REQ;
1882
1883        mutex_lock(&mcam->lock);
1884        rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
1885        mutex_unlock(&mcam->lock);
1886        if (rc)
1887                return rc;
1888
1889        npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
1890
1891        return 0;
1892}
1893
1894int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
1895                                          struct npc_mcam_shift_entry_req *req,
1896                                          struct npc_mcam_shift_entry_rsp *rsp)
1897{
1898        struct npc_mcam *mcam = &rvu->hw->mcam;
1899        u16 pcifunc = req->hdr.pcifunc;
1900        u16 old_entry, new_entry;
1901        u16 index, cntr;
1902        int blkaddr, rc;
1903
1904        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1905        if (blkaddr < 0)
1906                return NPC_MCAM_INVALID_REQ;
1907
1908        if (req->shift_count > NPC_MCAM_MAX_SHIFTS)
1909                return NPC_MCAM_INVALID_REQ;
1910
1911        mutex_lock(&mcam->lock);
1912        for (index = 0; index < req->shift_count; index++) {
1913                old_entry = req->curr_entry[index];
1914                new_entry = req->new_entry[index];
1915
1916                /* Check if both old and new entries are valid and
1917                 * does belong to this PFFUNC or not.
1918                 */
1919                rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry);
1920                if (rc)
1921                        break;
1922
1923                rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry);
1924                if (rc)
1925                        break;
1926
1927                /* new_entry should not have a counter mapped */
1928                if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) {
1929                        rc = NPC_MCAM_PERM_DENIED;
1930                        break;
1931                }
1932
1933                /* Disable the new_entry */
1934                npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false);
1935
1936                /* Copy rule from old entry to new entry */
1937                npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry);
1938
1939                /* Copy counter mapping, if any */
1940                cntr = mcam->entry2cntr_map[old_entry];
1941                if (cntr != NPC_MCAM_INVALID_MAP) {
1942                        npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1943                                                      old_entry, cntr);
1944                        npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
1945                                                    new_entry, cntr);
1946                }
1947
1948                /* Enable new_entry and disable old_entry */
1949                npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true);
1950                npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false);
1951        }
1952
1953        /* If shift has failed then report the failed index */
1954        if (index != req->shift_count) {
1955                rc = NPC_MCAM_PERM_DENIED;
1956                rsp->failed_entry_idx = index;
1957        }
1958
1959        mutex_unlock(&mcam->lock);
1960        return rc;
1961}
1962
1963int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
1964                        struct npc_mcam_alloc_counter_req *req,
1965                        struct npc_mcam_alloc_counter_rsp *rsp)
1966{
1967        struct npc_mcam *mcam = &rvu->hw->mcam;
1968        u16 pcifunc = req->hdr.pcifunc;
1969        u16 max_contig, cntr;
1970        int blkaddr, index;
1971
1972        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1973        if (blkaddr < 0)
1974                return NPC_MCAM_INVALID_REQ;
1975
1976        /* If the request is from a PFFUNC with no NIXLF attached, ignore */
1977        if (!is_nixlf_attached(rvu, pcifunc))
1978                return NPC_MCAM_INVALID_REQ;
1979
1980        /* Since list of allocated counter IDs needs to be sent to requester,
1981         * max number of non-contiguous counters per mbox msg is limited.
1982         */
1983        if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS)
1984                return NPC_MCAM_INVALID_REQ;
1985
1986        mutex_lock(&mcam->lock);
1987
1988        /* Check if unused counters are available or not */
1989        if (!rvu_rsrc_free_count(&mcam->counters)) {
1990                mutex_unlock(&mcam->lock);
1991                return NPC_MCAM_ALLOC_FAILED;
1992        }
1993
1994        rsp->count = 0;
1995
1996        if (req->contig) {
1997                /* Allocate requested number of contiguous counters, if
1998                 * unsuccessful find max contiguous entries available.
1999                 */
2000                index = npc_mcam_find_zero_area(mcam->counters.bmap,
2001                                                mcam->counters.max, 0,
2002                                                req->count, &max_contig);
2003                rsp->count = max_contig;
2004                rsp->cntr = index;
2005                for (cntr = index; cntr < (index + max_contig); cntr++) {
2006                        __set_bit(cntr, mcam->counters.bmap);
2007                        mcam->cntr2pfvf_map[cntr] = pcifunc;
2008                }
2009        } else {
2010                /* Allocate requested number of non-contiguous counters,
2011                 * if unsuccessful allocate as many as possible.
2012                 */
2013                for (cntr = 0; cntr < req->count; cntr++) {
2014                        index = rvu_alloc_rsrc(&mcam->counters);
2015                        if (index < 0)
2016                                break;
2017                        rsp->cntr_list[cntr] = index;
2018                        rsp->count++;
2019                        mcam->cntr2pfvf_map[index] = pcifunc;
2020                }
2021        }
2022
2023        mutex_unlock(&mcam->lock);
2024        return 0;
2025}
2026
2027int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
2028                struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2029{
2030        struct npc_mcam *mcam = &rvu->hw->mcam;
2031        u16 index, entry = 0;
2032        int blkaddr, err;
2033
2034        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2035        if (blkaddr < 0)
2036                return NPC_MCAM_INVALID_REQ;
2037
2038        mutex_lock(&mcam->lock);
2039        err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2040        if (err) {
2041                mutex_unlock(&mcam->lock);
2042                return err;
2043        }
2044
2045        /* Mark counter as free/unused */
2046        mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP;
2047        rvu_free_rsrc(&mcam->counters, req->cntr);
2048
2049        /* Disable all MCAM entry's stats which are using this counter */
2050        while (entry < mcam->bmap_entries) {
2051                if (!mcam->cntr_refcnt[req->cntr])
2052                        break;
2053
2054                index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2055                if (index >= mcam->bmap_entries)
2056                        break;
2057                if (mcam->entry2cntr_map[index] != req->cntr)
2058                        continue;
2059
2060                entry = index + 1;
2061                npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2062                                              index, req->cntr);
2063        }
2064
2065        mutex_unlock(&mcam->lock);
2066        return 0;
2067}
2068
2069int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
2070                struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp)
2071{
2072        struct npc_mcam *mcam = &rvu->hw->mcam;
2073        u16 index, entry = 0;
2074        int blkaddr, rc;
2075
2076        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2077        if (blkaddr < 0)
2078                return NPC_MCAM_INVALID_REQ;
2079
2080        mutex_lock(&mcam->lock);
2081        rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2082        if (rc)
2083                goto exit;
2084
2085        /* Unmap the MCAM entry and counter */
2086        if (!req->all) {
2087                rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry);
2088                if (rc)
2089                        goto exit;
2090                npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2091                                              req->entry, req->cntr);
2092                goto exit;
2093        }
2094
2095        /* Disable all MCAM entry's stats which are using this counter */
2096        while (entry < mcam->bmap_entries) {
2097                if (!mcam->cntr_refcnt[req->cntr])
2098                        break;
2099
2100                index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2101                if (index >= mcam->bmap_entries)
2102                        break;
2103                if (mcam->entry2cntr_map[index] != req->cntr)
2104                        continue;
2105
2106                entry = index + 1;
2107                npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2108                                              index, req->cntr);
2109        }
2110exit:
2111        mutex_unlock(&mcam->lock);
2112        return rc;
2113}
2114
2115int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
2116                struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2117{
2118        struct npc_mcam *mcam = &rvu->hw->mcam;
2119        int blkaddr, err;
2120
2121        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2122        if (blkaddr < 0)
2123                return NPC_MCAM_INVALID_REQ;
2124
2125        mutex_lock(&mcam->lock);
2126        err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2127        mutex_unlock(&mcam->lock);
2128        if (err)
2129                return err;
2130
2131        rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00);
2132
2133        return 0;
2134}
2135
2136int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
2137                        struct npc_mcam_oper_counter_req *req,
2138                        struct npc_mcam_oper_counter_rsp *rsp)
2139{
2140        struct npc_mcam *mcam = &rvu->hw->mcam;
2141        int blkaddr, err;
2142
2143        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2144        if (blkaddr < 0)
2145                return NPC_MCAM_INVALID_REQ;
2146
2147        mutex_lock(&mcam->lock);
2148        err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2149        mutex_unlock(&mcam->lock);
2150        if (err)
2151                return err;
2152
2153        rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr));
2154        rsp->stat &= BIT_ULL(48) - 1;
2155
2156        return 0;
2157}
2158
2159int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
2160                          struct npc_mcam_alloc_and_write_entry_req *req,
2161                          struct npc_mcam_alloc_and_write_entry_rsp *rsp)
2162{
2163        struct npc_mcam_alloc_counter_req cntr_req;
2164        struct npc_mcam_alloc_counter_rsp cntr_rsp;
2165        struct npc_mcam_alloc_entry_req entry_req;
2166        struct npc_mcam_alloc_entry_rsp entry_rsp;
2167        struct npc_mcam *mcam = &rvu->hw->mcam;
2168        u16 entry = NPC_MCAM_ENTRY_INVALID;
2169        u16 cntr = NPC_MCAM_ENTRY_INVALID;
2170        int blkaddr, rc;
2171
2172        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2173        if (blkaddr < 0)
2174                return NPC_MCAM_INVALID_REQ;
2175
2176        if (req->intf != NIX_INTF_RX && req->intf != NIX_INTF_TX)
2177                return NPC_MCAM_INVALID_REQ;
2178
2179        /* Try to allocate a MCAM entry */
2180        entry_req.hdr.pcifunc = req->hdr.pcifunc;
2181        entry_req.contig = true;
2182        entry_req.priority = req->priority;
2183        entry_req.ref_entry = req->ref_entry;
2184        entry_req.count = 1;
2185
2186        rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu,
2187                                                   &entry_req, &entry_rsp);
2188        if (rc)
2189                return rc;
2190
2191        if (!entry_rsp.count)
2192                return NPC_MCAM_ALLOC_FAILED;
2193
2194        entry = entry_rsp.entry;
2195
2196        if (!req->alloc_cntr)
2197                goto write_entry;
2198
2199        /* Now allocate counter */
2200        cntr_req.hdr.pcifunc = req->hdr.pcifunc;
2201        cntr_req.contig = true;
2202        cntr_req.count = 1;
2203
2204        rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
2205        if (rc) {
2206                /* Free allocated MCAM entry */
2207                mutex_lock(&mcam->lock);
2208                mcam->entry2pfvf_map[entry] = 0;
2209                npc_mcam_clear_bit(mcam, entry);
2210                mutex_unlock(&mcam->lock);
2211                return rc;
2212        }
2213
2214        cntr = cntr_rsp.cntr;
2215
2216write_entry:
2217        mutex_lock(&mcam->lock);
2218        npc_config_mcam_entry(rvu, mcam, blkaddr, entry, req->intf,
2219                              &req->entry_data, req->enable_entry);
2220
2221        if (req->alloc_cntr)
2222                npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr);
2223        mutex_unlock(&mcam->lock);
2224
2225        rsp->entry = entry;
2226        rsp->cntr = cntr;
2227
2228        return 0;
2229}
2230
2231#define GET_KEX_CFG(intf) \
2232        rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
2233
2234#define GET_KEX_FLAGS(ld) \
2235        rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld))
2236
2237#define GET_KEX_LD(intf, lid, lt, ld)   \
2238        rvu_read64(rvu, BLKADDR_NPC,    \
2239                NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld))
2240
2241#define GET_KEX_LDFLAGS(intf, ld, fl)   \
2242        rvu_read64(rvu, BLKADDR_NPC,    \
2243                NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl))
2244
2245int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
2246                                     struct npc_get_kex_cfg_rsp *rsp)
2247{
2248        int lid, lt, ld, fl;
2249
2250        rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX);
2251        rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX);
2252        for (lid = 0; lid < NPC_MAX_LID; lid++) {
2253                for (lt = 0; lt < NPC_MAX_LT; lt++) {
2254                        for (ld = 0; ld < NPC_MAX_LD; ld++) {
2255                                rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] =
2256                                        GET_KEX_LD(NIX_INTF_RX, lid, lt, ld);
2257                                rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] =
2258                                        GET_KEX_LD(NIX_INTF_TX, lid, lt, ld);
2259                        }
2260                }
2261        }
2262        for (ld = 0; ld < NPC_MAX_LD; ld++)
2263                rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld);
2264
2265        for (ld = 0; ld < NPC_MAX_LD; ld++) {
2266                for (fl = 0; fl < NPC_MAX_LFL; fl++) {
2267                        rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] =
2268                                        GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl);
2269                        rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] =
2270                                        GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl);
2271                }
2272        }
2273        memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN);
2274        return 0;
2275}
2276
2277int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf)
2278{
2279        struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
2280        struct npc_mcam *mcam = &rvu->hw->mcam;
2281        int blkaddr, index;
2282        bool enable;
2283
2284        blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2285        if (blkaddr < 0)
2286                return NIX_AF_ERR_AF_LF_INVALID;
2287
2288        if (!pfvf->rxvlan)
2289                return 0;
2290
2291        index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
2292                                         NIXLF_UCAST_ENTRY);
2293        pfvf->entry.action = npc_get_mcam_action(rvu, mcam, blkaddr, index);
2294        enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, index);
2295        npc_config_mcam_entry(rvu, mcam, blkaddr, pfvf->rxvlan_index,
2296                              NIX_INTF_RX, &pfvf->entry, enable);
2297
2298        return 0;
2299}
2300