LXR linux/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c

   1/*
   2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 *
  32 */
  33
  34#ifdef CONFIG_MLX5_FPGA_IPSEC
  35
  36#include <linux/mlx5/device.h>
  37
  38#include "accel/ipsec.h"
  39#include "mlx5_core.h"
  40#include "fpga/ipsec.h"
  41
  42u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev)
  43{
  44        return mlx5_fpga_ipsec_device_caps(mdev);
  45}
  46EXPORT_SYMBOL_GPL(mlx5_accel_ipsec_device_caps);
  47
  48unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev)
  49{
  50        return mlx5_fpga_ipsec_counters_count(mdev);
  51}
  52
  53int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
  54                                   unsigned int count)
  55{
  56        return mlx5_fpga_ipsec_counters_read(mdev, counters, count);
  57}
  58
  59void *mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
  60                                       struct mlx5_accel_esp_xfrm *xfrm,
  61                                       u32 *sa_handle)
  62{
  63        __be32 saddr[4] = {}, daddr[4] = {};
  64
  65        if (!xfrm->attrs.is_ipv6) {
  66                saddr[3] = xfrm->attrs.saddr.a4;
  67                daddr[3] = xfrm->attrs.daddr.a4;
  68        } else {
  69                memcpy(saddr, xfrm->attrs.saddr.a6, sizeof(saddr));
  70                memcpy(daddr, xfrm->attrs.daddr.a6, sizeof(daddr));
  71        }
  72
  73        return mlx5_fpga_ipsec_create_sa_ctx(mdev, xfrm, saddr,
  74                                             daddr, xfrm->attrs.spi,
  75                                             xfrm->attrs.is_ipv6, sa_handle);
  76}
  77
  78void mlx5_accel_esp_free_hw_context(void *context)
  79{
  80        mlx5_fpga_ipsec_delete_sa_ctx(context);
  81}
  82
  83int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
  84{
  85        return mlx5_fpga_ipsec_init(mdev);
  86}
  87
  88void mlx5_accel_ipsec_build_fs_cmds(void)
  89{
  90        mlx5_fpga_ipsec_build_fs_cmds();
  91}
  92
  93void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
  94{
  95        mlx5_fpga_ipsec_cleanup(mdev);
  96}
  97
  98struct mlx5_accel_esp_xfrm *
  99mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
 100                           const struct mlx5_accel_esp_xfrm_attrs *attrs,
 101                           u32 flags)
 102{
 103        struct mlx5_accel_esp_xfrm *xfrm;
 104
 105        xfrm = mlx5_fpga_esp_create_xfrm(mdev, attrs, flags);
 106        if (IS_ERR(xfrm))
 107                return xfrm;
 108
 109        xfrm->mdev = mdev;
 110        return xfrm;
 111}
 112EXPORT_SYMBOL_GPL(mlx5_accel_esp_create_xfrm);
 113
 114void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
 115{
 116        mlx5_fpga_esp_destroy_xfrm(xfrm);
 117}
 118EXPORT_SYMBOL_GPL(mlx5_accel_esp_destroy_xfrm);
 119
 120int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
 121                               const struct mlx5_accel_esp_xfrm_attrs *attrs)
 122{
 123        return mlx5_fpga_esp_modify_xfrm(xfrm, attrs);
 124}
 125EXPORT_SYMBOL_GPL(mlx5_accel_esp_modify_xfrm);
 126
 127#endif
 128