1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33#include <linux/mlx5/driver.h>
34#include <linux/mlx5/eswitch.h>
35#include <linux/module.h>
36#include "mlx5_core.h"
37#include "../../mlxfw/mlxfw.h"
38
39enum {
40 MCQS_IDENTIFIER_BOOT_IMG = 0x1,
41 MCQS_IDENTIFIER_OEM_NVCONFIG = 0x4,
42 MCQS_IDENTIFIER_MLNX_NVCONFIG = 0x5,
43 MCQS_IDENTIFIER_CS_TOKEN = 0x6,
44 MCQS_IDENTIFIER_DBG_TOKEN = 0x7,
45 MCQS_IDENTIFIER_GEARBOX = 0xA,
46};
47
48enum {
49 MCQS_UPDATE_STATE_IDLE,
50 MCQS_UPDATE_STATE_IN_PROGRESS,
51 MCQS_UPDATE_STATE_APPLIED,
52 MCQS_UPDATE_STATE_ACTIVE,
53 MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
54 MCQS_UPDATE_STATE_FAILED,
55 MCQS_UPDATE_STATE_CANCELED,
56 MCQS_UPDATE_STATE_BUSY,
57};
58
59enum {
60 MCQI_INFO_TYPE_CAPABILITIES = 0x0,
61 MCQI_INFO_TYPE_VERSION = 0x1,
62 MCQI_INFO_TYPE_ACTIVATION_METHOD = 0x5,
63};
64
65enum {
66 MCQI_FW_RUNNING_VERSION = 0,
67 MCQI_FW_STORED_VERSION = 1,
68};
69
70int mlx5_query_board_id(struct mlx5_core_dev *dev)
71{
72 u32 *out;
73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
75 int err;
76
77 out = kzalloc(outlen, GFP_KERNEL);
78 if (!out)
79 return -ENOMEM;
80
81 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
82 err = mlx5_cmd_exec_inout(dev, query_adapter, in, out);
83 if (err)
84 goto out;
85
86 memcpy(dev->board_id,
87 MLX5_ADDR_OF(query_adapter_out, out,
88 query_adapter_struct.vsd_contd_psid),
89 MLX5_FLD_SZ_BYTES(query_adapter_out,
90 query_adapter_struct.vsd_contd_psid));
91
92out:
93 kfree(out);
94 return err;
95}
96
97int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
98{
99 u32 *out;
100 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
102 int err;
103
104 out = kzalloc(outlen, GFP_KERNEL);
105 if (!out)
106 return -ENOMEM;
107
108 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
109 err = mlx5_cmd_exec_inout(mdev, query_adapter, in, out);
110 if (err)
111 goto out;
112
113 *vendor_id = MLX5_GET(query_adapter_out, out,
114 query_adapter_struct.ieee_vendor_id);
115out:
116 kfree(out);
117 return err;
118}
119EXPORT_SYMBOL(mlx5_core_query_vendor_id);
120
121static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
122{
123 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
124 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
125 MLX5_PCAM_REGS_5000_TO_507F);
126}
127
128static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
129 enum mlx5_mcam_reg_groups group)
130{
131 return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
132 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
133}
134
135static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
136{
137 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
138 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
139 MLX5_QCAM_REGS_FIRST_128);
140}
141
142int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
143{
144 int err;
145
146 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
147 if (err)
148 return err;
149
150 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
151 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
152 if (err)
153 return err;
154 }
155
156 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
157 err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS);
158 if (err)
159 return err;
160 }
161
162 if (MLX5_CAP_GEN(dev, pg)) {
163 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
164 if (err)
165 return err;
166 }
167
168 if (MLX5_CAP_GEN(dev, atomic)) {
169 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
170 if (err)
171 return err;
172 }
173
174 if (MLX5_CAP_GEN(dev, roce)) {
175 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
176 if (err)
177 return err;
178 }
179
180 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
181 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
182 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
183 if (err)
184 return err;
185 }
186
187 if (MLX5_CAP_GEN(dev, vport_group_manager) &&
188 MLX5_ESWITCH_MANAGER(dev)) {
189 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
190 if (err)
191 return err;
192 }
193
194 if (MLX5_ESWITCH_MANAGER(dev)) {
195 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
196 if (err)
197 return err;
198 }
199
200 if (MLX5_CAP_GEN(dev, vector_calc)) {
201 err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC);
202 if (err)
203 return err;
204 }
205
206 if (MLX5_CAP_GEN(dev, qos)) {
207 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
208 if (err)
209 return err;
210 }
211
212 if (MLX5_CAP_GEN(dev, debug))
213 mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
214
215 if (MLX5_CAP_GEN(dev, pcam_reg))
216 mlx5_get_pcam_reg(dev);
217
218 if (MLX5_CAP_GEN(dev, mcam_reg)) {
219 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
220 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF);
221 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
222 }
223
224 if (MLX5_CAP_GEN(dev, qcam_reg))
225 mlx5_get_qcam_reg(dev);
226
227 if (MLX5_CAP_GEN(dev, device_memory)) {
228 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_MEM);
229 if (err)
230 return err;
231 }
232
233 if (MLX5_CAP_GEN(dev, event_cap)) {
234 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_EVENT);
235 if (err)
236 return err;
237 }
238
239 if (MLX5_CAP_GEN(dev, tls_tx)) {
240 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
241 if (err)
242 return err;
243 }
244
245 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
246 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
247 err = mlx5_core_get_caps(dev, MLX5_CAP_VDPA_EMULATION);
248 if (err)
249 return err;
250 }
251
252 return 0;
253}
254
255int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
256{
257 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {};
258 int i;
259
260 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
261
262 if (MLX5_CAP_GEN(dev, sw_owner_id)) {
263 for (i = 0; i < 4; i++)
264 MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
265 sw_owner_id[i]);
266 }
267
268 return mlx5_cmd_exec_in(dev, init_hca, in);
269}
270
271int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
272{
273 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
274
275 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
276 return mlx5_cmd_exec_in(dev, teardown_hca, in);
277}
278
279int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
280{
281 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
282 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
283 int force_state;
284 int ret;
285
286 if (!MLX5_CAP_GEN(dev, force_teardown)) {
287 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
288 return -EOPNOTSUPP;
289 }
290
291 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
292 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
293
294 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
295 if (ret)
296 return ret;
297
298 force_state = MLX5_GET(teardown_hca_out, out, state);
299 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
300 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
301 return -EIO;
302 }
303
304 return 0;
305}
306
307#define MLX5_FAST_TEARDOWN_WAIT_MS 3000
308int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
309{
310 unsigned long end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
311 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
312 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
313 int state;
314 int ret;
315
316 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
317 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
318 return -EOPNOTSUPP;
319 }
320
321 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
322 MLX5_SET(teardown_hca_in, in, profile,
323 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
324
325 ret = mlx5_cmd_exec_inout(dev, teardown_hca, in, out);
326 if (ret)
327 return ret;
328
329 state = MLX5_GET(teardown_hca_out, out, state);
330 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
331 mlx5_core_warn(dev, "teardown with fast mode failed\n");
332 return -EIO;
333 }
334
335 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
336
337
338 end = jiffies + msecs_to_jiffies(delay_ms);
339 do {
340 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
341 break;
342
343 cond_resched();
344 } while (!time_after(jiffies, end));
345
346 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
347 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
348 mlx5_get_nic_state(dev), delay_ms);
349 return -EIO;
350 }
351
352 return 0;
353}
354
355enum mlxsw_reg_mcc_instruction {
356 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
357 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
358 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
359 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
360 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
361 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
362};
363
364static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
365 enum mlxsw_reg_mcc_instruction instr,
366 u16 component_index, u32 update_handle,
367 u32 component_size)
368{
369 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
370 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
371
372 memset(in, 0, sizeof(in));
373
374 MLX5_SET(mcc_reg, in, instruction, instr);
375 MLX5_SET(mcc_reg, in, component_index, component_index);
376 MLX5_SET(mcc_reg, in, update_handle, update_handle);
377 MLX5_SET(mcc_reg, in, component_size, component_size);
378
379 return mlx5_core_access_reg(dev, in, sizeof(in), out,
380 sizeof(out), MLX5_REG_MCC, 0, 1);
381}
382
383static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
384 u32 *update_handle, u8 *error_code,
385 u8 *control_state)
386{
387 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
388 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
389 int err;
390
391 memset(in, 0, sizeof(in));
392 memset(out, 0, sizeof(out));
393 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
394
395 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
396 sizeof(out), MLX5_REG_MCC, 0, 0);
397 if (err)
398 goto out;
399
400 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
401 *error_code = MLX5_GET(mcc_reg, out, error_code);
402 *control_state = MLX5_GET(mcc_reg, out, control_state);
403
404out:
405 return err;
406}
407
408static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
409 u32 update_handle,
410 u32 offset, u16 size,
411 u8 *data)
412{
413 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
414 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
415 int i, j, dw_size = size >> 2;
416 __be32 data_element;
417 u32 *in;
418
419 in = kzalloc(in_size, GFP_KERNEL);
420 if (!in)
421 return -ENOMEM;
422
423 MLX5_SET(mcda_reg, in, update_handle, update_handle);
424 MLX5_SET(mcda_reg, in, offset, offset);
425 MLX5_SET(mcda_reg, in, size, size);
426
427 for (i = 0; i < dw_size; i++) {
428 j = i * 4;
429 data_element = htonl(*(u32 *)&data[j]);
430 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
431 }
432
433 err = mlx5_core_access_reg(dev, in, in_size, out,
434 sizeof(out), MLX5_REG_MCDA, 0, 1);
435 kfree(in);
436 return err;
437}
438
439static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
440 u16 component_index, bool read_pending,
441 u8 info_type, u16 data_size, void *mcqi_data)
442{
443 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
444 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
445 void *data;
446 int err;
447
448 MLX5_SET(mcqi_reg, in, component_index, component_index);
449 MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
450 MLX5_SET(mcqi_reg, in, info_type, info_type);
451 MLX5_SET(mcqi_reg, in, data_size, data_size);
452
453 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
454 MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
455 MLX5_REG_MCQI, 0, 0);
456 if (err)
457 return err;
458
459 data = MLX5_ADDR_OF(mcqi_reg, out, data);
460 memcpy(mcqi_data, data, data_size);
461
462 return 0;
463}
464
465static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
466 u32 *max_component_size, u8 *log_mcda_word_size,
467 u16 *mcda_max_write_size)
468{
469 u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
470 int err;
471
472 err = mlx5_reg_mcqi_query(dev, component_index, 0,
473 MCQI_INFO_TYPE_CAPABILITIES,
474 MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
475 if (err)
476 return err;
477
478 *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
479 *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
480 *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
481
482 return 0;
483}
484
485struct mlx5_mlxfw_dev {
486 struct mlxfw_dev mlxfw_dev;
487 struct mlx5_core_dev *mlx5_core_dev;
488};
489
490static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
491 u16 component_index, u32 *p_max_size,
492 u8 *p_align_bits, u16 *p_max_write_size)
493{
494 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
495 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
496 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
497
498 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
499 mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
500 return -EOPNOTSUPP;
501 }
502
503 return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
504 p_align_bits, p_max_write_size);
505}
506
507static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
508{
509 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
510 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
511 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
512 u8 control_state, error_code;
513 int err;
514
515 *fwhandle = 0;
516 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
517 if (err)
518 return err;
519
520 if (control_state != MLXFW_FSM_STATE_IDLE)
521 return -EBUSY;
522
523 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
524 0, *fwhandle, 0);
525}
526
527static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
528 u16 component_index, u32 component_size)
529{
530 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
531 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
532 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
533
534 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
535 component_index, fwhandle, component_size);
536}
537
538static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
539 u8 *data, u16 size, u32 offset)
540{
541 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
542 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
543 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
544
545 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
546}
547
548static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
549 u16 component_index)
550{
551 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
552 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
553 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
554
555 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
556 component_index, fwhandle, 0);
557}
558
559static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
560{
561 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
562 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
563 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
564
565 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
566 fwhandle, 0);
567}
568
569static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
570 enum mlxfw_fsm_state *fsm_state,
571 enum mlxfw_fsm_state_err *fsm_state_err)
572{
573 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
574 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
575 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
576 u8 control_state, error_code;
577 int err;
578
579 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
580 if (err)
581 return err;
582
583 *fsm_state = control_state;
584 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
585 MLXFW_FSM_STATE_ERR_MAX);
586 return 0;
587}
588
589static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
590{
591 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
592 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
593 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
594
595 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
596}
597
598static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
599{
600 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
601 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
602 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
603
604 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
605 fwhandle, 0);
606}
607
608#define MLX5_FSM_REACTIVATE_TOUT 5000
609static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status)
610{
611 unsigned long exp_time = jiffies + msecs_to_jiffies(MLX5_FSM_REACTIVATE_TOUT);
612 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
613 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
614 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
615 u32 out[MLX5_ST_SZ_DW(mirc_reg)];
616 u32 in[MLX5_ST_SZ_DW(mirc_reg)];
617 int err;
618
619 if (!MLX5_CAP_MCAM_REG2(dev, mirc))
620 return -EOPNOTSUPP;
621
622 memset(in, 0, sizeof(in));
623
624 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
625 sizeof(out), MLX5_REG_MIRC, 0, 1);
626 if (err)
627 return err;
628
629 do {
630 memset(out, 0, sizeof(out));
631 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
632 sizeof(out), MLX5_REG_MIRC, 0, 0);
633 if (err)
634 return err;
635
636 *status = MLX5_GET(mirc_reg, out, status_code);
637 if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY)
638 return 0;
639
640 msleep(20);
641 } while (time_before(jiffies, exp_time));
642
643 return 0;
644}
645
646static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
647 .component_query = mlx5_component_query,
648 .fsm_lock = mlx5_fsm_lock,
649 .fsm_component_update = mlx5_fsm_component_update,
650 .fsm_block_download = mlx5_fsm_block_download,
651 .fsm_component_verify = mlx5_fsm_component_verify,
652 .fsm_activate = mlx5_fsm_activate,
653 .fsm_reactivate = mlx5_fsm_reactivate,
654 .fsm_query_state = mlx5_fsm_query_state,
655 .fsm_cancel = mlx5_fsm_cancel,
656 .fsm_release = mlx5_fsm_release
657};
658
659int mlx5_firmware_flash(struct mlx5_core_dev *dev,
660 const struct firmware *firmware,
661 struct netlink_ext_ack *extack)
662{
663 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
664 .mlxfw_dev = {
665 .ops = &mlx5_mlxfw_dev_ops,
666 .psid = dev->board_id,
667 .psid_size = strlen(dev->board_id),
668 .devlink = priv_to_devlink(dev),
669 },
670 .mlx5_core_dev = dev
671 };
672
673 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
674 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
675 !MLX5_CAP_MCAM_REG(dev, mcc) ||
676 !MLX5_CAP_MCAM_REG(dev, mcda)) {
677 pr_info("%s flashing isn't supported by the running FW\n", __func__);
678 return -EOPNOTSUPP;
679 }
680
681 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
682 firmware, extack);
683}
684
685static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
686 u16 component_index, bool read_pending,
687 u32 *mcqi_version_out)
688{
689 return mlx5_reg_mcqi_query(dev, component_index, read_pending,
690 MCQI_INFO_TYPE_VERSION,
691 MLX5_ST_SZ_BYTES(mcqi_version),
692 mcqi_version_out);
693}
694
695static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
696 u16 component_index)
697{
698 u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
699 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
700 int err;
701
702 memset(out, 0, out_sz);
703
704 MLX5_SET(mcqs_reg, in, component_index, component_index);
705
706 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
707 out_sz, MLX5_REG_MCQS, 0, 0);
708 return err;
709}
710
711
712static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
713{
714 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
715 u16 identifier, component_idx = 0;
716 bool quit;
717 int err;
718
719 do {
720 err = mlx5_reg_mcqs_query(dev, out, component_idx);
721 if (err)
722 return err;
723
724 identifier = MLX5_GET(mcqs_reg, out, identifier);
725 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
726 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
727 } while (!quit && ++component_idx);
728
729 if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
730 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
731 component_idx);
732 return -EOPNOTSUPP;
733 }
734
735 return component_idx;
736}
737
738static int
739mlx5_fw_image_pending(struct mlx5_core_dev *dev,
740 int component_index,
741 bool *pending_version_exists)
742{
743 u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
744 u8 component_update_state;
745 int err;
746
747 err = mlx5_reg_mcqs_query(dev, out, component_index);
748 if (err)
749 return err;
750
751 component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
752
753 if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
754 *pending_version_exists = false;
755 } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
756 *pending_version_exists = true;
757 } else {
758 mlx5_core_warn(dev,
759 "mcqs: can't read pending fw version while fw state is %d\n",
760 component_update_state);
761 return -ENODATA;
762 }
763 return 0;
764}
765
766int mlx5_fw_version_query(struct mlx5_core_dev *dev,
767 u32 *running_ver, u32 *pending_ver)
768{
769 u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
770 bool pending_version_exists;
771 int component_index;
772 int err;
773
774 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
775 !MLX5_CAP_MCAM_REG(dev, mcqs)) {
776 mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
777 return -EOPNOTSUPP;
778 }
779
780 component_index = mlx5_get_boot_img_component_index(dev);
781 if (component_index < 0)
782 return component_index;
783
784 err = mlx5_reg_mcqi_version_query(dev, component_index,
785 MCQI_FW_RUNNING_VERSION,
786 reg_mcqi_version);
787 if (err)
788 return err;
789
790 *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
791
792 err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
793 if (err)
794 return err;
795
796 if (!pending_version_exists) {
797 *pending_ver = 0;
798 return 0;
799 }
800
801 err = mlx5_reg_mcqi_version_query(dev, component_index,
802 MCQI_FW_STORED_VERSION,
803 reg_mcqi_version);
804 if (err)
805 return err;
806
807 *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
808
809 return 0;
810}
811
