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9#include <linux/device.h>
10#include <linux/errno.h>
11#include <linux/etherdevice.h>
12#include <linux/ethtool.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/netdevice.h>
17#include <linux/regmap.h>
18#include <linux/skbuff.h>
19#include <linux/spi/spi.h>
20
21#include "encx24j600_hw.h"
22
23#define DRV_NAME "encx24j600"
24#define DRV_VERSION "1.0"
25
26#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
27static int debug = -1;
28module_param(debug, int, 0000);
29MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
30
31
32
33
34
35
36#define ENC_TX_BUF_START 0x0000U
37#define ENC_RX_BUF_START 0x0600U
38#define ENC_RX_BUF_END 0x5fffU
39#define ENC_SRAM_SIZE 0x6000U
40
41enum {
42 RXFILTER_NORMAL,
43 RXFILTER_MULTI,
44 RXFILTER_PROMISC
45};
46
47struct encx24j600_priv {
48 struct net_device *ndev;
49 struct mutex lock;
50 struct encx24j600_context ctx;
51 struct sk_buff *tx_skb;
52 struct task_struct *kworker_task;
53 struct kthread_worker kworker;
54 struct kthread_work tx_work;
55 struct kthread_work setrx_work;
56 u16 next_packet;
57 bool hw_enabled;
58 bool full_duplex;
59 bool autoneg;
60 u16 speed;
61 int rxfilter;
62 u32 msg_enable;
63};
64
65static void dump_packet(const char *msg, int len, const char *data)
66{
67 pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len);
68 print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len);
69}
70
71static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
72 struct rsv *rsv)
73{
74 struct net_device *dev = priv->ndev;
75
76 netdev_info(dev, "RX packet Len:%d\n", rsv->len);
77 netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg,
78 rsv->next_packet);
79 netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n",
80 RSV_GETBIT(rsv->rxstat, RSV_RXOK),
81 RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE));
82 netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
83 RSV_GETBIT(rsv->rxstat, RSV_CRCERROR),
84 RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR),
85 RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE));
86 netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
87 RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST),
88 RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST),
89 RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV),
90 RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV));
91 netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
92 RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME),
93 RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME),
94 RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE),
95 RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN));
96}
97
98static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
99{
100 struct net_device *dev = priv->ndev;
101 unsigned int val = 0;
102 int ret = regmap_read(priv->ctx.regmap, reg, &val);
103
104 if (unlikely(ret))
105 netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
106 __func__, ret, reg);
107 return val;
108}
109
110static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
111{
112 struct net_device *dev = priv->ndev;
113 int ret = regmap_write(priv->ctx.regmap, reg, val);
114
115 if (unlikely(ret))
116 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
117 __func__, ret, reg, val);
118}
119
120static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
121 u16 mask, u16 val)
122{
123 struct net_device *dev = priv->ndev;
124 int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
125
126 if (unlikely(ret))
127 netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
128 __func__, ret, reg, val, mask);
129}
130
131static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
132{
133 struct net_device *dev = priv->ndev;
134 unsigned int val = 0;
135 int ret = regmap_read(priv->ctx.phymap, reg, &val);
136
137 if (unlikely(ret))
138 netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
139 __func__, ret, reg);
140 return val;
141}
142
143static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
144{
145 struct net_device *dev = priv->ndev;
146 int ret = regmap_write(priv->ctx.phymap, reg, val);
147
148 if (unlikely(ret))
149 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
150 __func__, ret, reg, val);
151}
152
153static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
154{
155 encx24j600_update_reg(priv, reg, mask, 0);
156}
157
158static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
159{
160 encx24j600_update_reg(priv, reg, mask, mask);
161}
162
163static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
164{
165 struct net_device *dev = priv->ndev;
166 int ret = regmap_write(priv->ctx.regmap, cmd, 0);
167
168 if (unlikely(ret))
169 netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
170 __func__, ret, cmd);
171}
172
173static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
174 size_t count)
175{
176 int ret;
177
178 mutex_lock(&priv->ctx.mutex);
179 ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
180 mutex_unlock(&priv->ctx.mutex);
181
182 return ret;
183}
184
185static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
186 const u8 *data, size_t count)
187{
188 int ret;
189
190 mutex_lock(&priv->ctx.mutex);
191 ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
192 mutex_unlock(&priv->ctx.mutex);
193
194 return ret;
195}
196
197static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
198{
199 u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
200
201 if (priv->autoneg == AUTONEG_ENABLE) {
202 phcon1 |= ANEN | RENEG;
203 } else {
204 phcon1 &= ~ANEN;
205 if (priv->speed == SPEED_100)
206 phcon1 |= SPD100;
207 else
208 phcon1 &= ~SPD100;
209
210 if (priv->full_duplex)
211 phcon1 |= PFULDPX;
212 else
213 phcon1 &= ~PFULDPX;
214 }
215 encx24j600_write_phy(priv, PHCON1, phcon1);
216}
217
218
219static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
220{
221 struct net_device *dev = priv->ndev;
222 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
223 u16 phstat1;
224 u16 estat;
225 int ret = 0;
226
227 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
228 while ((phstat1 & ANDONE) == 0) {
229 if (time_after(jiffies, timeout)) {
230 u16 phstat3;
231
232 netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
233
234 priv->autoneg = AUTONEG_DISABLE;
235 phstat3 = encx24j600_read_phy(priv, PHSTAT3);
236 priv->speed = (phstat3 & PHY3SPD100)
237 ? SPEED_100 : SPEED_10;
238 priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
239 encx24j600_update_phcon1(priv);
240 netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
241 priv->speed == SPEED_100 ? "100" : "10",
242 priv->full_duplex ? "Full" : "Half");
243
244 return -ETIMEDOUT;
245 }
246 cpu_relax();
247 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
248 }
249
250 estat = encx24j600_read_reg(priv, ESTAT);
251 if (estat & PHYDPX) {
252 encx24j600_set_bits(priv, MACON2, FULDPX);
253 encx24j600_write_reg(priv, MABBIPG, 0x15);
254 } else {
255 encx24j600_clr_bits(priv, MACON2, FULDPX);
256 encx24j600_write_reg(priv, MABBIPG, 0x12);
257
258 encx24j600_write_reg(priv, MACLCON, 0x370f);
259 }
260
261 return ret;
262}
263
264
265static void encx24j600_check_link_status(struct encx24j600_priv *priv)
266{
267 struct net_device *dev = priv->ndev;
268 u16 estat;
269
270 estat = encx24j600_read_reg(priv, ESTAT);
271
272 if (estat & PHYLNK) {
273 if (priv->autoneg == AUTONEG_ENABLE)
274 encx24j600_wait_for_autoneg(priv);
275
276 netif_carrier_on(dev);
277 netif_info(priv, ifup, dev, "link up\n");
278 } else {
279 netif_info(priv, ifdown, dev, "link down\n");
280
281
282
283
284 priv->autoneg = AUTONEG_ENABLE;
285 priv->full_duplex = true;
286 priv->speed = SPEED_100;
287 netif_carrier_off(dev);
288 }
289}
290
291static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
292{
293 struct net_device *dev = priv->ndev;
294
295 netif_dbg(priv, intr, dev, "%s", __func__);
296 encx24j600_check_link_status(priv);
297 encx24j600_clr_bits(priv, EIR, LINKIF);
298}
299
300static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
301{
302 struct net_device *dev = priv->ndev;
303
304 if (!priv->tx_skb) {
305 BUG();
306 return;
307 }
308
309 mutex_lock(&priv->lock);
310
311 if (err)
312 dev->stats.tx_errors++;
313 else
314 dev->stats.tx_packets++;
315
316 dev->stats.tx_bytes += priv->tx_skb->len;
317
318 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
319
320 netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
321
322 dev_kfree_skb(priv->tx_skb);
323 priv->tx_skb = NULL;
324
325 netif_wake_queue(dev);
326
327 mutex_unlock(&priv->lock);
328}
329
330static int encx24j600_receive_packet(struct encx24j600_priv *priv,
331 struct rsv *rsv)
332{
333 struct net_device *dev = priv->ndev;
334 struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN);
335
336 if (!skb) {
337 pr_err_ratelimited("RX: OOM: packet dropped\n");
338 dev->stats.rx_dropped++;
339 return -ENOMEM;
340 }
341 skb_reserve(skb, NET_IP_ALIGN);
342 encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
343
344 if (netif_msg_pktdata(priv))
345 dump_packet("RX", skb->len, skb->data);
346
347 skb->dev = dev;
348 skb->protocol = eth_type_trans(skb, dev);
349 skb->ip_summed = CHECKSUM_COMPLETE;
350
351
352 dev->stats.rx_packets++;
353 dev->stats.rx_bytes += rsv->len;
354
355 netif_rx(skb);
356
357 return 0;
358}
359
360static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
361{
362 struct net_device *dev = priv->ndev;
363
364 while (packet_count--) {
365 struct rsv rsv;
366 u16 newrxtail;
367
368 encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
369 encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
370
371 if (netif_msg_rx_status(priv))
372 encx24j600_dump_rsv(priv, __func__, &rsv);
373
374 if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) ||
375 (rsv.len > MAX_FRAMELEN)) {
376 netif_err(priv, rx_err, dev, "RX Error %04x\n",
377 rsv.rxstat);
378 dev->stats.rx_errors++;
379
380 if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR))
381 dev->stats.rx_crc_errors++;
382 if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR))
383 dev->stats.rx_frame_errors++;
384 if (rsv.len > MAX_FRAMELEN)
385 dev->stats.rx_over_errors++;
386 } else {
387 encx24j600_receive_packet(priv, &rsv);
388 }
389
390 priv->next_packet = rsv.next_packet;
391
392 newrxtail = priv->next_packet - 2;
393 if (newrxtail == ENC_RX_BUF_START)
394 newrxtail = SRAM_SIZE - 2;
395
396 encx24j600_cmd(priv, SETPKTDEC);
397 encx24j600_write_reg(priv, ERXTAIL, newrxtail);
398 }
399}
400
401static irqreturn_t encx24j600_isr(int irq, void *dev_id)
402{
403 struct encx24j600_priv *priv = dev_id;
404 struct net_device *dev = priv->ndev;
405 int eir;
406
407
408 encx24j600_cmd(priv, CLREIE);
409
410 eir = encx24j600_read_reg(priv, EIR);
411
412 if (eir & LINKIF)
413 encx24j600_int_link_handler(priv);
414
415 if (eir & TXIF)
416 encx24j600_tx_complete(priv, false);
417
418 if (eir & TXABTIF)
419 encx24j600_tx_complete(priv, true);
420
421 if (eir & RXABTIF) {
422 if (eir & PCFULIF) {
423
424 netif_err(priv, rx_err, dev, "Packet counter full\n");
425 }
426 dev->stats.rx_dropped++;
427 encx24j600_clr_bits(priv, EIR, RXABTIF);
428 }
429
430 if (eir & PKTIF) {
431 u8 packet_count;
432
433 mutex_lock(&priv->lock);
434
435 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
436 while (packet_count) {
437 encx24j600_rx_packets(priv, packet_count);
438 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
439 }
440
441 mutex_unlock(&priv->lock);
442 }
443
444
445 encx24j600_cmd(priv, SETEIE);
446
447 return IRQ_HANDLED;
448}
449
450static int encx24j600_soft_reset(struct encx24j600_priv *priv)
451{
452 int ret = 0;
453 int timeout;
454 u16 eudast;
455
456
457 regcache_cache_bypass(priv->ctx.regmap, true);
458 timeout = 10;
459 do {
460 encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
461 eudast = encx24j600_read_reg(priv, EUDAST);
462 usleep_range(25, 100);
463 } while ((eudast != EUDAST_TEST_VAL) && --timeout);
464 regcache_cache_bypass(priv->ctx.regmap, false);
465
466 if (timeout == 0) {
467 ret = -ETIMEDOUT;
468 goto err_out;
469 }
470
471
472 timeout = 10;
473 while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
474 usleep_range(25, 100);
475
476 if (timeout == 0) {
477 ret = -ETIMEDOUT;
478 goto err_out;
479 }
480
481
482 encx24j600_cmd(priv, SETETHRST);
483 usleep_range(25, 100);
484
485
486 if (encx24j600_read_reg(priv, EUDAST) != 0) {
487 ret = -EINVAL;
488 goto err_out;
489 }
490
491
492 usleep_range(256, 1000);
493
494err_out:
495 return ret;
496}
497
498static int encx24j600_hw_reset(struct encx24j600_priv *priv)
499{
500 int ret;
501
502 mutex_lock(&priv->lock);
503 ret = encx24j600_soft_reset(priv);
504 mutex_unlock(&priv->lock);
505
506 return ret;
507}
508
509static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
510{
511 encx24j600_set_bits(priv, ECON2, TXRST);
512 encx24j600_clr_bits(priv, ECON2, TXRST);
513}
514
515static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
516{
517
518 encx24j600_reset_hw_tx(priv);
519
520
521 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
522
523
524 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
525}
526
527static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
528{
529 encx24j600_cmd(priv, DISABLERX);
530
531
532 encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
533
534
535 encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
536
537 priv->next_packet = ENC_RX_BUF_START;
538
539
540 encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
541
542
543 encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
544 encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
545
546
547 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
548}
549
550static void encx24j600_dump_config(struct encx24j600_priv *priv,
551 const char *msg)
552{
553 pr_info(DRV_NAME ": %s\n", msg);
554
555
556 pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1));
557 pr_info(DRV_NAME " ECON2: %04X\n", encx24j600_read_reg(priv, ECON2));
558 pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
559 ERXFCON));
560 pr_info(DRV_NAME " ESTAT: %04X\n", encx24j600_read_reg(priv, ESTAT));
561 pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR));
562 pr_info(DRV_NAME " EIDLED: %04X\n", encx24j600_read_reg(priv, EIDLED));
563
564
565 pr_info(DRV_NAME " MACON1: %04X\n", encx24j600_read_reg(priv, MACON1));
566 pr_info(DRV_NAME " MACON2: %04X\n", encx24j600_read_reg(priv, MACON2));
567 pr_info(DRV_NAME " MAIPG: %04X\n", encx24j600_read_reg(priv, MAIPG));
568 pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
569 MACLCON));
570 pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
571 MABBIPG));
572
573
574 pr_info(DRV_NAME " PHCON1: %04X\n", encx24j600_read_phy(priv, PHCON1));
575 pr_info(DRV_NAME " PHCON2: %04X\n", encx24j600_read_phy(priv, PHCON2));
576 pr_info(DRV_NAME " PHANA: %04X\n", encx24j600_read_phy(priv, PHANA));
577 pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
578 PHANLPA));
579 pr_info(DRV_NAME " PHANE: %04X\n", encx24j600_read_phy(priv, PHANE));
580 pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
581 PHSTAT1));
582 pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
583 PHSTAT2));
584 pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
585 PHSTAT3));
586}
587
588static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
589{
590 switch (priv->rxfilter) {
591 case RXFILTER_PROMISC:
592 encx24j600_set_bits(priv, MACON1, PASSALL);
593 encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
594 break;
595 case RXFILTER_MULTI:
596 encx24j600_clr_bits(priv, MACON1, PASSALL);
597 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
598 break;
599 case RXFILTER_NORMAL:
600 default:
601 encx24j600_clr_bits(priv, MACON1, PASSALL);
602 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
603 break;
604 }
605}
606
607static void encx24j600_hw_init(struct encx24j600_priv *priv)
608{
609 u16 macon2;
610
611 priv->hw_enabled = false;
612
613
614
615
616
617 encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00);
618
619
620 encx24j600_write_reg(priv, MACON1, 0x9);
621
622
623 encx24j600_write_reg(priv, MAIPG, 0x0c12);
624
625
626 encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
627
628 encx24j600_update_phcon1(priv);
629 encx24j600_check_link_status(priv);
630
631 macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER;
632 if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
633 macon2 |= FULDPX;
634
635 encx24j600_set_bits(priv, MACON2, macon2);
636
637 priv->rxfilter = RXFILTER_NORMAL;
638 encx24j600_set_rxfilter_mode(priv);
639
640
641 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
642
643
644 encx24j600_hw_init_tx(priv);
645
646
647 encx24j600_hw_init_rx(priv);
648
649 if (netif_msg_hw(priv))
650 encx24j600_dump_config(priv, "Hw is initialized");
651}
652
653static void encx24j600_hw_enable(struct encx24j600_priv *priv)
654{
655
656 encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
657 PKTIF | LINKIF));
658
659
660 encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
661 PKTIE | LINKIE | INTIE));
662
663
664 encx24j600_cmd(priv, ENABLERX);
665
666 priv->hw_enabled = true;
667}
668
669static void encx24j600_hw_disable(struct encx24j600_priv *priv)
670{
671
672 encx24j600_write_reg(priv, EIE, 0);
673
674
675 encx24j600_cmd(priv, DISABLERX);
676
677 priv->hw_enabled = false;
678}
679
680static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed,
681 u8 duplex)
682{
683 struct encx24j600_priv *priv = netdev_priv(dev);
684 int ret = 0;
685
686 if (!priv->hw_enabled) {
687
688
689
690 if (speed == SPEED_10 || speed == SPEED_100) {
691 priv->autoneg = (autoneg == AUTONEG_ENABLE);
692 priv->full_duplex = (duplex == DUPLEX_FULL);
693 priv->speed = (speed == SPEED_100);
694 } else {
695 netif_warn(priv, link, dev, "unsupported link speed setting\n");
696
697
698 ret = -EOPNOTSUPP;
699 }
700 } else {
701 netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
702 ret = -EBUSY;
703 }
704 return ret;
705}
706
707static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
708 unsigned char *ethaddr)
709{
710 unsigned short val;
711
712 val = encx24j600_read_reg(priv, MAADR1);
713
714 ethaddr[0] = val & 0x00ff;
715 ethaddr[1] = (val & 0xff00) >> 8;
716
717 val = encx24j600_read_reg(priv, MAADR2);
718
719 ethaddr[2] = val & 0x00ffU;
720 ethaddr[3] = (val & 0xff00U) >> 8;
721
722 val = encx24j600_read_reg(priv, MAADR3);
723
724 ethaddr[4] = val & 0x00ffU;
725 ethaddr[5] = (val & 0xff00U) >> 8;
726}
727
728
729static int encx24j600_set_hw_macaddr(struct net_device *dev)
730{
731 struct encx24j600_priv *priv = netdev_priv(dev);
732
733 if (priv->hw_enabled) {
734 netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
735 return -EBUSY;
736 }
737
738 mutex_lock(&priv->lock);
739
740 netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
741 dev->name, dev->dev_addr);
742
743 encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
744 dev->dev_addr[5] << 8));
745 encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
746 dev->dev_addr[3] << 8));
747 encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
748 dev->dev_addr[1] << 8));
749
750 mutex_unlock(&priv->lock);
751
752 return 0;
753}
754
755
756static int encx24j600_set_mac_address(struct net_device *dev, void *addr)
757{
758 struct sockaddr *address = addr;
759
760 if (netif_running(dev))
761 return -EBUSY;
762 if (!is_valid_ether_addr(address->sa_data))
763 return -EADDRNOTAVAIL;
764
765 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
766 return encx24j600_set_hw_macaddr(dev);
767}
768
769static int encx24j600_open(struct net_device *dev)
770{
771 struct encx24j600_priv *priv = netdev_priv(dev);
772
773 int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
774 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
775 DRV_NAME, priv);
776 if (unlikely(ret < 0)) {
777 netdev_err(dev, "request irq %d failed (ret = %d)\n",
778 priv->ctx.spi->irq, ret);
779 return ret;
780 }
781
782 encx24j600_hw_disable(priv);
783 encx24j600_hw_init(priv);
784 encx24j600_hw_enable(priv);
785 netif_start_queue(dev);
786
787 return 0;
788}
789
790static int encx24j600_stop(struct net_device *dev)
791{
792 struct encx24j600_priv *priv = netdev_priv(dev);
793
794 netif_stop_queue(dev);
795 free_irq(priv->ctx.spi->irq, priv);
796 return 0;
797}
798
799static void encx24j600_setrx_proc(struct kthread_work *ws)
800{
801 struct encx24j600_priv *priv =
802 container_of(ws, struct encx24j600_priv, setrx_work);
803
804 mutex_lock(&priv->lock);
805 encx24j600_set_rxfilter_mode(priv);
806 mutex_unlock(&priv->lock);
807}
808
809static void encx24j600_set_multicast_list(struct net_device *dev)
810{
811 struct encx24j600_priv *priv = netdev_priv(dev);
812 int oldfilter = priv->rxfilter;
813
814 if (dev->flags & IFF_PROMISC) {
815 netif_dbg(priv, link, dev, "promiscuous mode\n");
816 priv->rxfilter = RXFILTER_PROMISC;
817 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
818 netif_dbg(priv, link, dev, "%smulticast mode\n",
819 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
820 priv->rxfilter = RXFILTER_MULTI;
821 } else {
822 netif_dbg(priv, link, dev, "normal mode\n");
823 priv->rxfilter = RXFILTER_NORMAL;
824 }
825
826 if (oldfilter != priv->rxfilter)
827 kthread_queue_work(&priv->kworker, &priv->setrx_work);
828}
829
830static void encx24j600_hw_tx(struct encx24j600_priv *priv)
831{
832 struct net_device *dev = priv->ndev;
833
834 netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
835 priv->tx_skb->len);
836
837 if (netif_msg_pktdata(priv))
838 dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
839
840 if (encx24j600_read_reg(priv, EIR) & TXABTIF)
841
842 encx24j600_reset_hw_tx(priv);
843
844
845 encx24j600_clr_bits(priv, EIR, TXIF);
846
847
848 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
849
850
851 encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
852 priv->tx_skb->len);
853
854
855 encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
856
857
858 encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
859
860
861 encx24j600_cmd(priv, SETTXRTS);
862}
863
864static void encx24j600_tx_proc(struct kthread_work *ws)
865{
866 struct encx24j600_priv *priv =
867 container_of(ws, struct encx24j600_priv, tx_work);
868
869 mutex_lock(&priv->lock);
870 encx24j600_hw_tx(priv);
871 mutex_unlock(&priv->lock);
872}
873
874static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev)
875{
876 struct encx24j600_priv *priv = netdev_priv(dev);
877
878 netif_stop_queue(dev);
879
880
881 netif_trans_update(dev);
882
883
884 priv->tx_skb = skb;
885
886 kthread_queue_work(&priv->kworker, &priv->tx_work);
887
888 return NETDEV_TX_OK;
889}
890
891
892static void encx24j600_tx_timeout(struct net_device *dev, unsigned int txqueue)
893{
894 struct encx24j600_priv *priv = netdev_priv(dev);
895
896 netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
897 jiffies, jiffies - dev_trans_start(dev));
898
899 dev->stats.tx_errors++;
900 netif_wake_queue(dev);
901}
902
903static int encx24j600_get_regs_len(struct net_device *dev)
904{
905 return SFR_REG_COUNT;
906}
907
908static void encx24j600_get_regs(struct net_device *dev,
909 struct ethtool_regs *regs, void *p)
910{
911 struct encx24j600_priv *priv = netdev_priv(dev);
912 u16 *buff = p;
913 u8 reg;
914
915 regs->version = 1;
916 mutex_lock(&priv->lock);
917 for (reg = 0; reg < SFR_REG_COUNT; reg += 2) {
918 unsigned int val = 0;
919
920 regmap_read(priv->ctx.regmap, reg, &val);
921 buff[reg] = val & 0xffff;
922 }
923 mutex_unlock(&priv->lock);
924}
925
926static void encx24j600_get_drvinfo(struct net_device *dev,
927 struct ethtool_drvinfo *info)
928{
929 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
930 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
931 strlcpy(info->bus_info, dev_name(dev->dev.parent),
932 sizeof(info->bus_info));
933}
934
935static int encx24j600_get_link_ksettings(struct net_device *dev,
936 struct ethtool_link_ksettings *cmd)
937{
938 struct encx24j600_priv *priv = netdev_priv(dev);
939 u32 supported;
940
941 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
942 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
943 SUPPORTED_Autoneg | SUPPORTED_TP;
944
945 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
946 supported);
947
948 cmd->base.speed = priv->speed;
949 cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
950 cmd->base.port = PORT_TP;
951 cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
952
953 return 0;
954}
955
956static int
957encx24j600_set_link_ksettings(struct net_device *dev,
958 const struct ethtool_link_ksettings *cmd)
959{
960 return encx24j600_setlink(dev, cmd->base.autoneg,
961 cmd->base.speed, cmd->base.duplex);
962}
963
964static u32 encx24j600_get_msglevel(struct net_device *dev)
965{
966 struct encx24j600_priv *priv = netdev_priv(dev);
967
968 return priv->msg_enable;
969}
970
971static void encx24j600_set_msglevel(struct net_device *dev, u32 val)
972{
973 struct encx24j600_priv *priv = netdev_priv(dev);
974
975 priv->msg_enable = val;
976}
977
978static const struct ethtool_ops encx24j600_ethtool_ops = {
979 .get_drvinfo = encx24j600_get_drvinfo,
980 .get_msglevel = encx24j600_get_msglevel,
981 .set_msglevel = encx24j600_set_msglevel,
982 .get_regs_len = encx24j600_get_regs_len,
983 .get_regs = encx24j600_get_regs,
984 .get_link_ksettings = encx24j600_get_link_ksettings,
985 .set_link_ksettings = encx24j600_set_link_ksettings,
986};
987
988static const struct net_device_ops encx24j600_netdev_ops = {
989 .ndo_open = encx24j600_open,
990 .ndo_stop = encx24j600_stop,
991 .ndo_start_xmit = encx24j600_tx,
992 .ndo_set_rx_mode = encx24j600_set_multicast_list,
993 .ndo_set_mac_address = encx24j600_set_mac_address,
994 .ndo_tx_timeout = encx24j600_tx_timeout,
995 .ndo_validate_addr = eth_validate_addr,
996};
997
998static int encx24j600_spi_probe(struct spi_device *spi)
999{
1000 int ret;
1001
1002 struct net_device *ndev;
1003 struct encx24j600_priv *priv;
1004 u16 eidled;
1005
1006 ndev = alloc_etherdev(sizeof(struct encx24j600_priv));
1007
1008 if (!ndev) {
1009 ret = -ENOMEM;
1010 goto error_out;
1011 }
1012
1013 priv = netdev_priv(ndev);
1014 spi_set_drvdata(spi, priv);
1015 dev_set_drvdata(&spi->dev, priv);
1016 SET_NETDEV_DEV(ndev, &spi->dev);
1017
1018 priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1019 priv->ndev = ndev;
1020
1021
1022 priv->full_duplex = true;
1023 priv->autoneg = AUTONEG_ENABLE;
1024 priv->speed = SPEED_100;
1025
1026 priv->ctx.spi = spi;
1027 devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
1028 ndev->irq = spi->irq;
1029 ndev->netdev_ops = &encx24j600_netdev_ops;
1030
1031 mutex_init(&priv->lock);
1032
1033
1034 if (encx24j600_hw_reset(priv)) {
1035 netif_err(priv, probe, ndev,
1036 DRV_NAME ": Chip is not detected\n");
1037 ret = -EIO;
1038 goto out_free;
1039 }
1040
1041
1042 encx24j600_hw_init(priv);
1043
1044 kthread_init_worker(&priv->kworker);
1045 kthread_init_work(&priv->tx_work, encx24j600_tx_proc);
1046 kthread_init_work(&priv->setrx_work, encx24j600_setrx_proc);
1047
1048 priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
1049 "encx24j600");
1050
1051 if (IS_ERR(priv->kworker_task)) {
1052 ret = PTR_ERR(priv->kworker_task);
1053 goto out_free;
1054 }
1055
1056
1057 encx24j600_hw_get_macaddr(priv, ndev->dev_addr);
1058
1059 ndev->ethtool_ops = &encx24j600_ethtool_ops;
1060
1061 ret = register_netdev(ndev);
1062 if (unlikely(ret)) {
1063 netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
1064 ret);
1065 goto out_stop;
1066 }
1067
1068 eidled = encx24j600_read_reg(priv, EIDLED);
1069 if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) {
1070 ret = -EINVAL;
1071 goto out_unregister;
1072 }
1073
1074 netif_info(priv, probe, ndev, "Silicon rev ID: 0x%02x\n",
1075 (eidled & REVID_MASK) >> REVID_SHIFT);
1076
1077 netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
1078
1079 return ret;
1080
1081out_unregister:
1082 unregister_netdev(priv->ndev);
1083out_stop:
1084 kthread_stop(priv->kworker_task);
1085out_free:
1086 free_netdev(ndev);
1087
1088error_out:
1089 return ret;
1090}
1091
1092static int encx24j600_spi_remove(struct spi_device *spi)
1093{
1094 struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
1095
1096 unregister_netdev(priv->ndev);
1097 kthread_stop(priv->kworker_task);
1098
1099 free_netdev(priv->ndev);
1100
1101 return 0;
1102}
1103
1104static const struct spi_device_id encx24j600_spi_id_table[] = {
1105 { .name = "encx24j600" },
1106 { }
1107};
1108MODULE_DEVICE_TABLE(spi, encx24j600_spi_id_table);
1109
1110static struct spi_driver encx24j600_spi_net_driver = {
1111 .driver = {
1112 .name = DRV_NAME,
1113 .owner = THIS_MODULE,
1114 .bus = &spi_bus_type,
1115 },
1116 .probe = encx24j600_spi_probe,
1117 .remove = encx24j600_spi_remove,
1118 .id_table = encx24j600_spi_id_table,
1119};
1120
1121static int __init encx24j600_init(void)
1122{
1123 return spi_register_driver(&encx24j600_spi_net_driver);
1124}
1125module_init(encx24j600_init);
1126
1127static void encx24j600_exit(void)
1128{
1129 spi_unregister_driver(&encx24j600_spi_net_driver);
1130}
1131module_exit(encx24j600_exit);
1132
1133MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1134MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1135MODULE_LICENSE("GPL");
1136MODULE_ALIAS("spi:" DRV_NAME);
1137
