1
2
3
4#include <linux/etherdevice.h>
5#include <linux/timekeeping.h>
6#include "mt7915.h"
7#include "../dma.h"
8#include "mac.h"
9
10#define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
11
12#define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f)
13#define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
14 IEEE80211_RADIOTAP_HE_##f)
15
16static const struct mt7915_dfs_radar_spec etsi_radar_specs = {
17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
18 .radar_pattern = {
19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
27 },
28};
29
30static const struct mt7915_dfs_radar_spec fcc_radar_specs = {
31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
32 .radar_pattern = {
33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
38 },
39};
40
41static const struct mt7915_dfs_radar_spec jp_radar_specs = {
42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
43 .radar_pattern = {
44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 },
50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 },
51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 },
52 },
53};
54
55static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev,
56 u16 idx, bool unicast)
57{
58 struct mt7915_sta *sta;
59 struct mt76_wcid *wcid;
60
61 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
62 return NULL;
63
64 wcid = rcu_dereference(dev->mt76.wcid[idx]);
65 if (unicast || !wcid)
66 return wcid;
67
68 if (!wcid->sta)
69 return NULL;
70
71 sta = container_of(wcid, struct mt7915_sta, wcid);
72 if (!sta->vif)
73 return NULL;
74
75 return &sta->vif->sta.wcid;
76}
77
78void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
79{
80}
81
82bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask)
83{
84 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
85 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
86
87 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
88 0, 5000);
89}
90
91static u32 mt7915_mac_wtbl_lmac_read(struct mt7915_dev *dev, u16 wcid,
92 u16 addr)
93{
94 mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
95 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7)));
96
97 return mt76_rr(dev, MT_WTBL_LMAC_OFFS(wcid, addr));
98}
99
100
101void mt7915_mac_sta_poll(struct mt7915_dev *dev)
102{
103 static const u8 ac_to_tid[] = {
104 [IEEE80211_AC_BE] = 0,
105 [IEEE80211_AC_BK] = 1,
106 [IEEE80211_AC_VI] = 4,
107 [IEEE80211_AC_VO] = 6
108 };
109 static const u8 hw_queue_map[] = {
110 [IEEE80211_AC_BK] = 0,
111 [IEEE80211_AC_BE] = 1,
112 [IEEE80211_AC_VI] = 2,
113 [IEEE80211_AC_VO] = 3,
114 };
115 struct ieee80211_sta *sta;
116 struct mt7915_sta *msta;
117 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
118 int i;
119
120 rcu_read_lock();
121
122 while (true) {
123 bool clear = false;
124 u16 idx;
125
126 spin_lock_bh(&dev->sta_poll_lock);
127 if (list_empty(&dev->sta_poll_list)) {
128 spin_unlock_bh(&dev->sta_poll_lock);
129 break;
130 }
131 msta = list_first_entry(&dev->sta_poll_list,
132 struct mt7915_sta, poll_list);
133 list_del_init(&msta->poll_list);
134 spin_unlock_bh(&dev->sta_poll_lock);
135
136 for (i = 0, idx = msta->wcid.idx; i < IEEE80211_NUM_ACS; i++) {
137 u32 tx_last = msta->airtime_ac[i];
138 u32 rx_last = msta->airtime_ac[i + IEEE80211_NUM_ACS];
139
140 msta->airtime_ac[i] =
141 mt7915_mac_wtbl_lmac_read(dev, idx, 20 + i);
142 msta->airtime_ac[i + IEEE80211_NUM_ACS] =
143 mt7915_mac_wtbl_lmac_read(dev, idx, 21 + i);
144 tx_time[i] = msta->airtime_ac[i] - tx_last;
145 rx_time[i] = msta->airtime_ac[i + IEEE80211_NUM_ACS] -
146 rx_last;
147
148 if ((tx_last | rx_last) & BIT(30))
149 clear = true;
150 }
151
152 if (clear) {
153 mt7915_mac_wtbl_update(dev, idx,
154 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
155 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
156 }
157
158 if (!msta->wcid.sta)
159 continue;
160
161 sta = container_of((void *)msta, struct ieee80211_sta,
162 drv_priv);
163 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
164 u32 tx_cur = tx_time[i];
165 u32 rx_cur = rx_time[hw_queue_map[i]];
166 u8 tid = ac_to_tid[i];
167
168 if (!tx_cur && !rx_cur)
169 continue;
170
171 ieee80211_sta_register_airtime(sta, tid, tx_cur,
172 rx_cur);
173 }
174 }
175
176 rcu_read_unlock();
177}
178
179static void
180mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status,
181 struct mt7915_rxv *rxv,
182 struct ieee80211_radiotap_he *he)
183{
184 u32 ru_h, ru_l;
185 u8 ru, offs = 0;
186
187 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv->v[0]));
188 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv->v[1]));
189 ru = (u8)(ru_l | ru_h << 4);
190
191 status->bw = RATE_INFO_BW_HE_RU;
192
193 switch (ru) {
194 case 0 ... 36:
195 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26;
196 offs = ru;
197 break;
198 case 37 ... 52:
199 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52;
200 offs = ru - 37;
201 break;
202 case 53 ... 60:
203 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106;
204 offs = ru - 53;
205 break;
206 case 61 ... 64:
207 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242;
208 offs = ru - 61;
209 break;
210 case 65 ... 66:
211 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484;
212 offs = ru - 65;
213 break;
214 case 67:
215 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996;
216 break;
217 case 68:
218 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
219 break;
220 }
221
222 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
223 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) |
224 le16_encode_bits(offs,
225 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET);
226}
227
228static void
229mt7915_mac_decode_he_radiotap(struct sk_buff *skb,
230 struct mt76_rx_status *status,
231 struct mt7915_rxv *rxv)
232{
233
234 static const struct ieee80211_radiotap_he known = {
235 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) |
236 HE_BITS(DATA1_DATA_DCM_KNOWN) |
237 HE_BITS(DATA1_STBC_KNOWN) |
238 HE_BITS(DATA1_CODING_KNOWN) |
239 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) |
240 HE_BITS(DATA1_DOPPLER_KNOWN) |
241 HE_BITS(DATA1_BSS_COLOR_KNOWN),
242 .data2 = HE_BITS(DATA2_GI_KNOWN) |
243 HE_BITS(DATA2_TXBF_KNOWN) |
244 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) |
245 HE_BITS(DATA2_TXOP_KNOWN),
246 };
247 struct ieee80211_radiotap_he *he = NULL;
248 __le32 v2 = rxv->v[2];
249 __le32 v11 = rxv->v[11];
250 __le32 v14 = rxv->v[14];
251 u32 ltf_size = le32_get_bits(v2, MT_CRXV_HE_LTF_SIZE) + 1;
252
253 he = skb_push(skb, sizeof(known));
254 memcpy(he, &known, sizeof(known));
255
256 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, v14) |
257 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, v2);
258 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, v2) |
259 le16_encode_bits(ltf_size,
260 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE);
261 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, v14) |
262 HE_PREP(DATA6_DOPPLER, DOPPLER, v14);
263
264 switch (rxv->phy) {
265 case MT_PHY_TYPE_HE_SU:
266 he->data1 |= HE_BITS(DATA1_FORMAT_SU) |
267 HE_BITS(DATA1_UL_DL_KNOWN) |
268 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) |
269 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
270
271 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, v14) |
272 HE_PREP(DATA3_UL_DL, UPLINK, v2);
273 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, v11);
274 break;
275 case MT_PHY_TYPE_HE_EXT_SU:
276 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) |
277 HE_BITS(DATA1_UL_DL_KNOWN);
278
279 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, v2);
280 break;
281 case MT_PHY_TYPE_HE_MU:
282 he->data1 |= HE_BITS(DATA1_FORMAT_MU) |
283 HE_BITS(DATA1_UL_DL_KNOWN) |
284 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
285
286 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, v2);
287 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, v11);
288
289 mt7915_mac_decode_he_radiotap_ru(status, rxv, he);
290 break;
291 case MT_PHY_TYPE_HE_TB:
292 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) |
293 HE_BITS(DATA1_SPTL_REUSE_KNOWN) |
294 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) |
295 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) |
296 HE_BITS(DATA1_SPTL_REUSE4_KNOWN);
297
298 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, v11) |
299 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, v11) |
300 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, v11) |
301 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, v11);
302
303 mt7915_mac_decode_he_radiotap_ru(status, rxv, he);
304 break;
305 default:
306 break;
307 }
308}
309
310int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
311{
312 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
313 struct mt76_phy *mphy = &dev->mt76.phy;
314 struct mt7915_phy *phy = &dev->phy;
315 struct ieee80211_supported_band *sband;
316 struct ieee80211_hdr *hdr;
317 struct mt7915_rxv rxv = {};
318 __le32 *rxd = (__le32 *)skb->data;
319 u32 rxd1 = le32_to_cpu(rxd[1]);
320 u32 rxd2 = le32_to_cpu(rxd[2]);
321 u32 rxd3 = le32_to_cpu(rxd[3]);
322 bool unicast, insert_ccmp_hdr = false;
323 u8 remove_pad;
324 int i, idx;
325
326 memset(status, 0, sizeof(*status));
327
328 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) {
329 mphy = dev->mt76.phy2;
330 if (!mphy)
331 return -EINVAL;
332
333 phy = mphy->priv;
334 status->ext_phy = true;
335 }
336
337 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
338 return -EINVAL;
339
340 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
341 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
342 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast);
343
344 if (status->wcid) {
345 struct mt7915_sta *msta;
346
347 msta = container_of(status->wcid, struct mt7915_sta, wcid);
348 spin_lock_bh(&dev->sta_poll_lock);
349 if (list_empty(&msta->poll_list))
350 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
351 spin_unlock_bh(&dev->sta_poll_lock);
352 }
353
354 status->freq = mphy->chandef.chan->center_freq;
355 status->band = mphy->chandef.chan->band;
356 if (status->band == NL80211_BAND_5GHZ)
357 sband = &mphy->sband_5g.sband;
358 else
359 sband = &mphy->sband_2g.sband;
360
361 if (!sband->channels)
362 return -EINVAL;
363
364 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
365 status->flag |= RX_FLAG_FAILED_FCS_CRC;
366
367 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
368 status->flag |= RX_FLAG_MMIC_ERROR;
369
370 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
371 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
372 status->flag |= RX_FLAG_DECRYPTED;
373 status->flag |= RX_FLAG_IV_STRIPPED;
374 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
375 }
376
377 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
378 status->flag |= RX_FLAG_AMPDU_DETAILS;
379
380
381 if (phy->rx_ampdu_ts != rxd[14]) {
382 if (!++phy->ampdu_ref)
383 phy->ampdu_ref++;
384 }
385 phy->rx_ampdu_ts = rxd[14];
386
387 status->ampdu_ref = phy->ampdu_ref;
388 }
389
390 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
391
392 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
393 return -EINVAL;
394
395 rxd += 6;
396 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
397 rxd += 4;
398 if ((u8 *)rxd - skb->data >= skb->len)
399 return -EINVAL;
400 }
401
402 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
403 u8 *data = (u8 *)rxd;
404
405 if (status->flag & RX_FLAG_DECRYPTED) {
406 status->iv[0] = data[5];
407 status->iv[1] = data[4];
408 status->iv[2] = data[3];
409 status->iv[3] = data[2];
410 status->iv[4] = data[1];
411 status->iv[5] = data[0];
412
413 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
414 }
415 rxd += 4;
416 if ((u8 *)rxd - skb->data >= skb->len)
417 return -EINVAL;
418 }
419
420 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
421 rxd += 2;
422 if ((u8 *)rxd - skb->data >= skb->len)
423 return -EINVAL;
424 }
425
426
427 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
428 u32 v0, v1, v2;
429
430 memcpy(rxv.v, rxd, sizeof(rxv.v));
431
432 rxd += 2;
433 if ((u8 *)rxd - skb->data >= skb->len)
434 return -EINVAL;
435
436 v0 = le32_to_cpu(rxv.v[0]);
437 v1 = le32_to_cpu(rxv.v[1]);
438 v2 = le32_to_cpu(rxv.v[2]);
439
440 if (v0 & MT_PRXV_HT_AD_CODE)
441 status->enc_flags |= RX_ENC_FLAG_LDPC;
442
443 status->chains = mphy->antenna_mask;
444 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
445 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
446 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
447 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
448 status->signal = status->chain_signal[0];
449
450 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
451 if (!(status->chains & BIT(i)))
452 continue;
453
454 status->signal = max(status->signal,
455 status->chain_signal[i]);
456 }
457
458
459 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
460 u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
461 u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
462 bool cck = false;
463
464 rxd += 18;
465 if ((u8 *)rxd - skb->data >= skb->len)
466 return -EINVAL;
467
468 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
469 rxv.phy = FIELD_GET(MT_CRXV_TX_MODE, v2);
470
471 switch (rxv.phy) {
472 case MT_PHY_TYPE_CCK:
473 cck = true;
474
475 case MT_PHY_TYPE_OFDM:
476 i = mt76_get_rate(&dev->mt76, sband, i, cck);
477 break;
478 case MT_PHY_TYPE_HT_GF:
479 case MT_PHY_TYPE_HT:
480 status->encoding = RX_ENC_HT;
481 if (i > 31)
482 return -EINVAL;
483 break;
484 case MT_PHY_TYPE_VHT:
485 status->nss =
486 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
487 status->encoding = RX_ENC_VHT;
488 if (i > 9)
489 return -EINVAL;
490 break;
491 case MT_PHY_TYPE_HE_MU:
492 status->flag |= RX_FLAG_RADIOTAP_HE_MU;
493
494 case MT_PHY_TYPE_HE_SU:
495 case MT_PHY_TYPE_HE_EXT_SU:
496 case MT_PHY_TYPE_HE_TB:
497 status->nss =
498 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
499 status->encoding = RX_ENC_HE;
500 status->flag |= RX_FLAG_RADIOTAP_HE;
501 i &= GENMASK(3, 0);
502
503 if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
504 status->he_gi = gi;
505
506 if (idx & MT_PRXV_TX_DCM)
507 status->he_dcm = true;
508 break;
509 default:
510 return -EINVAL;
511 }
512 status->rate_idx = i;
513
514 switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
515 case IEEE80211_STA_RX_BW_20:
516 break;
517 case IEEE80211_STA_RX_BW_40:
518 if (rxv.phy & MT_PHY_TYPE_HE_EXT_SU &&
519 (idx & MT_PRXV_TX_ER_SU_106T)) {
520 status->bw = RATE_INFO_BW_HE_RU;
521 status->he_ru =
522 NL80211_RATE_INFO_HE_RU_ALLOC_106;
523 } else {
524 status->bw = RATE_INFO_BW_40;
525 }
526 break;
527 case IEEE80211_STA_RX_BW_80:
528 status->bw = RATE_INFO_BW_80;
529 break;
530 case IEEE80211_STA_RX_BW_160:
531 status->bw = RATE_INFO_BW_160;
532 break;
533 default:
534 return -EINVAL;
535 }
536
537 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
538 if (rxv.phy < MT_PHY_TYPE_HE_SU && gi)
539 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
540 }
541 }
542
543 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
544
545 if (insert_ccmp_hdr) {
546 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
547
548 mt76_insert_ccmp_hdr(skb, key_id);
549 }
550
551 if (status->flag & RX_FLAG_RADIOTAP_HE)
552 mt7915_mac_decode_he_radiotap(skb, status, &rxv);
553
554 hdr = mt76_skb_get_hdr(skb);
555 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
556 return 0;
557
558 status->aggr = unicast &&
559 !ieee80211_is_qos_nullfunc(hdr->frame_control);
560 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
561 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
562
563 return 0;
564}
565
566void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi,
567 struct sk_buff *skb, struct mt76_wcid *wcid,
568 struct ieee80211_key_conf *key, bool beacon)
569{
570 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
571 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
572 bool multicast = is_multicast_ether_addr(hdr->addr1);
573 struct ieee80211_vif *vif = info->control.vif;
574 struct mt76_phy *mphy = &dev->mphy;
575 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
576 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
577 __le16 fc = hdr->frame_control;
578 u16 tx_count = 4, seqno = 0;
579 u32 val;
580
581 if (vif) {
582 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
583
584 omac_idx = mvif->omac_idx;
585 wmm_idx = mvif->wmm_idx;
586 }
587
588 if (ext_phy && dev->mt76.phy2)
589 mphy = dev->mt76.phy2;
590
591 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
592 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
593
594 if (ieee80211_is_data(fc) || ieee80211_is_bufferable_mmpdu(fc)) {
595 q_idx = wmm_idx * MT7915_MAX_WMM_SETS +
596 skb_get_queue_mapping(skb);
597 p_fmt = MT_TX_TYPE_CT;
598 } else if (beacon) {
599 q_idx = MT_LMAC_BCN0;
600 p_fmt = MT_TX_TYPE_FW;
601 } else {
602 q_idx = MT_LMAC_ALTX0;
603 p_fmt = MT_TX_TYPE_CT;
604 }
605
606 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
607 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) |
608 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
609 txwi[0] = cpu_to_le32(val);
610
611 val = MT_TXD1_LONG_FORMAT |
612 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
613 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
614 FIELD_PREP(MT_TXD1_HDR_INFO,
615 ieee80211_get_hdrlen_from_skb(skb) / 2) |
616 FIELD_PREP(MT_TXD1_TID,
617 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
618 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
619 if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0)
620 val |= MT_TXD1_TGID;
621
622 txwi[1] = cpu_to_le32(val);
623
624 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
625 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
626 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
627 if (key) {
628 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
629 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
630 val |= MT_TXD2_BIP;
631 txwi[3] = 0;
632 } else {
633 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
634 }
635 } else {
636 txwi[3] = 0;
637 }
638 txwi[2] = cpu_to_le32(val);
639
640 txwi[4] = 0;
641 txwi[5] = 0;
642 txwi[6] = 0;
643
644 if (!ieee80211_is_data(fc) || multicast) {
645 u16 rate;
646
647
648 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE | MT_TXD2_HTC_VLD);
649
650 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
651 rate = MT7915_5G_RATE_DEFAULT;
652 else
653 rate = MT7915_2G_RATE_DEFAULT;
654
655 val = MT_TXD6_FIXED_BW |
656 FIELD_PREP(MT_TXD6_TX_RATE, rate);
657 txwi[6] |= cpu_to_le32(val);
658 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
659 }
660
661 if (!ieee80211_is_beacon(fc))
662 txwi[3] |= cpu_to_le32(MT_TXD3_SW_POWER_MGMT);
663 else
664 tx_count = 0x1f;
665
666 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
667 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
668
669 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
670 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
671 txwi[7] = cpu_to_le32(val);
672
673 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
674 if (ieee80211_is_data_qos(fc)) {
675 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
676 val |= MT_TXD3_SN_VALID;
677 } else if (ieee80211_is_back_req(fc)) {
678 struct ieee80211_bar *bar;
679
680 bar = (struct ieee80211_bar *)skb->data;
681 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
682 val |= MT_TXD3_SN_VALID;
683 }
684 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
685 txwi[3] |= cpu_to_le32(val);
686}
687
688int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
689 enum mt76_txq_id qid, struct mt76_wcid *wcid,
690 struct ieee80211_sta *sta,
691 struct mt76_tx_info *tx_info)
692{
693 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
694 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
695 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
696 struct ieee80211_key_conf *key = info->control.hw_key;
697 struct ieee80211_vif *vif = info->control.vif;
698 struct mt76_tx_cb *cb = mt76_tx_skb_cb(tx_info->skb);
699 struct mt76_txwi_cache *t;
700 struct mt7915_txp *txp;
701 int id, i, nbuf = tx_info->nbuf - 1;
702 u8 *txwi = (u8 *)txwi_ptr;
703
704 if (!wcid)
705 wcid = &dev->mt76.global_wcid;
706
707 cb->wcid = wcid->idx;
708
709 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key,
710 false);
711
712 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
713 for (i = 0; i < nbuf; i++) {
714 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
715 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
716 }
717 txp->nbuf = nbuf;
718
719
720 tx_info->buf[1].len = MT_CT_PARSE_LEN;
721 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
722
723 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
724
725 if (!key)
726 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
727
728 if (ieee80211_is_mgmt(hdr->frame_control))
729 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
730
731 if (vif) {
732 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
733
734 txp->bss_idx = mvif->idx;
735 }
736
737 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
738 t->skb = tx_info->skb;
739
740 spin_lock_bh(&dev->token_lock);
741 id = idr_alloc(&dev->token, t, 0, MT7915_TOKEN_SIZE, GFP_ATOMIC);
742 spin_unlock_bh(&dev->token_lock);
743 if (id < 0)
744 return id;
745
746 txp->token = cpu_to_le16(id);
747 txp->rept_wds_wcid = 0xff;
748 tx_info->skb = DMA_DUMMY_DATA;
749
750 return 0;
751}
752
753static inline bool
754mt7915_tx_check_aggr_tid(struct mt7915_sta *msta, u8 tid)
755{
756 bool ret = false;
757
758 spin_lock_bh(&msta->ampdu_lock);
759 if (msta->ampdu_state[tid] == MT7915_AGGR_STOP)
760 ret = true;
761 spin_unlock_bh(&msta->ampdu_lock);
762
763 return ret;
764}
765
766static void
767mt7915_tx_check_aggr(struct ieee80211_sta *sta, struct sk_buff *skb)
768{
769 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
770 struct mt7915_sta *msta;
771 u16 tid;
772
773 if (!sta->ht_cap.ht_supported)
774 return;
775
776 if (skb_get_queue_mapping(skb) == IEEE80211_AC_VO)
777 return;
778
779 if (unlikely(!ieee80211_is_data_qos(hdr->frame_control)))
780 return;
781
782 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE)))
783 return;
784
785 msta = (struct mt7915_sta *)sta->drv_priv;
786 tid = ieee80211_get_tid(hdr);
787
788 if (mt7915_tx_check_aggr_tid(msta, tid)) {
789 ieee80211_start_tx_ba_session(sta, tid, 0);
790 mt7915_set_aggr_state(msta, tid, MT7915_AGGR_PROGRESS);
791 }
792}
793
794static inline void
795mt7915_tx_status(struct ieee80211_sta *sta, struct ieee80211_hw *hw,
796 struct ieee80211_tx_info *info, struct sk_buff *skb)
797{
798 struct ieee80211_tx_status status = {
799 .sta = sta,
800 .info = info,
801 };
802
803 if (skb)
804 status.skb = skb;
805
806 if (sta) {
807 struct mt7915_sta *msta;
808
809 msta = (struct mt7915_sta *)sta->drv_priv;
810 status.rate = &msta->stats.tx_rate;
811 }
812
813
814 ieee80211_tx_status_ext(hw, &status);
815}
816
817static void
818mt7915_tx_complete_status(struct mt76_dev *mdev, struct sk_buff *skb,
819 struct ieee80211_sta *sta, u8 stat)
820{
821 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
822 struct ieee80211_hw *hw;
823
824 hw = mt76_tx_status_get_hw(mdev, skb);
825
826 if (info->flags & IEEE80211_TX_CTL_AMPDU)
827 info->flags |= IEEE80211_TX_STAT_AMPDU;
828 else if (sta)
829 mt7915_tx_check_aggr(sta, skb);
830
831 if (stat)
832 ieee80211_tx_info_clear_status(info);
833
834 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
835 info->flags |= IEEE80211_TX_STAT_ACK;
836
837 info->status.tx_time = 0;
838
839 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
840 mt7915_tx_status(sta, hw, info, skb);
841 return;
842 }
843
844 if (sta || !(info->flags & IEEE80211_TX_CTL_NO_ACK))
845 mt7915_tx_status(sta, hw, info, NULL);
846
847 dev_kfree_skb(skb);
848}
849
850void mt7915_txp_skb_unmap(struct mt76_dev *dev,
851 struct mt76_txwi_cache *t)
852{
853 struct mt7915_txp *txp;
854 int i;
855
856 txp = mt7915_txwi_to_txp(dev, t);
857 for (i = 1; i < txp->nbuf; i++)
858 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
859 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
860}
861
862void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
863{
864 struct mt7915_tx_free *free = (struct mt7915_tx_free *)skb->data;
865 struct mt76_dev *mdev = &dev->mt76;
866 struct mt76_txwi_cache *txwi;
867 struct ieee80211_sta *sta = NULL;
868 u8 i, count;
869
870
871
872
873
874
875 count = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl));
876 for (i = 0; i < count; i++) {
877 u32 msdu, info = le32_to_cpu(free->info[i]);
878 u8 stat;
879
880
881
882
883
884 if (info & MT_TX_FREE_PAIR) {
885 struct mt7915_sta *msta;
886 struct mt76_wcid *wcid;
887 u16 idx;
888
889 count++;
890 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
891 wcid = rcu_dereference(dev->mt76.wcid[idx]);
892 sta = wcid_to_sta(wcid);
893 if (!sta)
894 continue;
895
896 msta = container_of(wcid, struct mt7915_sta, wcid);
897 ieee80211_queue_work(mt76_hw(dev), &msta->stats_work);
898 continue;
899 }
900
901 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
902 stat = FIELD_GET(MT_TX_FREE_STATUS, info);
903
904 spin_lock_bh(&dev->token_lock);
905 txwi = idr_remove(&dev->token, msdu);
906 spin_unlock_bh(&dev->token_lock);
907
908 if (!txwi)
909 continue;
910
911 mt7915_txp_skb_unmap(mdev, txwi);
912 if (txwi->skb) {
913 mt7915_tx_complete_status(mdev, txwi->skb, sta, stat);
914 txwi->skb = NULL;
915 }
916
917 mt76_put_txwi(mdev, txwi);
918 }
919 dev_kfree_skb(skb);
920}
921
922void mt7915_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
923 struct mt76_queue_entry *e)
924{
925 struct mt7915_dev *dev;
926
927 if (!e->txwi) {
928 dev_kfree_skb_any(e->skb);
929 return;
930 }
931
932 dev = container_of(mdev, struct mt7915_dev, mt76);
933
934
935 if (e->skb == DMA_DUMMY_DATA) {
936 struct mt76_txwi_cache *t;
937 struct mt7915_txp *txp;
938
939 txp = mt7915_txwi_to_txp(mdev, e->txwi);
940
941 spin_lock_bh(&dev->token_lock);
942 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
943 spin_unlock_bh(&dev->token_lock);
944 e->skb = t ? t->skb : NULL;
945 }
946
947 if (e->skb) {
948 struct mt76_tx_cb *cb = mt76_tx_skb_cb(e->skb);
949 struct mt76_wcid *wcid;
950
951 wcid = rcu_dereference(dev->mt76.wcid[cb->wcid]);
952
953 mt7915_tx_complete_status(mdev, e->skb, wcid_to_sta(wcid), 0);
954 }
955}
956
957void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy)
958{
959 struct mt7915_dev *dev = phy->dev;
960 bool ext_phy = phy != &dev->phy;
961 u32 reg = MT_WF_PHY_RX_CTRL1(ext_phy);
962
963 mt7915_l2_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN);
964 mt7915_l2_set(dev, reg, BIT(11) | BIT(9));
965}
966
967void mt7915_mac_reset_counters(struct mt7915_phy *phy)
968{
969 struct mt7915_dev *dev = phy->dev;
970 bool ext_phy = phy != &dev->phy;
971 int i;
972
973 for (i = 0; i < 4; i++) {
974 mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
975 mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
976 }
977
978 if (ext_phy) {
979 dev->mt76.phy2->survey_time = ktime_get_boottime();
980 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2;
981 } else {
982 dev->mt76.phy.survey_time = ktime_get_boottime();
983 i = 0;
984 }
985 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2);
986
987
988 mt76_rr(dev, MT_MIB_SDR9(ext_phy));
989 mt76_rr(dev, MT_MIB_SDR36(ext_phy));
990 mt76_rr(dev, MT_MIB_SDR37(ext_phy));
991
992 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(ext_phy),
993 MT_WF_RMAC_MIB_RXTIME_CLR);
994 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(ext_phy),
995 MT_WF_RMAC_MIB_RXTIME_CLR);
996}
997
998void mt7915_mac_set_timing(struct mt7915_phy *phy)
999{
1000 s16 coverage_class = phy->coverage_class;
1001 struct mt7915_dev *dev = phy->dev;
1002 bool ext_phy = phy != &dev->phy;
1003 u32 val, reg_offset;
1004 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
1005 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
1006 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
1007 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
1008 int sifs, offset;
1009 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
1010
1011 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1012 return;
1013
1014 if (is_5ghz)
1015 sifs = 16;
1016 else
1017 sifs = 10;
1018
1019 if (ext_phy) {
1020 coverage_class = max_t(s16, dev->phy.coverage_class,
1021 coverage_class);
1022 } else {
1023 struct mt7915_phy *phy_ext = mt7915_ext_phy(dev);
1024
1025 if (phy_ext)
1026 coverage_class = max_t(s16, phy_ext->coverage_class,
1027 coverage_class);
1028 }
1029 mt76_set(dev, MT_ARB_SCR(ext_phy),
1030 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1031 udelay(1);
1032
1033 offset = 3 * coverage_class;
1034 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1035 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
1036
1037 mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset);
1038 mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset);
1039 mt76_wr(dev, MT_TMAC_ICR0(ext_phy),
1040 FIELD_PREP(MT_IFS_EIFS, 360) |
1041 FIELD_PREP(MT_IFS_RIFS, 2) |
1042 FIELD_PREP(MT_IFS_SIFS, sifs) |
1043 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
1044
1045 if (phy->slottime < 20 || is_5ghz)
1046 val = MT7915_CFEND_RATE_DEFAULT;
1047 else
1048 val = MT7915_CFEND_RATE_11B;
1049
1050 mt76_rmw_field(dev, MT_AGG_ACR0(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
1051 mt76_clear(dev, MT_ARB_SCR(ext_phy),
1052 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1053}
1054
1055
1056
1057
1058
1059
1060static void
1061mt7915_phy_update_channel(struct mt76_phy *mphy, int idx)
1062{
1063 struct mt7915_dev *dev = container_of(mphy->dev, struct mt7915_dev, mt76);
1064 struct mt76_channel_state *state;
1065 u64 busy_time, tx_time, rx_time, obss_time;
1066
1067 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1068 MT_MIB_SDR9_BUSY_MASK);
1069 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1070 MT_MIB_SDR36_TXTIME_MASK);
1071 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1072 MT_MIB_SDR37_RXTIME_MASK);
1073 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx),
1074 MT_MIB_OBSSTIME_MASK);
1075
1076
1077 state = mphy->chan_state;
1078 state->cc_busy += busy_time;
1079 state->cc_tx += tx_time;
1080 state->cc_rx += rx_time + obss_time;
1081 state->cc_bss_rx += rx_time;
1082}
1083
1084void mt7915_update_channel(struct mt76_dev *mdev)
1085{
1086 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1087
1088 mt7915_phy_update_channel(&mdev->phy, 0);
1089 if (mdev->phy2)
1090 mt7915_phy_update_channel(mdev->phy2, 1);
1091
1092
1093 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
1094 if (mdev->phy2)
1095 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(1),
1096 MT_WF_RMAC_MIB_RXTIME_CLR);
1097}
1098
1099static bool
1100mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state)
1101{
1102 bool ret;
1103
1104 ret = wait_event_timeout(dev->reset_wait,
1105 (READ_ONCE(dev->reset_state) & state),
1106 MT7915_RESET_TIMEOUT);
1107
1108 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1109 return ret;
1110}
1111
1112static void
1113mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1114{
1115 struct ieee80211_hw *hw = priv;
1116
1117 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon);
1118}
1119
1120static void
1121mt7915_update_beacons(struct mt7915_dev *dev)
1122{
1123 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1124 IEEE80211_IFACE_ITER_RESUME_ALL,
1125 mt7915_update_vif_beacon, dev->mt76.hw);
1126
1127 if (!dev->mt76.phy2)
1128 return;
1129
1130 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
1131 IEEE80211_IFACE_ITER_RESUME_ALL,
1132 mt7915_update_vif_beacon, dev->mt76.phy2->hw);
1133}
1134
1135static void
1136mt7915_dma_reset(struct mt7915_dev *dev)
1137{
1138 int i;
1139
1140 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
1141 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1142 mt76_clear(dev, MT_WFDMA1_GLO_CFG,
1143 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1144 usleep_range(1000, 2000);
1145
1146 for (i = 0; i < __MT_TXQ_MAX; i++)
1147 mt76_queue_tx_cleanup(dev, i, true);
1148
1149 mt76_for_each_q_rx(&dev->mt76, i) {
1150 mt76_queue_rx_reset(dev, i);
1151 }
1152
1153
1154 mt7915_dma_prefetch(dev);
1155
1156 mt76_set(dev, MT_WFDMA0_GLO_CFG,
1157 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1158 mt76_set(dev, MT_WFDMA1_GLO_CFG,
1159 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1160}
1161
1162
1163void mt7915_mac_reset_work(struct work_struct *work)
1164{
1165 struct mt7915_phy *phy2;
1166 struct mt76_phy *ext_phy;
1167 struct mt7915_dev *dev;
1168
1169 dev = container_of(work, struct mt7915_dev, reset_work);
1170 ext_phy = dev->mt76.phy2;
1171 phy2 = ext_phy ? ext_phy->priv : NULL;
1172
1173 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA))
1174 return;
1175
1176 ieee80211_stop_queues(mt76_hw(dev));
1177 if (ext_phy)
1178 ieee80211_stop_queues(ext_phy->hw);
1179
1180 set_bit(MT76_RESET, &dev->mphy.state);
1181 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1182 wake_up(&dev->mt76.mcu.wait);
1183 cancel_delayed_work_sync(&dev->phy.mac_work);
1184 if (phy2)
1185 cancel_delayed_work_sync(&phy2->mac_work);
1186
1187
1188 mt76_txq_schedule_all(&dev->mphy);
1189 if (ext_phy)
1190 mt76_txq_schedule_all(ext_phy);
1191
1192 tasklet_disable(&dev->mt76.tx_tasklet);
1193 napi_disable(&dev->mt76.napi[0]);
1194 napi_disable(&dev->mt76.napi[1]);
1195 napi_disable(&dev->mt76.napi[2]);
1196 napi_disable(&dev->mt76.tx_napi);
1197
1198 mutex_lock(&dev->mt76.mutex);
1199
1200 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
1201
1202 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1203 mt7915_dma_reset(dev);
1204
1205 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
1206 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1207 }
1208
1209 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1210 clear_bit(MT76_RESET, &dev->mphy.state);
1211
1212 tasklet_enable(&dev->mt76.tx_tasklet);
1213 napi_enable(&dev->mt76.tx_napi);
1214 napi_schedule(&dev->mt76.tx_napi);
1215
1216 napi_enable(&dev->mt76.napi[0]);
1217 napi_schedule(&dev->mt76.napi[0]);
1218
1219 napi_enable(&dev->mt76.napi[1]);
1220 napi_schedule(&dev->mt76.napi[1]);
1221
1222 napi_enable(&dev->mt76.napi[2]);
1223 napi_schedule(&dev->mt76.napi[2]);
1224
1225 ieee80211_wake_queues(mt76_hw(dev));
1226 if (ext_phy)
1227 ieee80211_wake_queues(ext_phy->hw);
1228
1229 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1230 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1231
1232 mutex_unlock(&dev->mt76.mutex);
1233
1234 mt7915_update_beacons(dev);
1235
1236 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
1237 MT7915_WATCHDOG_TIME);
1238 if (phy2)
1239 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
1240 MT7915_WATCHDOG_TIME);
1241}
1242
1243static void
1244mt7915_mac_update_mib_stats(struct mt7915_phy *phy)
1245{
1246 struct mt7915_dev *dev = phy->dev;
1247 struct mib_stats *mib = &phy->mib;
1248 bool ext_phy = phy != &dev->phy;
1249 int i, aggr0, aggr1;
1250
1251 memset(mib, 0, sizeof(*mib));
1252
1253 mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1254 MT_MIB_SDR3_FCS_ERR_MASK);
1255
1256 aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1257 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
1258 u32 val, val2;
1259
1260 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1261
1262 val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1263 if (val2 > mib->ack_fail_cnt)
1264 mib->ack_fail_cnt = val2;
1265
1266 val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1267 if (val2 > mib->ba_miss_cnt)
1268 mib->ba_miss_cnt = val2;
1269
1270 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1271 val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1272 if (val2 > mib->rts_retries_cnt) {
1273 mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1274 mib->rts_retries_cnt = val2;
1275 }
1276
1277 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1278 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
1279
1280 dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
1281 dev->mt76.aggr_stats[aggr0++] += val >> 16;
1282 dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff;
1283 dev->mt76.aggr_stats[aggr1++] += val2 >> 16;
1284 }
1285}
1286
1287void mt7915_mac_sta_stats_work(struct work_struct *work)
1288{
1289 struct ieee80211_sta *sta;
1290 struct ieee80211_vif *vif;
1291 struct mt7915_sta_stats *stats;
1292 struct mt7915_sta *msta;
1293 struct mt7915_dev *dev;
1294
1295 msta = container_of(work, struct mt7915_sta, stats_work);
1296 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
1297 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
1298 dev = msta->vif->dev;
1299 stats = &msta->stats;
1300
1301
1302 if (time_after(jiffies, stats->jiffies + HZ)) {
1303 mt7915_mcu_get_rate_info(dev, RATE_CTRL_RU_INFO,
1304 msta->wcid.idx);
1305
1306 stats->jiffies = jiffies;
1307 }
1308
1309 if (test_and_clear_bit(IEEE80211_RC_SUPP_RATES_CHANGED |
1310 IEEE80211_RC_NSS_CHANGED |
1311 IEEE80211_RC_BW_CHANGED, &stats->changed))
1312 mt7915_mcu_add_rate_ctrl(dev, vif, sta);
1313
1314 if (test_and_clear_bit(IEEE80211_RC_SMPS_CHANGED, &stats->changed))
1315 mt7915_mcu_add_smps(dev, vif, sta);
1316
1317 spin_lock_bh(&dev->sta_poll_lock);
1318 if (list_empty(&msta->poll_list))
1319 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1320 spin_unlock_bh(&dev->sta_poll_lock);
1321}
1322
1323void mt7915_mac_work(struct work_struct *work)
1324{
1325 struct mt7915_phy *phy;
1326 struct mt76_dev *mdev;
1327
1328 phy = (struct mt7915_phy *)container_of(work, struct mt7915_phy,
1329 mac_work.work);
1330 mdev = &phy->dev->mt76;
1331
1332 mutex_lock(&mdev->mutex);
1333
1334 mt76_update_survey(mdev);
1335 if (++phy->mac_work_count == 5) {
1336 phy->mac_work_count = 0;
1337
1338 mt7915_mac_update_mib_stats(phy);
1339 }
1340
1341 mutex_unlock(&mdev->mutex);
1342
1343 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
1344 MT7915_WATCHDOG_TIME);
1345}
1346
1347static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy)
1348{
1349 struct mt7915_dev *dev = phy->dev;
1350
1351 if (phy->rdd_state & BIT(0))
1352 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
1353 if (phy->rdd_state & BIT(1))
1354 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
1355}
1356
1357static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain)
1358{
1359 int err;
1360
1361 err = mt7915_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
1362 if (err < 0)
1363 return err;
1364
1365 return mt7915_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, MT_RX_SEL0, 1);
1366}
1367
1368static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy)
1369{
1370 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1371 struct mt7915_dev *dev = phy->dev;
1372 bool ext_phy = phy != &dev->phy;
1373 int err;
1374
1375
1376 err = mt7915_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
1377 if (err < 0)
1378 return err;
1379
1380 err = mt7915_dfs_start_rdd(dev, ext_phy);
1381 if (err < 0)
1382 return err;
1383
1384 phy->rdd_state |= BIT(ext_phy);
1385
1386 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1387 chandef->width == NL80211_CHAN_WIDTH_80P80) {
1388 err = mt7915_dfs_start_rdd(dev, 1);
1389 if (err < 0)
1390 return err;
1391
1392 phy->rdd_state |= BIT(1);
1393 }
1394
1395 return 0;
1396}
1397
1398static int
1399mt7915_dfs_init_radar_specs(struct mt7915_phy *phy)
1400{
1401 const struct mt7915_dfs_radar_spec *radar_specs;
1402 struct mt7915_dev *dev = phy->dev;
1403 int err, i;
1404
1405 switch (dev->mt76.region) {
1406 case NL80211_DFS_FCC:
1407 radar_specs = &fcc_radar_specs;
1408 err = mt7915_mcu_set_fcc5_lpn(dev, 8);
1409 if (err < 0)
1410 return err;
1411 break;
1412 case NL80211_DFS_ETSI:
1413 radar_specs = &etsi_radar_specs;
1414 break;
1415 case NL80211_DFS_JP:
1416 radar_specs = &jp_radar_specs;
1417 break;
1418 default:
1419 return -EINVAL;
1420 }
1421
1422 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
1423 err = mt7915_mcu_set_radar_th(dev, i,
1424 &radar_specs->radar_pattern[i]);
1425 if (err < 0)
1426 return err;
1427 }
1428
1429 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
1430}
1431
1432int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy)
1433{
1434 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1435 struct mt7915_dev *dev = phy->dev;
1436 bool ext_phy = phy != &dev->phy;
1437 int err;
1438
1439 if (dev->mt76.region == NL80211_DFS_UNSET) {
1440 phy->dfs_state = -1;
1441 if (phy->rdd_state)
1442 goto stop;
1443
1444 return 0;
1445 }
1446
1447 if (test_bit(MT76_SCANNING, &phy->mt76->state))
1448 return 0;
1449
1450 if (phy->dfs_state == chandef->chan->dfs_state)
1451 return 0;
1452
1453 err = mt7915_dfs_init_radar_specs(phy);
1454 if (err < 0) {
1455 phy->dfs_state = -1;
1456 goto stop;
1457 }
1458
1459 phy->dfs_state = chandef->chan->dfs_state;
1460
1461 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
1462 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
1463 return mt7915_dfs_start_radar_detector(phy);
1464
1465 return mt7915_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
1466 MT_RX_SEL0, 0);
1467 }
1468
1469stop:
1470 err = mt7915_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy,
1471 MT_RX_SEL0, 0);
1472 if (err < 0)
1473 return err;
1474
1475 mt7915_dfs_stop_radar_detector(phy);
1476 return 0;
1477}
1478
