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6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27
28#define SW_RESET BIT(0)
29
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36
37#define PHYSTATUS BIT(6)
38
39#define PCS_READY BIT(0)
40
41
42
43#define SW_DPPHY_RESET BIT(0)
44
45#define SW_DPPHY_RESET_MUX BIT(1)
46
47#define SW_USB3PHY_RESET BIT(2)
48
49#define SW_USB3PHY_RESET_MUX BIT(3)
50
51
52#define USB3_MODE BIT(0)
53#define DP_MODE BIT(1)
54
55
56#define ARCVR_DTCT_EN BIT(0)
57#define ALFPS_DTCT_EN BIT(1)
58#define ARCVR_DTCT_EVENT_SEL BIT(4)
59
60
61#define IRQ_CLEAR BIT(0)
62
63
64#define RCVR_DETECT BIT(0)
65
66
67#define CLAMP_EN BIT(0)
68
69#define PHY_INIT_COMPLETE_TIMEOUT 10000
70#define POWER_DOWN_DELAY_US_MIN 10
71#define POWER_DOWN_DELAY_US_MAX 11
72
73#define MAX_PROP_NAME 32
74
75
76#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
77
78struct qmp_phy_init_tbl {
79 unsigned int offset;
80 unsigned int val;
81
82
83
84
85 int in_layout;
86};
87
88#define QMP_PHY_INIT_CFG(o, v) \
89 { \
90 .offset = o, \
91 .val = v, \
92 }
93
94#define QMP_PHY_INIT_CFG_L(o, v) \
95 { \
96 .offset = o, \
97 .val = v, \
98 .in_layout = 1, \
99 }
100
101
102enum qphy_reg_layout {
103
104 QPHY_COM_SW_RESET,
105 QPHY_COM_POWER_DOWN_CONTROL,
106 QPHY_COM_START_CONTROL,
107 QPHY_COM_PCS_READY_STATUS,
108
109 QPHY_PLL_LOCK_CHK_DLY_TIME,
110 QPHY_FLL_CNTRL1,
111 QPHY_FLL_CNTRL2,
112 QPHY_FLL_CNT_VAL_L,
113 QPHY_FLL_CNT_VAL_H_TOL,
114 QPHY_FLL_MAN_CODE,
115 QPHY_SW_RESET,
116 QPHY_START_CTRL,
117 QPHY_PCS_READY_STATUS,
118 QPHY_PCS_STATUS,
119 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
120 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
121 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
122 QPHY_PCS_POWER_DOWN_CONTROL,
123
124 QPHY_LAYOUT_SIZE
125};
126
127static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
128 [QPHY_START_CTRL] = 0x00,
129 [QPHY_PCS_READY_STATUS] = 0x168,
130};
131
132static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
133 [QPHY_COM_SW_RESET] = 0x400,
134 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
135 [QPHY_COM_START_CONTROL] = 0x408,
136 [QPHY_COM_PCS_READY_STATUS] = 0x448,
137 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
138 [QPHY_FLL_CNTRL1] = 0xc4,
139 [QPHY_FLL_CNTRL2] = 0xc8,
140 [QPHY_FLL_CNT_VAL_L] = 0xcc,
141 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
142 [QPHY_FLL_MAN_CODE] = 0xd4,
143 [QPHY_SW_RESET] = 0x00,
144 [QPHY_START_CTRL] = 0x08,
145 [QPHY_PCS_STATUS] = 0x174,
146};
147
148static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
149 [QPHY_FLL_CNTRL1] = 0xc0,
150 [QPHY_FLL_CNTRL2] = 0xc4,
151 [QPHY_FLL_CNT_VAL_L] = 0xc8,
152 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
153 [QPHY_FLL_MAN_CODE] = 0xd0,
154 [QPHY_SW_RESET] = 0x00,
155 [QPHY_START_CTRL] = 0x08,
156 [QPHY_PCS_STATUS] = 0x17c,
157 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
158 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
159 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
160};
161
162static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
163 [QPHY_SW_RESET] = 0x00,
164 [QPHY_START_CTRL] = 0x08,
165 [QPHY_PCS_STATUS] = 0x174,
166 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
167 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
168 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
169};
170
171static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
172 [QPHY_SW_RESET] = 0x00,
173 [QPHY_START_CTRL] = 0x08,
174 [QPHY_PCS_STATUS] = 0x174,
175};
176
177static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
178 [QPHY_SW_RESET] = 0x00,
179 [QPHY_START_CTRL] = 0x08,
180 [QPHY_PCS_STATUS] = 0x2ac,
181};
182
183static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
184 [QPHY_SW_RESET] = 0x00,
185 [QPHY_START_CTRL] = 0x44,
186 [QPHY_PCS_STATUS] = 0x14,
187 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
188};
189
190static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
191 [QPHY_START_CTRL] = 0x00,
192 [QPHY_PCS_READY_STATUS] = 0x160,
193};
194
195static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
196 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
197 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
198 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
199};
200
201static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
202 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
203 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
204 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
205 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
206 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
207 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
208 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
209 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
210 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
211 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
212 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
213 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
214 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
215 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
216 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
217 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
218 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
219 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
220 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
221 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
222 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
223 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
224 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
225 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
226 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
227 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
228 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
229 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
230 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
231 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
232 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
233 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
234 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
235 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
236 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
237 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
238 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
239 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
240 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
241 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
242 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
243 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
244 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
245};
246
247static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
248 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
249 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
250};
251
252static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
253 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
254 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
255 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
256 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
257 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
258 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
259 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
260 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
261 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
262 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
263};
264
265static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
266 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
267 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
268 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
269
270 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
271
272 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
273 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
274 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
275 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
276 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
277};
278
279static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
322};
323
324static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
325 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
326 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
327 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
328 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
329};
330
331static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
332 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
333 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
334 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
335 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
336 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
337 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
338 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
339 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
340 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
341 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
342 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
343 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
344 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
345 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
346};
347
348static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
352 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
359};
360
361static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
362 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
363 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
364 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
365 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
366 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
367 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
368 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
369 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
370 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
371 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
372 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
373 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
374 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
375 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
376 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
377 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
378 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
379 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
380 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
381 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
382 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
383 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
384 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
385 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
386 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
387 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
388 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
389 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
390 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
391 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
392 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
393 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
394 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
395 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
396 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
397 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
398 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
399 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
400 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
401 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
402 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
403 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
404 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
405 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
406 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
407 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
408 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
409};
410
411static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
412 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
413 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
414};
415
416static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
417 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
418 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
419 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
420 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
421 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
422 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
423 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
424 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
425 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
426 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
427 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
428};
429
430static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
431 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
432 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
433 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
434 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
435 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
436 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
437 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
438 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
439 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
440
441 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
442 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
443 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
444 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
445 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
446 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
447 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
448 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
449 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
450 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
451 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
452 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
453 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
454 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
455 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
456 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
457
458 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
459 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
460 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
461 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
462 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
463 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
464 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
465};
466
467static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
468 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
469 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
470 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
471};
472
473static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
474 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
475 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
476 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
477 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
478 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
479 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
480 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
481 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
482 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
483 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
484};
485
486static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
487
488 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
489 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
490 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
491 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
492 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
493
494
495 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
496 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
497 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
498 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
499};
500
501static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
502 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
503 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
504 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
505 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
506 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
507 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
508 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
509 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
510 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
511 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
512 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
513 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
514 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
515 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
516 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
517 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
518 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
519 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
520 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
521 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
522 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
523 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
524 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
525 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
526 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
527 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
528 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
529 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
530 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
531 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
532 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
533 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
534 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
535 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
536 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
537 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
538 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
539 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
540 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
541 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
542 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
543 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
544};
545
546static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
547 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
548 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
549 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
550 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
551};
552
553static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
554 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
555 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
556 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
557 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
558 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
559 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
560 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
561 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
562};
563
564static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
565 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
566 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
567 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
568 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
569 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
570 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
571 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
572 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
573 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
574 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
575 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
576 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
577 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
578};
579
580static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
581 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
582 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
583 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
584 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
585 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
586 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
587 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
588 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
589 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
590 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
591 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
592 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
593 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
594 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
595 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
596 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
597 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
598 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
599 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
600 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
601 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
602 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
603 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
604 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
605 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
606 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
607 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
608 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
609 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
610 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
611 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
612 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
613 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
614 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
615 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
616 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
617 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
618 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
619 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
620 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
621 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
622 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
623};
624
625static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
626 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
627 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
628 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
629 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
630};
631
632static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
633 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
634 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
635 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
636 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
637 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
638 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
639 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
640 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
641 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
642 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
643 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
644 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
645 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
646 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
647 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
648 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
649};
650
651static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
652 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
653
654 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
655 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
656 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
657 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
658 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
659
660 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
661 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
662 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
663 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
664 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
665 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
666 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
667
668 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
669 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
670 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
671
672 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
673};
674
675static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
676 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
677 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
678 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
679 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
680 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
681};
682
683static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
729};
730
731static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
735 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
736 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
737 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
738 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
739 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
740 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
741 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
742 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
743 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
744 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
745 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
746 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
747 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
748 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
749 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
750 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
751 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
752 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
753 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
754 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
755 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
756 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
757 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
758 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
759 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
760 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
761 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
762 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
763 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
764 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
765 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
766 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
767 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
768 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
769 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
770 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
771 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
772 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
773 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
774 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
775 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
776 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
777 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
778 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
779 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
780 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
781 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
782 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
783 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
784 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
785 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
786 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
787 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
788};
789
790static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
791};
792
793static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
794 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
795 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
796 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
797 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
798 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
799 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
800 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
801};
802
803static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
804 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
805 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
806 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
807 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
808 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
809 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
810 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
811 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
812 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
813 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
814 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
815 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
816 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
817 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
818 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
819 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
820 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
821 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
822 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
823 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
824 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
825 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
826 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
827 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
828 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
829 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
830 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
831 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
832 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
833 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
834 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
835 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
836 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
837 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
838 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
839 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
840};
841
842static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
843 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
844 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
845 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
846 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
847 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
848};
849
850static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
851 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
852 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
853 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
854 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
855 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
856 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
857 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
858 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
859 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
860};
861
862static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
863
864 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
865 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
866 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
867 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
868 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
869
870
871 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
872 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
873 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
874 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
875
876 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
877 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
878 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
879 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
880 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
881 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
882 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
883 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
884 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
885 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
886 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
887 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
888 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
889 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
890 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
891 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
892 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
893 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
894 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
895
896 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
897 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
898 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
899 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
900 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
901 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
902 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
903 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
904 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
905 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
906 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
907};
908
909static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
910 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
911 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
912 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
913 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
914 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
915 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
916 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
917 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
918 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
919 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
920 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
921 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
922 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
923 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
924 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
925 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
926 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
927 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
928 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
929 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
930 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
931 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
932 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
933 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
934 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
935 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
936 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
937 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
938 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
939 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
940 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
941 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
942 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
943 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
944 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
945 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
946};
947
948static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
949 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
950 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
951 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
952 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
953 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
954};
955
956static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
957 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
958 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
959 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
960 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
961 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
962 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
963 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
964 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
965 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
966 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
967 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
968};
969
970static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
971
972 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
973 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
974 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
975 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
976 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
977
978
979 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
980 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
981 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
982 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
983
984 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
985 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
986 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
987 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
988 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
989 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
990 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
991 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
992 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
993 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
994 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
995 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
996 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
997 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
998 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
999 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1000 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1001 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1002 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1003
1004 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1005 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1006 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1007 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1008 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1009 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1010 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1011 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1012 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1013 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1014 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1015
1016 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1017 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1018};
1019
1020static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1021 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1022 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1023 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1024 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1025 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1026 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1027 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1028 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1029 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1030 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1031 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1032 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1033 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1034 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1035 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1036 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1037 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1038 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1039 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1040 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1041 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1042 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1043 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1044 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1045 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1046 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1047 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1048 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1049 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1050 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1051 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1052 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1053 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1054 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1055 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1056 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1057
1058
1059 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1060};
1061
1062static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1063 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1064 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1065 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1066};
1067
1068static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1069 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1070 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1071 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1072 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1073 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1074 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1075 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1076 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1077 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1078 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1079 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1080 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1081 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1082 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1083 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1084 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1085};
1086
1087static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1088 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1089 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1090 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1091 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1092 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1093 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1094 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1095 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1096};
1097
1098static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1099 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1137};
1138
1139static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1140 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1141 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1142 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1143 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1144};
1145
1146static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1147 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1148 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1149 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1150 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1151 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1152 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1153 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1159 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1160 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1161 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1162 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1163 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1164};
1165
1166static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1205};
1206
1207static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1208 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1209 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1210 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1211 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1212 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1213 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1214 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1215 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1216 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1217 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1218 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1219 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1220 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1221 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1222 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1223 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1224 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1225 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1226 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1227 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1228 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1229 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1230 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1231 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1232
1233
1234 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1235};
1236
1237static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1238 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1239 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1240 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1241 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1242 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1243 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1244};
1245
1246static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1281
1282};
1283
1284static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1288 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1289 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1290 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1292};
1293
1294static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1295 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1296 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1297 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1298 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1299 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1300 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1301 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1302 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1303 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1304 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1305 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1306 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1307 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1308 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1309 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1310 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1311 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1312 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1313 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1314 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1315 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1316 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1317 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1318 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1319 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1320 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1321 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1322 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1323 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1324 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1325 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1326 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1327 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1328 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1329 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1330 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1331 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1332 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1333 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1334 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1335};
1336
1337static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1338 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1339 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1340 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1341 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1342 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1343};
1344
1345static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1346 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1347 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1348 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1349 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1350 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1351 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1352 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1353 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1354 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1355 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1356 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1357 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1358 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1359 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1360 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1361 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1362 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1363 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1364 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1365 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1366 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1367 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1368 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1369 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1370 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1371 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1372 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1373 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1374 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1375 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1376 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1377 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1378 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1379 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1380 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1381 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1382};
1383
1384static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1385
1386 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1387 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1388 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1389
1390 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1391 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1392 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1393 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1394 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1395 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1396 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1397 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1398 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1399 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1400};
1401
1402
1403struct qmp_phy_cfg {
1404
1405 unsigned int type;
1406
1407 int nlanes;
1408
1409
1410 const struct qmp_phy_init_tbl *serdes_tbl;
1411 int serdes_tbl_num;
1412 const struct qmp_phy_init_tbl *tx_tbl;
1413 int tx_tbl_num;
1414 const struct qmp_phy_init_tbl *rx_tbl;
1415 int rx_tbl_num;
1416 const struct qmp_phy_init_tbl *pcs_tbl;
1417 int pcs_tbl_num;
1418 const struct qmp_phy_init_tbl *pcs_misc_tbl;
1419 int pcs_misc_tbl_num;
1420
1421
1422 const char * const *clk_list;
1423 int num_clks;
1424
1425 const char * const *reset_list;
1426 int num_resets;
1427
1428 const char * const *vreg_list;
1429 int num_vregs;
1430
1431
1432 const unsigned int *regs;
1433
1434 unsigned int start_ctrl;
1435 unsigned int pwrdn_ctrl;
1436 unsigned int mask_com_pcs_ready;
1437
1438
1439 bool has_phy_com_ctrl;
1440
1441 bool has_lane_rst;
1442
1443 bool has_pwrdn_delay;
1444
1445 int pwrdn_delay_min;
1446 int pwrdn_delay_max;
1447
1448
1449 bool has_phy_dp_com_ctrl;
1450
1451 bool is_dual_lane_phy;
1452
1453
1454 bool no_pcs_sw_reset;
1455};
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472struct qmp_phy {
1473 struct phy *phy;
1474 void __iomem *tx;
1475 void __iomem *rx;
1476 void __iomem *pcs;
1477 void __iomem *tx2;
1478 void __iomem *rx2;
1479 void __iomem *pcs_misc;
1480 struct clk *pipe_clk;
1481 unsigned int index;
1482 struct qcom_qmp *qmp;
1483 struct reset_control *lane_rst;
1484};
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505struct qcom_qmp {
1506 struct device *dev;
1507 void __iomem *serdes;
1508 void __iomem *dp_com;
1509
1510 struct clk_bulk_data *clks;
1511 struct reset_control **resets;
1512 struct regulator_bulk_data *vregs;
1513
1514 const struct qmp_phy_cfg *cfg;
1515 struct qmp_phy **phys;
1516
1517 struct mutex phy_mutex;
1518 int init_count;
1519 bool phy_initialized;
1520 enum phy_mode mode;
1521
1522 struct reset_control *ufs_reset;
1523};
1524
1525static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1526{
1527 u32 reg;
1528
1529 reg = readl(base + offset);
1530 reg |= val;
1531 writel(reg, base + offset);
1532
1533
1534 readl(base + offset);
1535}
1536
1537static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1538{
1539 u32 reg;
1540
1541 reg = readl(base + offset);
1542 reg &= ~val;
1543 writel(reg, base + offset);
1544
1545
1546 readl(base + offset);
1547}
1548
1549
1550static const char * const msm8996_phy_clk_l[] = {
1551 "aux", "cfg_ahb", "ref",
1552};
1553
1554static const char * const msm8996_ufs_phy_clk_l[] = {
1555 "ref",
1556};
1557
1558static const char * const qmp_v3_phy_clk_l[] = {
1559 "aux", "cfg_ahb", "ref", "com_aux",
1560};
1561
1562static const char * const sdm845_pciephy_clk_l[] = {
1563 "aux", "cfg_ahb", "ref", "refgen",
1564};
1565
1566static const char * const qmp_v4_phy_clk_l[] = {
1567 "aux", "ref_clk_src", "ref", "com_aux",
1568};
1569
1570static const char * const sdm845_ufs_phy_clk_l[] = {
1571 "ref", "ref_aux",
1572};
1573
1574
1575static const char * const msm8996_pciephy_reset_l[] = {
1576 "phy", "common", "cfg",
1577};
1578
1579static const char * const msm8996_usb3phy_reset_l[] = {
1580 "phy", "common",
1581};
1582
1583static const char * const sc7180_usb3phy_reset_l[] = {
1584 "phy",
1585};
1586
1587static const char * const sdm845_pciephy_reset_l[] = {
1588 "phy",
1589};
1590
1591
1592static const char * const qmp_phy_vreg_l[] = {
1593 "vdda-phy", "vdda-pll",
1594};
1595
1596static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
1597 .type = PHY_TYPE_PCIE,
1598 .nlanes = 3,
1599
1600 .serdes_tbl = msm8996_pcie_serdes_tbl,
1601 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
1602 .tx_tbl = msm8996_pcie_tx_tbl,
1603 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
1604 .rx_tbl = msm8996_pcie_rx_tbl,
1605 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
1606 .pcs_tbl = msm8996_pcie_pcs_tbl,
1607 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
1608 .clk_list = msm8996_phy_clk_l,
1609 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1610 .reset_list = msm8996_pciephy_reset_l,
1611 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
1612 .vreg_list = qmp_phy_vreg_l,
1613 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1614 .regs = pciephy_regs_layout,
1615
1616 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
1617 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1618 .mask_com_pcs_ready = PCS_READY,
1619
1620 .has_phy_com_ctrl = true,
1621 .has_lane_rst = true,
1622 .has_pwrdn_delay = true,
1623 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1624 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1625};
1626
1627static const struct qmp_phy_cfg msm8996_ufs_cfg = {
1628 .type = PHY_TYPE_UFS,
1629 .nlanes = 1,
1630
1631 .serdes_tbl = msm8996_ufs_serdes_tbl,
1632 .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
1633 .tx_tbl = msm8996_ufs_tx_tbl,
1634 .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
1635 .rx_tbl = msm8996_ufs_rx_tbl,
1636 .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
1637
1638 .clk_list = msm8996_ufs_phy_clk_l,
1639 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
1640
1641 .vreg_list = qmp_phy_vreg_l,
1642 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1643
1644 .regs = msm8996_ufsphy_regs_layout,
1645
1646 .start_ctrl = SERDES_START,
1647 .pwrdn_ctrl = SW_PWRDN,
1648
1649 .no_pcs_sw_reset = true,
1650};
1651
1652static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1653 .type = PHY_TYPE_USB3,
1654 .nlanes = 1,
1655
1656 .serdes_tbl = msm8996_usb3_serdes_tbl,
1657 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1658 .tx_tbl = msm8996_usb3_tx_tbl,
1659 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1660 .rx_tbl = msm8996_usb3_rx_tbl,
1661 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1662 .pcs_tbl = msm8996_usb3_pcs_tbl,
1663 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1664 .clk_list = msm8996_phy_clk_l,
1665 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1666 .reset_list = msm8996_usb3phy_reset_l,
1667 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1668 .vreg_list = qmp_phy_vreg_l,
1669 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1670 .regs = usb3phy_regs_layout,
1671
1672 .start_ctrl = SERDES_START | PCS_START,
1673 .pwrdn_ctrl = SW_PWRDN,
1674};
1675
1676
1677static const char * const ipq8074_pciephy_reset_l[] = {
1678 "phy", "common",
1679};
1680
1681static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1682 .type = PHY_TYPE_PCIE,
1683 .nlanes = 1,
1684
1685 .serdes_tbl = ipq8074_pcie_serdes_tbl,
1686 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1687 .tx_tbl = ipq8074_pcie_tx_tbl,
1688 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1689 .rx_tbl = ipq8074_pcie_rx_tbl,
1690 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1691 .pcs_tbl = ipq8074_pcie_pcs_tbl,
1692 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1693 .clk_list = NULL,
1694 .num_clks = 0,
1695 .reset_list = ipq8074_pciephy_reset_l,
1696 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1697 .vreg_list = NULL,
1698 .num_vregs = 0,
1699 .regs = pciephy_regs_layout,
1700
1701 .start_ctrl = SERDES_START | PCS_START,
1702 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1703
1704 .has_phy_com_ctrl = false,
1705 .has_lane_rst = false,
1706 .has_pwrdn_delay = true,
1707 .pwrdn_delay_min = 995,
1708 .pwrdn_delay_max = 1005,
1709};
1710
1711static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
1712 .type = PHY_TYPE_PCIE,
1713 .nlanes = 1,
1714
1715 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
1716 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
1717 .tx_tbl = sdm845_qmp_pcie_tx_tbl,
1718 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
1719 .rx_tbl = sdm845_qmp_pcie_rx_tbl,
1720 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
1721 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
1722 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
1723 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
1724 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
1725 .clk_list = sdm845_pciephy_clk_l,
1726 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1727 .reset_list = sdm845_pciephy_reset_l,
1728 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1729 .vreg_list = qmp_phy_vreg_l,
1730 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1731 .regs = sdm845_qmp_pciephy_regs_layout,
1732
1733 .start_ctrl = PCS_START | SERDES_START,
1734 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1735
1736 .has_pwrdn_delay = true,
1737 .pwrdn_delay_min = 995,
1738 .pwrdn_delay_max = 1005,
1739};
1740
1741static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
1742 .type = PHY_TYPE_PCIE,
1743 .nlanes = 1,
1744
1745 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
1746 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
1747 .tx_tbl = sdm845_qhp_pcie_tx_tbl,
1748 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
1749 .rx_tbl = sdm845_qhp_pcie_rx_tbl,
1750 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
1751 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
1752 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
1753 .clk_list = sdm845_pciephy_clk_l,
1754 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1755 .reset_list = sdm845_pciephy_reset_l,
1756 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1757 .vreg_list = qmp_phy_vreg_l,
1758 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1759 .regs = sdm845_qhp_pciephy_regs_layout,
1760
1761 .start_ctrl = PCS_START | SERDES_START,
1762 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1763
1764 .has_pwrdn_delay = true,
1765 .pwrdn_delay_min = 995,
1766 .pwrdn_delay_max = 1005,
1767};
1768
1769static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1770 .type = PHY_TYPE_USB3,
1771 .nlanes = 1,
1772
1773 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1774 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1775 .tx_tbl = qmp_v3_usb3_tx_tbl,
1776 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1777 .rx_tbl = qmp_v3_usb3_rx_tbl,
1778 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1779 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1780 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1781 .clk_list = qmp_v3_phy_clk_l,
1782 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1783 .reset_list = msm8996_usb3phy_reset_l,
1784 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1785 .vreg_list = qmp_phy_vreg_l,
1786 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1787 .regs = qmp_v3_usb3phy_regs_layout,
1788
1789 .start_ctrl = SERDES_START | PCS_START,
1790 .pwrdn_ctrl = SW_PWRDN,
1791
1792 .has_pwrdn_delay = true,
1793 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1794 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1795
1796 .has_phy_dp_com_ctrl = true,
1797 .is_dual_lane_phy = true,
1798};
1799
1800static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
1801 .type = PHY_TYPE_USB3,
1802 .nlanes = 1,
1803
1804 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1805 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1806 .tx_tbl = qmp_v3_usb3_tx_tbl,
1807 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1808 .rx_tbl = qmp_v3_usb3_rx_tbl,
1809 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1810 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1811 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1812 .clk_list = qmp_v3_phy_clk_l,
1813 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1814 .reset_list = sc7180_usb3phy_reset_l,
1815 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1816 .vreg_list = qmp_phy_vreg_l,
1817 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1818 .regs = qmp_v3_usb3phy_regs_layout,
1819
1820 .start_ctrl = SERDES_START | PCS_START,
1821 .pwrdn_ctrl = SW_PWRDN,
1822
1823 .has_pwrdn_delay = true,
1824 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1825 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1826
1827 .has_phy_dp_com_ctrl = true,
1828 .is_dual_lane_phy = true,
1829};
1830
1831static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1832 .type = PHY_TYPE_USB3,
1833 .nlanes = 1,
1834
1835 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1836 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1837 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1838 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1839 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1840 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1841 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1842 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1843 .clk_list = qmp_v3_phy_clk_l,
1844 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1845 .reset_list = msm8996_usb3phy_reset_l,
1846 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1847 .vreg_list = qmp_phy_vreg_l,
1848 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1849 .regs = qmp_v3_usb3phy_regs_layout,
1850
1851 .start_ctrl = SERDES_START | PCS_START,
1852 .pwrdn_ctrl = SW_PWRDN,
1853
1854 .has_pwrdn_delay = true,
1855 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1856 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1857};
1858
1859static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1860 .type = PHY_TYPE_UFS,
1861 .nlanes = 2,
1862
1863 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
1864 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1865 .tx_tbl = sdm845_ufsphy_tx_tbl,
1866 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1867 .rx_tbl = sdm845_ufsphy_rx_tbl,
1868 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1869 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
1870 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1871 .clk_list = sdm845_ufs_phy_clk_l,
1872 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1873 .vreg_list = qmp_phy_vreg_l,
1874 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1875 .regs = sdm845_ufsphy_regs_layout,
1876
1877 .start_ctrl = SERDES_START,
1878 .pwrdn_ctrl = SW_PWRDN,
1879
1880 .is_dual_lane_phy = true,
1881 .no_pcs_sw_reset = true,
1882};
1883
1884static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
1885 .type = PHY_TYPE_PCIE,
1886 .nlanes = 1,
1887
1888 .serdes_tbl = msm8998_pcie_serdes_tbl,
1889 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
1890 .tx_tbl = msm8998_pcie_tx_tbl,
1891 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
1892 .rx_tbl = msm8998_pcie_rx_tbl,
1893 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
1894 .pcs_tbl = msm8998_pcie_pcs_tbl,
1895 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
1896 .clk_list = msm8996_phy_clk_l,
1897 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1898 .reset_list = ipq8074_pciephy_reset_l,
1899 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1900 .vreg_list = qmp_phy_vreg_l,
1901 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1902 .regs = pciephy_regs_layout,
1903
1904 .start_ctrl = SERDES_START | PCS_START,
1905 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1906};
1907
1908static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1909 .type = PHY_TYPE_USB3,
1910 .nlanes = 1,
1911
1912 .serdes_tbl = msm8998_usb3_serdes_tbl,
1913 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1914 .tx_tbl = msm8998_usb3_tx_tbl,
1915 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1916 .rx_tbl = msm8998_usb3_rx_tbl,
1917 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1918 .pcs_tbl = msm8998_usb3_pcs_tbl,
1919 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1920 .clk_list = msm8996_phy_clk_l,
1921 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1922 .reset_list = msm8996_usb3phy_reset_l,
1923 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1924 .vreg_list = qmp_phy_vreg_l,
1925 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1926 .regs = qmp_v3_usb3phy_regs_layout,
1927
1928 .start_ctrl = SERDES_START | PCS_START,
1929 .pwrdn_ctrl = SW_PWRDN,
1930
1931 .is_dual_lane_phy = true,
1932};
1933
1934static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1935 .type = PHY_TYPE_UFS,
1936 .nlanes = 2,
1937
1938 .serdes_tbl = sm8150_ufsphy_serdes_tbl,
1939 .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
1940 .tx_tbl = sm8150_ufsphy_tx_tbl,
1941 .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
1942 .rx_tbl = sm8150_ufsphy_rx_tbl,
1943 .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
1944 .pcs_tbl = sm8150_ufsphy_pcs_tbl,
1945 .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
1946 .clk_list = sdm845_ufs_phy_clk_l,
1947 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1948 .vreg_list = qmp_phy_vreg_l,
1949 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1950 .regs = sm8150_ufsphy_regs_layout,
1951
1952 .start_ctrl = SERDES_START,
1953 .pwrdn_ctrl = SW_PWRDN,
1954
1955 .is_dual_lane_phy = true,
1956};
1957
1958static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
1959 .type = PHY_TYPE_USB3,
1960 .nlanes = 1,
1961
1962 .serdes_tbl = sm8150_usb3_serdes_tbl,
1963 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1964 .tx_tbl = sm8150_usb3_tx_tbl,
1965 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1966 .rx_tbl = sm8150_usb3_rx_tbl,
1967 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1968 .pcs_tbl = sm8150_usb3_pcs_tbl,
1969 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1970 .clk_list = qmp_v4_phy_clk_l,
1971 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1972 .reset_list = msm8996_usb3phy_reset_l,
1973 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1974 .vreg_list = qmp_phy_vreg_l,
1975 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1976 .regs = qmp_v4_usb3phy_regs_layout,
1977
1978 .start_ctrl = SERDES_START | PCS_START,
1979 .pwrdn_ctrl = SW_PWRDN,
1980
1981 .has_pwrdn_delay = true,
1982 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1983 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1984
1985 .has_phy_dp_com_ctrl = true,
1986 .is_dual_lane_phy = true,
1987};
1988
1989static void qcom_qmp_phy_configure(void __iomem *base,
1990 const unsigned int *regs,
1991 const struct qmp_phy_init_tbl tbl[],
1992 int num)
1993{
1994 int i;
1995 const struct qmp_phy_init_tbl *t = tbl;
1996
1997 if (!t)
1998 return;
1999
2000 for (i = 0; i < num; i++, t++) {
2001 if (t->in_layout)
2002 writel(t->val, base + regs[t->offset]);
2003 else
2004 writel(t->val, base + t->offset);
2005 }
2006}
2007
2008static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
2009{
2010 struct qcom_qmp *qmp = qphy->qmp;
2011 const struct qmp_phy_cfg *cfg = qmp->cfg;
2012 void __iomem *serdes = qmp->serdes;
2013 void __iomem *pcs = qphy->pcs;
2014 void __iomem *dp_com = qmp->dp_com;
2015 int ret, i;
2016
2017 mutex_lock(&qmp->phy_mutex);
2018 if (qmp->init_count++) {
2019 mutex_unlock(&qmp->phy_mutex);
2020 return 0;
2021 }
2022
2023
2024 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2025 if (ret) {
2026 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2027 goto err_reg_enable;
2028 }
2029
2030 for (i = 0; i < cfg->num_resets; i++) {
2031 ret = reset_control_assert(qmp->resets[i]);
2032 if (ret) {
2033 dev_err(qmp->dev, "%s reset assert failed\n",
2034 cfg->reset_list[i]);
2035 goto err_rst_assert;
2036 }
2037 }
2038
2039 for (i = cfg->num_resets - 1; i >= 0; i--) {
2040 ret = reset_control_deassert(qmp->resets[i]);
2041 if (ret) {
2042 dev_err(qmp->dev, "%s reset deassert failed\n",
2043 qmp->cfg->reset_list[i]);
2044 goto err_rst;
2045 }
2046 }
2047
2048 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2049 if (ret) {
2050 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
2051 goto err_rst;
2052 }
2053
2054 if (cfg->has_phy_dp_com_ctrl) {
2055 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
2056 SW_PWRDN);
2057
2058 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2059 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2060 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2061
2062 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
2063 USB3_MODE | DP_MODE);
2064
2065
2066 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2067 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2068 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2069 }
2070
2071 if (cfg->has_phy_com_ctrl) {
2072 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
2073 SW_PWRDN);
2074 } else {
2075 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
2076 qphy_setbits(pcs,
2077 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2078 cfg->pwrdn_ctrl);
2079 else
2080 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
2081 cfg->pwrdn_ctrl);
2082 }
2083
2084
2085 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
2086 cfg->serdes_tbl_num);
2087
2088 if (cfg->has_phy_com_ctrl) {
2089 void __iomem *status;
2090 unsigned int mask, val;
2091
2092 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
2093 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
2094 SERDES_START | PCS_START);
2095
2096 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
2097 mask = cfg->mask_com_pcs_ready;
2098
2099 ret = readl_poll_timeout(status, val, (val & mask), 10,
2100 PHY_INIT_COMPLETE_TIMEOUT);
2101 if (ret) {
2102 dev_err(qmp->dev,
2103 "phy common block init timed-out\n");
2104 goto err_com_init;
2105 }
2106 }
2107
2108 mutex_unlock(&qmp->phy_mutex);
2109
2110 return 0;
2111
2112err_com_init:
2113 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2114err_rst:
2115 while (++i < cfg->num_resets)
2116 reset_control_assert(qmp->resets[i]);
2117err_rst_assert:
2118 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2119err_reg_enable:
2120 mutex_unlock(&qmp->phy_mutex);
2121
2122 return ret;
2123}
2124
2125static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
2126{
2127 const struct qmp_phy_cfg *cfg = qmp->cfg;
2128 void __iomem *serdes = qmp->serdes;
2129 int i = cfg->num_resets;
2130
2131 mutex_lock(&qmp->phy_mutex);
2132 if (--qmp->init_count) {
2133 mutex_unlock(&qmp->phy_mutex);
2134 return 0;
2135 }
2136
2137 reset_control_assert(qmp->ufs_reset);
2138 if (cfg->has_phy_com_ctrl) {
2139 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
2140 SERDES_START | PCS_START);
2141 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
2142 SW_RESET);
2143 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
2144 SW_PWRDN);
2145 }
2146
2147 while (--i >= 0)
2148 reset_control_assert(qmp->resets[i]);
2149
2150 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2151
2152 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2153
2154 mutex_unlock(&qmp->phy_mutex);
2155
2156 return 0;
2157}
2158
2159static int qcom_qmp_phy_enable(struct phy *phy)
2160{
2161 struct qmp_phy *qphy = phy_get_drvdata(phy);
2162 struct qcom_qmp *qmp = qphy->qmp;
2163 const struct qmp_phy_cfg *cfg = qmp->cfg;
2164 void __iomem *tx = qphy->tx;
2165 void __iomem *rx = qphy->rx;
2166 void __iomem *pcs = qphy->pcs;
2167 void __iomem *pcs_misc = qphy->pcs_misc;
2168 void __iomem *dp_com = qmp->dp_com;
2169 void __iomem *status;
2170 unsigned int mask, val, ready;
2171 int ret;
2172
2173 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
2174
2175 if (cfg->no_pcs_sw_reset) {
2176
2177
2178
2179
2180
2181 if (!qmp->ufs_reset) {
2182 qmp->ufs_reset =
2183 devm_reset_control_get_exclusive(qmp->dev,
2184 "ufsphy");
2185
2186 if (IS_ERR(qmp->ufs_reset)) {
2187 ret = PTR_ERR(qmp->ufs_reset);
2188 dev_err(qmp->dev,
2189 "failed to get UFS reset: %d\n",
2190 ret);
2191
2192 qmp->ufs_reset = NULL;
2193 return ret;
2194 }
2195 }
2196
2197 ret = reset_control_assert(qmp->ufs_reset);
2198 if (ret)
2199 goto err_lane_rst;
2200 }
2201
2202 ret = qcom_qmp_phy_com_init(qphy);
2203 if (ret)
2204 return ret;
2205
2206 if (cfg->has_lane_rst) {
2207 ret = reset_control_deassert(qphy->lane_rst);
2208 if (ret) {
2209 dev_err(qmp->dev, "lane%d reset deassert failed\n",
2210 qphy->index);
2211 goto err_lane_rst;
2212 }
2213 }
2214
2215 ret = clk_prepare_enable(qphy->pipe_clk);
2216 if (ret) {
2217 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2218 goto err_clk_enable;
2219 }
2220
2221
2222 qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
2223
2224 if (cfg->is_dual_lane_phy)
2225 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
2226 cfg->tx_tbl, cfg->tx_tbl_num);
2227
2228 qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
2229 if (cfg->is_dual_lane_phy)
2230 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
2231 cfg->rx_tbl, cfg->rx_tbl_num);
2232
2233 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2234 ret = reset_control_deassert(qmp->ufs_reset);
2235 if (ret)
2236 goto err_lane_rst;
2237
2238 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
2239 cfg->pcs_misc_tbl_num);
2240
2241
2242
2243
2244
2245 if(cfg->type == PHY_TYPE_PCIE)
2246 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
2247
2248 if (cfg->has_pwrdn_delay)
2249 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
2250
2251
2252 if (!cfg->no_pcs_sw_reset)
2253 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2254
2255 if (cfg->has_phy_dp_com_ctrl)
2256 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2257
2258
2259 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2260
2261 if (cfg->type == PHY_TYPE_UFS) {
2262 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
2263 mask = PCS_READY;
2264 ready = PCS_READY;
2265 } else {
2266 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2267 mask = PHYSTATUS;
2268 ready = 0;
2269 }
2270
2271 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
2272 PHY_INIT_COMPLETE_TIMEOUT);
2273 if (ret) {
2274 dev_err(qmp->dev, "phy initialization timed-out\n");
2275 goto err_pcs_ready;
2276 }
2277 qmp->phy_initialized = true;
2278 return 0;
2279
2280err_pcs_ready:
2281 reset_control_assert(qmp->ufs_reset);
2282 clk_disable_unprepare(qphy->pipe_clk);
2283err_clk_enable:
2284 if (cfg->has_lane_rst)
2285 reset_control_assert(qphy->lane_rst);
2286err_lane_rst:
2287 qcom_qmp_phy_com_exit(qmp);
2288
2289 return ret;
2290}
2291
2292static int qcom_qmp_phy_disable(struct phy *phy)
2293{
2294 struct qmp_phy *qphy = phy_get_drvdata(phy);
2295 struct qcom_qmp *qmp = qphy->qmp;
2296 const struct qmp_phy_cfg *cfg = qmp->cfg;
2297
2298 clk_disable_unprepare(qphy->pipe_clk);
2299
2300
2301 if (!cfg->no_pcs_sw_reset)
2302 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2303
2304
2305 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2306
2307
2308 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
2309 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2310 cfg->pwrdn_ctrl);
2311 } else {
2312 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
2313 cfg->pwrdn_ctrl);
2314 }
2315
2316 if (cfg->has_lane_rst)
2317 reset_control_assert(qphy->lane_rst);
2318
2319 qcom_qmp_phy_com_exit(qmp);
2320
2321 qmp->phy_initialized = false;
2322
2323 return 0;
2324}
2325
2326static int qcom_qmp_phy_set_mode(struct phy *phy,
2327 enum phy_mode mode, int submode)
2328{
2329 struct qmp_phy *qphy = phy_get_drvdata(phy);
2330 struct qcom_qmp *qmp = qphy->qmp;
2331
2332 qmp->mode = mode;
2333
2334 return 0;
2335}
2336
2337static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
2338{
2339 struct qcom_qmp *qmp = qphy->qmp;
2340 const struct qmp_phy_cfg *cfg = qmp->cfg;
2341 void __iomem *pcs = qphy->pcs;
2342 void __iomem *pcs_misc = qphy->pcs_misc;
2343 u32 intr_mask;
2344
2345 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2346 qmp->mode == PHY_MODE_USB_DEVICE_SS)
2347 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2348 else
2349 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2350
2351
2352 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2353
2354 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2355
2356 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2357 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2358
2359
2360 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2361
2362
2363 if (pcs_misc)
2364 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2365}
2366
2367static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
2368{
2369 struct qcom_qmp *qmp = qphy->qmp;
2370 const struct qmp_phy_cfg *cfg = qmp->cfg;
2371 void __iomem *pcs = qphy->pcs;
2372 void __iomem *pcs_misc = qphy->pcs_misc;
2373
2374
2375 if (pcs_misc)
2376 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2377
2378 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2379 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2380
2381 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2382
2383 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2384}
2385
2386static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
2387{
2388 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2389 struct qmp_phy *qphy = qmp->phys[0];
2390 const struct qmp_phy_cfg *cfg = qmp->cfg;
2391
2392 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2393
2394
2395 if (cfg->type != PHY_TYPE_USB3)
2396 return 0;
2397
2398 if (!qmp->phy_initialized) {
2399 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2400 return 0;
2401 }
2402
2403 qcom_qmp_phy_enable_autonomous_mode(qphy);
2404
2405 clk_disable_unprepare(qphy->pipe_clk);
2406 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2407
2408 return 0;
2409}
2410
2411static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
2412{
2413 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2414 struct qmp_phy *qphy = qmp->phys[0];
2415 const struct qmp_phy_cfg *cfg = qmp->cfg;
2416 int ret = 0;
2417
2418 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2419
2420
2421 if (cfg->type != PHY_TYPE_USB3)
2422 return 0;
2423
2424 if (!qmp->phy_initialized) {
2425 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2426 return 0;
2427 }
2428
2429 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2430 if (ret) {
2431 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
2432 return ret;
2433 }
2434
2435 ret = clk_prepare_enable(qphy->pipe_clk);
2436 if (ret) {
2437 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2438 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2439 return ret;
2440 }
2441
2442 qcom_qmp_phy_disable_autonomous_mode(qphy);
2443
2444 return 0;
2445}
2446
2447static int qcom_qmp_phy_vreg_init(struct device *dev)
2448{
2449 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2450 int num = qmp->cfg->num_vregs;
2451 int i;
2452
2453 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2454 if (!qmp->vregs)
2455 return -ENOMEM;
2456
2457 for (i = 0; i < num; i++)
2458 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
2459
2460 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2461}
2462
2463static int qcom_qmp_phy_reset_init(struct device *dev)
2464{
2465 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2466 int i;
2467
2468 qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
2469 sizeof(*qmp->resets), GFP_KERNEL);
2470 if (!qmp->resets)
2471 return -ENOMEM;
2472
2473 for (i = 0; i < qmp->cfg->num_resets; i++) {
2474 struct reset_control *rst;
2475 const char *name = qmp->cfg->reset_list[i];
2476
2477 rst = devm_reset_control_get(dev, name);
2478 if (IS_ERR(rst)) {
2479 dev_err(dev, "failed to get %s reset\n", name);
2480 return PTR_ERR(rst);
2481 }
2482 qmp->resets[i] = rst;
2483 }
2484
2485 return 0;
2486}
2487
2488static int qcom_qmp_phy_clk_init(struct device *dev)
2489{
2490 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2491 int num = qmp->cfg->num_clks;
2492 int i;
2493
2494 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2495 if (!qmp->clks)
2496 return -ENOMEM;
2497
2498 for (i = 0; i < num; i++)
2499 qmp->clks[i].id = qmp->cfg->clk_list[i];
2500
2501 return devm_clk_bulk_get(dev, num, qmp->clks);
2502}
2503
2504static void phy_pipe_clk_release_provider(void *res)
2505{
2506 of_clk_del_provider(res);
2507}
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
2528{
2529 struct clk_fixed_rate *fixed;
2530 struct clk_init_data init = { };
2531 int ret;
2532
2533 if ((qmp->cfg->type != PHY_TYPE_USB3) &&
2534 (qmp->cfg->type != PHY_TYPE_PCIE)) {
2535
2536 return 0;
2537 }
2538
2539 ret = of_property_read_string(np, "clock-output-names", &init.name);
2540 if (ret) {
2541 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2542 return ret;
2543 }
2544
2545 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
2546 if (!fixed)
2547 return -ENOMEM;
2548
2549 init.ops = &clk_fixed_rate_ops;
2550
2551
2552 fixed->fixed_rate = 125000000;
2553 fixed->hw.init = &init;
2554
2555 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2556 if (ret)
2557 return ret;
2558
2559 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2560 if (ret)
2561 return ret;
2562
2563
2564
2565
2566
2567 ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
2568 if (ret)
2569 phy_pipe_clk_release_provider(np);
2570
2571 return ret;
2572}
2573
2574static const struct phy_ops qcom_qmp_phy_gen_ops = {
2575 .init = qcom_qmp_phy_enable,
2576 .exit = qcom_qmp_phy_disable,
2577 .set_mode = qcom_qmp_phy_set_mode,
2578 .owner = THIS_MODULE,
2579};
2580
2581static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
2582 .power_on = qcom_qmp_phy_enable,
2583 .power_off = qcom_qmp_phy_disable,
2584 .set_mode = qcom_qmp_phy_set_mode,
2585 .owner = THIS_MODULE,
2586};
2587
2588static
2589int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
2590{
2591 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2592 struct phy *generic_phy;
2593 struct qmp_phy *qphy;
2594 const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
2595 char prop_name[MAX_PROP_NAME];
2596 int ret;
2597
2598 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
2599 if (!qphy)
2600 return -ENOMEM;
2601
2602
2603
2604
2605
2606
2607
2608 qphy->tx = of_iomap(np, 0);
2609 if (!qphy->tx)
2610 return -ENOMEM;
2611
2612 qphy->rx = of_iomap(np, 1);
2613 if (!qphy->rx)
2614 return -ENOMEM;
2615
2616 qphy->pcs = of_iomap(np, 2);
2617 if (!qphy->pcs)
2618 return -ENOMEM;
2619
2620
2621
2622
2623
2624
2625
2626 if (qmp->cfg->is_dual_lane_phy) {
2627 qphy->tx2 = of_iomap(np, 3);
2628 qphy->rx2 = of_iomap(np, 4);
2629 if (!qphy->tx2 || !qphy->rx2) {
2630 dev_warn(dev,
2631 "Underspecified device tree, falling back to legacy register regions\n");
2632
2633
2634 qphy->pcs_misc = qphy->tx2;
2635 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
2636 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
2637
2638 } else {
2639 qphy->pcs_misc = of_iomap(np, 5);
2640 }
2641
2642 } else {
2643 qphy->pcs_misc = of_iomap(np, 3);
2644 }
2645
2646 if (!qphy->pcs_misc)
2647 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2648
2649
2650
2651
2652
2653
2654
2655
2656 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
2657 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
2658 if (IS_ERR(qphy->pipe_clk)) {
2659 if (qmp->cfg->type == PHY_TYPE_PCIE ||
2660 qmp->cfg->type == PHY_TYPE_USB3) {
2661 ret = PTR_ERR(qphy->pipe_clk);
2662 if (ret != -EPROBE_DEFER)
2663 dev_err(dev,
2664 "failed to get lane%d pipe_clk, %d\n",
2665 id, ret);
2666 return ret;
2667 }
2668 qphy->pipe_clk = NULL;
2669 }
2670
2671
2672 if (qmp->cfg->has_lane_rst) {
2673 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
2674 qphy->lane_rst = of_reset_control_get(np, prop_name);
2675 if (IS_ERR(qphy->lane_rst)) {
2676 dev_err(dev, "failed to get lane%d reset\n", id);
2677 return PTR_ERR(qphy->lane_rst);
2678 }
2679 }
2680
2681 if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE)
2682 ops = &qcom_qmp_pcie_ufs_ops;
2683
2684 generic_phy = devm_phy_create(dev, np, ops);
2685 if (IS_ERR(generic_phy)) {
2686 ret = PTR_ERR(generic_phy);
2687 dev_err(dev, "failed to create qphy %d\n", ret);
2688 return ret;
2689 }
2690
2691 qphy->phy = generic_phy;
2692 qphy->index = id;
2693 qphy->qmp = qmp;
2694 qmp->phys[id] = qphy;
2695 phy_set_drvdata(generic_phy, qphy);
2696
2697 return 0;
2698}
2699
2700static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
2701 {
2702 .compatible = "qcom,msm8996-qmp-pcie-phy",
2703 .data = &msm8996_pciephy_cfg,
2704 }, {
2705 .compatible = "qcom,msm8996-qmp-ufs-phy",
2706 .data = &msm8996_ufs_cfg,
2707 }, {
2708 .compatible = "qcom,msm8996-qmp-usb3-phy",
2709 .data = &msm8996_usb3phy_cfg,
2710 }, {
2711 .compatible = "qcom,msm8998-qmp-pcie-phy",
2712 .data = &msm8998_pciephy_cfg,
2713 }, {
2714 .compatible = "qcom,msm8998-qmp-ufs-phy",
2715 .data = &sdm845_ufsphy_cfg,
2716 }, {
2717 .compatible = "qcom,ipq8074-qmp-pcie-phy",
2718 .data = &ipq8074_pciephy_cfg,
2719 }, {
2720 .compatible = "qcom,sc7180-qmp-usb3-phy",
2721 .data = &sc7180_usb3phy_cfg,
2722 }, {
2723 .compatible = "qcom,sdm845-qhp-pcie-phy",
2724 .data = &sdm845_qhp_pciephy_cfg,
2725 }, {
2726 .compatible = "qcom,sdm845-qmp-pcie-phy",
2727 .data = &sdm845_qmp_pciephy_cfg,
2728 }, {
2729 .compatible = "qcom,sdm845-qmp-usb3-phy",
2730 .data = &qmp_v3_usb3phy_cfg,
2731 }, {
2732 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2733 .data = &qmp_v3_usb3_uniphy_cfg,
2734 }, {
2735 .compatible = "qcom,sdm845-qmp-ufs-phy",
2736 .data = &sdm845_ufsphy_cfg,
2737 }, {
2738 .compatible = "qcom,msm8998-qmp-usb3-phy",
2739 .data = &msm8998_usb3phy_cfg,
2740 }, {
2741 .compatible = "qcom,sm8150-qmp-ufs-phy",
2742 .data = &sm8150_ufsphy_cfg,
2743 }, {
2744 .compatible = "qcom,sm8250-qmp-ufs-phy",
2745 .data = &sm8150_ufsphy_cfg,
2746 }, {
2747 .compatible = "qcom,sm8150-qmp-usb3-phy",
2748 .data = &sm8150_usb3phy_cfg,
2749 },
2750 { },
2751};
2752MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
2753
2754static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
2755 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
2756 qcom_qmp_phy_runtime_resume, NULL)
2757};
2758
2759static int qcom_qmp_phy_probe(struct platform_device *pdev)
2760{
2761 struct qcom_qmp *qmp;
2762 struct device *dev = &pdev->dev;
2763 struct resource *res;
2764 struct device_node *child;
2765 struct phy_provider *phy_provider;
2766 void __iomem *base;
2767 int num, id;
2768 int ret;
2769
2770 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2771 if (!qmp)
2772 return -ENOMEM;
2773
2774 qmp->dev = dev;
2775 dev_set_drvdata(dev, qmp);
2776
2777
2778 qmp->cfg = of_device_get_match_data(dev);
2779 if (!qmp->cfg)
2780 return -EINVAL;
2781
2782 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2783 base = devm_ioremap_resource(dev, res);
2784 if (IS_ERR(base))
2785 return PTR_ERR(base);
2786
2787
2788 qmp->serdes = base;
2789
2790
2791 if (qmp->cfg->has_phy_dp_com_ctrl) {
2792 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2793 "dp_com");
2794 base = devm_ioremap_resource(dev, res);
2795 if (IS_ERR(base))
2796 return PTR_ERR(base);
2797
2798 qmp->dp_com = base;
2799 }
2800
2801 mutex_init(&qmp->phy_mutex);
2802
2803 ret = qcom_qmp_phy_clk_init(dev);
2804 if (ret)
2805 return ret;
2806
2807 ret = qcom_qmp_phy_reset_init(dev);
2808 if (ret)
2809 return ret;
2810
2811 ret = qcom_qmp_phy_vreg_init(dev);
2812 if (ret) {
2813 if (ret != -EPROBE_DEFER)
2814 dev_err(dev, "failed to get regulator supplies: %d\n",
2815 ret);
2816 return ret;
2817 }
2818
2819 num = of_get_available_child_count(dev->of_node);
2820
2821 if (num > qmp->cfg->nlanes)
2822 return -EINVAL;
2823
2824 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2825 if (!qmp->phys)
2826 return -ENOMEM;
2827
2828 id = 0;
2829 pm_runtime_set_active(dev);
2830 pm_runtime_enable(dev);
2831
2832
2833
2834
2835 pm_runtime_forbid(dev);
2836
2837 for_each_available_child_of_node(dev->of_node, child) {
2838
2839 ret = qcom_qmp_phy_create(dev, child, id);
2840 if (ret) {
2841 dev_err(dev, "failed to create lane%d phy, %d\n",
2842 id, ret);
2843 goto err_node_put;
2844 }
2845
2846
2847
2848
2849
2850 ret = phy_pipe_clk_register(qmp, child);
2851 if (ret) {
2852 dev_err(qmp->dev,
2853 "failed to register pipe clock source\n");
2854 goto err_node_put;
2855 }
2856 id++;
2857 }
2858
2859 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2860 if (!IS_ERR(phy_provider))
2861 dev_info(dev, "Registered Qcom-QMP phy\n");
2862 else
2863 pm_runtime_disable(dev);
2864
2865 return PTR_ERR_OR_ZERO(phy_provider);
2866
2867err_node_put:
2868 pm_runtime_disable(dev);
2869 of_node_put(child);
2870 return ret;
2871}
2872
2873static struct platform_driver qcom_qmp_phy_driver = {
2874 .probe = qcom_qmp_phy_probe,
2875 .driver = {
2876 .name = "qcom-qmp-phy",
2877 .pm = &qcom_qmp_phy_pm_ops,
2878 .of_match_table = qcom_qmp_phy_of_match_table,
2879 },
2880};
2881
2882module_platform_driver(qcom_qmp_phy_driver);
2883
2884MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2885MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
2886MODULE_LICENSE("GPL v2");
2887
