1
2
3
4
5
6
7
8
9
10
11
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27
28#include "../core.h"
29#include "../pinctrl-utils.h"
30#include "pinctrl-owl.h"
31
32
33
34
35
36
37
38
39
40
41struct owl_pinctrl {
42 struct device *dev;
43 struct pinctrl_dev *pctrldev;
44 struct gpio_chip chip;
45 raw_spinlock_t lock;
46 struct clk *clk;
47 const struct owl_pinctrl_soc_data *soc;
48 void __iomem *base;
49 struct irq_chip irq_chip;
50 unsigned int num_irq;
51 unsigned int *irq;
52};
53
54static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
55{
56 u32 reg_val;
57
58 reg_val = readl_relaxed(base);
59
60 reg_val = (reg_val & ~mask) | (val & mask);
61
62 writel_relaxed(reg_val, base);
63}
64
65static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
66 u32 bit, u32 width)
67{
68 u32 tmp, mask;
69
70 tmp = readl_relaxed(pctrl->base + reg);
71 mask = (1 << width) - 1;
72
73 return (tmp >> bit) & mask;
74}
75
76static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
77 u32 bit, u32 width)
78{
79 u32 mask;
80
81 mask = (1 << width) - 1;
82 mask = mask << bit;
83
84 owl_update_bits(pctrl->base + reg, mask, (arg << bit));
85}
86
87static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
88{
89 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
90
91 return pctrl->soc->ngroups;
92}
93
94static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
95 unsigned int group)
96{
97 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
98
99 return pctrl->soc->groups[group].name;
100}
101
102static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
103 unsigned int group,
104 const unsigned int **pins,
105 unsigned int *num_pins)
106{
107 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
108
109 *pins = pctrl->soc->groups[group].pads;
110 *num_pins = pctrl->soc->groups[group].npads;
111
112 return 0;
113}
114
115static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
116 struct seq_file *s,
117 unsigned int offset)
118{
119 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
120
121 seq_printf(s, "%s", dev_name(pctrl->dev));
122}
123
124static struct pinctrl_ops owl_pinctrl_ops = {
125 .get_groups_count = owl_get_groups_count,
126 .get_group_name = owl_get_group_name,
127 .get_group_pins = owl_get_group_pins,
128 .pin_dbg_show = owl_pin_dbg_show,
129 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
130 .dt_free_map = pinctrl_utils_free_map,
131};
132
133static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
134{
135 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
136
137 return pctrl->soc->nfunctions;
138}
139
140static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
141 unsigned int function)
142{
143 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
144
145 return pctrl->soc->functions[function].name;
146}
147
148static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
149 unsigned int function,
150 const char * const **groups,
151 unsigned int * const num_groups)
152{
153 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
154
155 *groups = pctrl->soc->functions[function].groups;
156 *num_groups = pctrl->soc->functions[function].ngroups;
157
158 return 0;
159}
160
161static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
162 int function,
163 u32 *mask,
164 u32 *val)
165{
166 int id;
167 u32 option_num;
168 u32 option_mask;
169
170 for (id = 0; id < g->nfuncs; id++) {
171 if (g->funcs[id] == function)
172 break;
173 }
174 if (WARN_ON(id == g->nfuncs))
175 return -EINVAL;
176
177 option_num = (1 << g->mfpctl_width);
178 if (id > option_num)
179 id -= option_num;
180
181 option_mask = option_num - 1;
182 *mask = (option_mask << g->mfpctl_shift);
183 *val = (id << g->mfpctl_shift);
184
185 return 0;
186}
187
188static int owl_set_mux(struct pinctrl_dev *pctrldev,
189 unsigned int function,
190 unsigned int group)
191{
192 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
193 const struct owl_pingroup *g;
194 unsigned long flags;
195 u32 val, mask;
196
197 g = &pctrl->soc->groups[group];
198
199 if (get_group_mfp_mask_val(g, function, &mask, &val))
200 return -EINVAL;
201
202 raw_spin_lock_irqsave(&pctrl->lock, flags);
203
204 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
205
206 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
207
208 return 0;
209}
210
211static struct pinmux_ops owl_pinmux_ops = {
212 .get_functions_count = owl_get_funcs_count,
213 .get_function_name = owl_get_func_name,
214 .get_function_groups = owl_get_func_groups,
215 .set_mux = owl_set_mux,
216};
217
218static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
219 unsigned int param,
220 u32 *reg,
221 u32 *bit,
222 u32 *width)
223{
224 switch (param) {
225 case PIN_CONFIG_BIAS_BUS_HOLD:
226 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
227 case PIN_CONFIG_BIAS_PULL_DOWN:
228 case PIN_CONFIG_BIAS_PULL_UP:
229 if (!info->pullctl)
230 return -EINVAL;
231 *reg = info->pullctl->reg;
232 *bit = info->pullctl->shift;
233 *width = info->pullctl->width;
234 break;
235 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
236 if (!info->st)
237 return -EINVAL;
238 *reg = info->st->reg;
239 *bit = info->st->shift;
240 *width = info->st->width;
241 break;
242 default:
243 return -ENOTSUPP;
244 }
245
246 return 0;
247}
248
249static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
250 unsigned int pin,
251 unsigned long *config)
252{
253 int ret = 0;
254 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
255 const struct owl_padinfo *info;
256 unsigned int param = pinconf_to_config_param(*config);
257 u32 reg, bit, width, arg;
258
259 info = &pctrl->soc->padinfo[pin];
260
261 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
262 if (ret)
263 return ret;
264
265 arg = owl_read_field(pctrl, reg, bit, width);
266
267 if (!pctrl->soc->padctl_val2arg)
268 return -ENOTSUPP;
269
270 ret = pctrl->soc->padctl_val2arg(info, param, &arg);
271 if (ret)
272 return ret;
273
274 *config = pinconf_to_config_packed(param, arg);
275
276 return ret;
277}
278
279static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
280 unsigned int pin,
281 unsigned long *configs,
282 unsigned int num_configs)
283{
284 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
285 const struct owl_padinfo *info;
286 unsigned long flags;
287 unsigned int param;
288 u32 reg, bit, width, arg;
289 int ret = 0, i;
290
291 info = &pctrl->soc->padinfo[pin];
292
293 for (i = 0; i < num_configs; i++) {
294 param = pinconf_to_config_param(configs[i]);
295 arg = pinconf_to_config_argument(configs[i]);
296
297 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
298 if (ret)
299 return ret;
300
301 if (!pctrl->soc->padctl_arg2val)
302 return -ENOTSUPP;
303
304 ret = pctrl->soc->padctl_arg2val(info, param, &arg);
305 if (ret)
306 return ret;
307
308 raw_spin_lock_irqsave(&pctrl->lock, flags);
309
310 owl_write_field(pctrl, reg, arg, bit, width);
311
312 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
313 }
314
315 return ret;
316}
317
318static int owl_group_pinconf_reg(const struct owl_pingroup *g,
319 unsigned int param,
320 u32 *reg,
321 u32 *bit,
322 u32 *width)
323{
324 switch (param) {
325 case PIN_CONFIG_DRIVE_STRENGTH:
326 if (g->drv_reg < 0)
327 return -EINVAL;
328 *reg = g->drv_reg;
329 *bit = g->drv_shift;
330 *width = g->drv_width;
331 break;
332 case PIN_CONFIG_SLEW_RATE:
333 if (g->sr_reg < 0)
334 return -EINVAL;
335 *reg = g->sr_reg;
336 *bit = g->sr_shift;
337 *width = g->sr_width;
338 break;
339 default:
340 return -ENOTSUPP;
341 }
342
343 return 0;
344}
345
346static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
347 unsigned int param,
348 u32 *arg)
349{
350 switch (param) {
351 case PIN_CONFIG_DRIVE_STRENGTH:
352 switch (*arg) {
353 case 2:
354 *arg = OWL_PINCONF_DRV_2MA;
355 break;
356 case 4:
357 *arg = OWL_PINCONF_DRV_4MA;
358 break;
359 case 8:
360 *arg = OWL_PINCONF_DRV_8MA;
361 break;
362 case 12:
363 *arg = OWL_PINCONF_DRV_12MA;
364 break;
365 default:
366 return -EINVAL;
367 }
368 break;
369 case PIN_CONFIG_SLEW_RATE:
370 if (*arg)
371 *arg = OWL_PINCONF_SLEW_FAST;
372 else
373 *arg = OWL_PINCONF_SLEW_SLOW;
374 break;
375 default:
376 return -ENOTSUPP;
377 }
378
379 return 0;
380}
381
382static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
383 unsigned int param,
384 u32 *arg)
385{
386 switch (param) {
387 case PIN_CONFIG_DRIVE_STRENGTH:
388 switch (*arg) {
389 case OWL_PINCONF_DRV_2MA:
390 *arg = 2;
391 break;
392 case OWL_PINCONF_DRV_4MA:
393 *arg = 4;
394 break;
395 case OWL_PINCONF_DRV_8MA:
396 *arg = 8;
397 break;
398 case OWL_PINCONF_DRV_12MA:
399 *arg = 12;
400 break;
401 default:
402 return -EINVAL;
403 }
404 break;
405 case PIN_CONFIG_SLEW_RATE:
406 if (*arg)
407 *arg = 1;
408 else
409 *arg = 0;
410 break;
411 default:
412 return -ENOTSUPP;
413 }
414
415 return 0;
416}
417
418static int owl_group_config_get(struct pinctrl_dev *pctrldev,
419 unsigned int group,
420 unsigned long *config)
421{
422 const struct owl_pingroup *g;
423 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
424 unsigned int param = pinconf_to_config_param(*config);
425 u32 reg, bit, width, arg;
426 int ret;
427
428 g = &pctrl->soc->groups[group];
429
430 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
431 if (ret)
432 return ret;
433
434 arg = owl_read_field(pctrl, reg, bit, width);
435
436 ret = owl_group_pinconf_val2arg(g, param, &arg);
437 if (ret)
438 return ret;
439
440 *config = pinconf_to_config_packed(param, arg);
441
442 return ret;
443
444}
445
446static int owl_group_config_set(struct pinctrl_dev *pctrldev,
447 unsigned int group,
448 unsigned long *configs,
449 unsigned int num_configs)
450{
451 const struct owl_pingroup *g;
452 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
453 unsigned long flags;
454 unsigned int param;
455 u32 reg, bit, width, arg;
456 int ret, i;
457
458 g = &pctrl->soc->groups[group];
459
460 for (i = 0; i < num_configs; i++) {
461 param = pinconf_to_config_param(configs[i]);
462 arg = pinconf_to_config_argument(configs[i]);
463
464 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
465 if (ret)
466 return ret;
467
468 ret = owl_group_pinconf_arg2val(g, param, &arg);
469 if (ret)
470 return ret;
471
472
473 raw_spin_lock_irqsave(&pctrl->lock, flags);
474
475 owl_write_field(pctrl, reg, arg, bit, width);
476
477 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
478 }
479
480 return 0;
481}
482
483static const struct pinconf_ops owl_pinconf_ops = {
484 .is_generic = true,
485 .pin_config_get = owl_pin_config_get,
486 .pin_config_set = owl_pin_config_set,
487 .pin_config_group_get = owl_group_config_get,
488 .pin_config_group_set = owl_group_config_set,
489};
490
491static struct pinctrl_desc owl_pinctrl_desc = {
492 .pctlops = &owl_pinctrl_ops,
493 .pmxops = &owl_pinmux_ops,
494 .confops = &owl_pinconf_ops,
495 .owner = THIS_MODULE,
496};
497
498static const struct owl_gpio_port *
499owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
500{
501 unsigned int start = 0, i;
502
503 for (i = 0; i < pctrl->soc->nports; i++) {
504 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
505
506 if (*pin >= start && *pin < start + port->pins) {
507 *pin -= start;
508 return port;
509 }
510
511 start += port->pins;
512 }
513
514 return NULL;
515}
516
517static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
518{
519 u32 val;
520
521 val = readl_relaxed(base);
522
523 if (flag)
524 val |= BIT(pin);
525 else
526 val &= ~BIT(pin);
527
528 writel_relaxed(val, base);
529}
530
531static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
532{
533 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
534 const struct owl_gpio_port *port;
535 void __iomem *gpio_base;
536 unsigned long flags;
537
538 port = owl_gpio_get_port(pctrl, &offset);
539 if (WARN_ON(port == NULL))
540 return -ENODEV;
541
542 gpio_base = pctrl->base + port->offset;
543
544
545
546
547
548 raw_spin_lock_irqsave(&pctrl->lock, flags);
549 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
550 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
551
552 return 0;
553}
554
555static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
556{
557 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
558 const struct owl_gpio_port *port;
559 void __iomem *gpio_base;
560 unsigned long flags;
561
562 port = owl_gpio_get_port(pctrl, &offset);
563 if (WARN_ON(port == NULL))
564 return;
565
566 gpio_base = pctrl->base + port->offset;
567
568 raw_spin_lock_irqsave(&pctrl->lock, flags);
569
570 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
571
572
573 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
574 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
575}
576
577static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
578{
579 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
580 const struct owl_gpio_port *port;
581 void __iomem *gpio_base;
582 unsigned long flags;
583 u32 val;
584
585 port = owl_gpio_get_port(pctrl, &offset);
586 if (WARN_ON(port == NULL))
587 return -ENODEV;
588
589 gpio_base = pctrl->base + port->offset;
590
591 raw_spin_lock_irqsave(&pctrl->lock, flags);
592 val = readl_relaxed(gpio_base + port->dat);
593 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
594
595 return !!(val & BIT(offset));
596}
597
598static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
599{
600 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
601 const struct owl_gpio_port *port;
602 void __iomem *gpio_base;
603 unsigned long flags;
604
605 port = owl_gpio_get_port(pctrl, &offset);
606 if (WARN_ON(port == NULL))
607 return;
608
609 gpio_base = pctrl->base + port->offset;
610
611 raw_spin_lock_irqsave(&pctrl->lock, flags);
612 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
613 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
614}
615
616static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
617{
618 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
619 const struct owl_gpio_port *port;
620 void __iomem *gpio_base;
621 unsigned long flags;
622
623 port = owl_gpio_get_port(pctrl, &offset);
624 if (WARN_ON(port == NULL))
625 return -ENODEV;
626
627 gpio_base = pctrl->base + port->offset;
628
629 raw_spin_lock_irqsave(&pctrl->lock, flags);
630 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
631 owl_gpio_update_reg(gpio_base + port->inen, offset, true);
632 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
633
634 return 0;
635}
636
637static int owl_gpio_direction_output(struct gpio_chip *chip,
638 unsigned int offset, int value)
639{
640 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
641 const struct owl_gpio_port *port;
642 void __iomem *gpio_base;
643 unsigned long flags;
644
645 port = owl_gpio_get_port(pctrl, &offset);
646 if (WARN_ON(port == NULL))
647 return -ENODEV;
648
649 gpio_base = pctrl->base + port->offset;
650
651 raw_spin_lock_irqsave(&pctrl->lock, flags);
652 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
653 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
654 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
655 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
656
657 return 0;
658}
659
660static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
661{
662 const struct owl_gpio_port *port;
663 void __iomem *gpio_base;
664 unsigned long flags;
665 unsigned int offset, value, irq_type = 0;
666
667 switch (type) {
668 case IRQ_TYPE_EDGE_BOTH:
669
670
671
672
673
674
675 if (owl_gpio_get(&pctrl->chip, gpio))
676 irq_type = OWL_GPIO_INT_EDGE_FALLING;
677 else
678 irq_type = OWL_GPIO_INT_EDGE_RISING;
679 break;
680
681 case IRQ_TYPE_EDGE_RISING:
682 irq_type = OWL_GPIO_INT_EDGE_RISING;
683 break;
684
685 case IRQ_TYPE_EDGE_FALLING:
686 irq_type = OWL_GPIO_INT_EDGE_FALLING;
687 break;
688
689 case IRQ_TYPE_LEVEL_HIGH:
690 irq_type = OWL_GPIO_INT_LEVEL_HIGH;
691 break;
692
693 case IRQ_TYPE_LEVEL_LOW:
694 irq_type = OWL_GPIO_INT_LEVEL_LOW;
695 break;
696
697 default:
698 break;
699 }
700
701 port = owl_gpio_get_port(pctrl, &gpio);
702 if (WARN_ON(port == NULL))
703 return;
704
705 gpio_base = pctrl->base + port->offset;
706
707 raw_spin_lock_irqsave(&pctrl->lock, flags);
708
709 offset = (gpio < 16) ? 4 : 0;
710 value = readl_relaxed(gpio_base + port->intc_type + offset);
711 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
712 value |= irq_type << ((gpio % 16) * 2);
713 writel_relaxed(value, gpio_base + port->intc_type + offset);
714
715 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
716}
717
718static void owl_gpio_irq_mask(struct irq_data *data)
719{
720 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
721 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
722 const struct owl_gpio_port *port;
723 void __iomem *gpio_base;
724 unsigned long flags;
725 unsigned int gpio = data->hwirq;
726 u32 val;
727
728 port = owl_gpio_get_port(pctrl, &gpio);
729 if (WARN_ON(port == NULL))
730 return;
731
732 gpio_base = pctrl->base + port->offset;
733
734 raw_spin_lock_irqsave(&pctrl->lock, flags);
735
736 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
737
738
739 val = readl_relaxed(gpio_base + port->intc_msk);
740 if (val == 0)
741 owl_gpio_update_reg(gpio_base + port->intc_ctl,
742 OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
743
744 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
745}
746
747static void owl_gpio_irq_unmask(struct irq_data *data)
748{
749 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
750 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
751 const struct owl_gpio_port *port;
752 void __iomem *gpio_base;
753 unsigned long flags;
754 unsigned int gpio = data->hwirq;
755 u32 value;
756
757 port = owl_gpio_get_port(pctrl, &gpio);
758 if (WARN_ON(port == NULL))
759 return;
760
761 gpio_base = pctrl->base + port->offset;
762 raw_spin_lock_irqsave(&pctrl->lock, flags);
763
764
765 value = readl_relaxed(gpio_base + port->intc_ctl);
766 value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
767 << port->shared_ctl_offset * 5);
768 writel_relaxed(value, gpio_base + port->intc_ctl);
769
770
771 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
772
773 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
774}
775
776static void owl_gpio_irq_ack(struct irq_data *data)
777{
778 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
779 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
780 const struct owl_gpio_port *port;
781 void __iomem *gpio_base;
782 unsigned long flags;
783 unsigned int gpio = data->hwirq;
784
785
786
787
788
789 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
790 if (owl_gpio_get(gc, gpio))
791 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
792 else
793 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
794 }
795
796 port = owl_gpio_get_port(pctrl, &gpio);
797 if (WARN_ON(port == NULL))
798 return;
799
800 gpio_base = pctrl->base + port->offset;
801
802 raw_spin_lock_irqsave(&pctrl->lock, flags);
803
804 owl_gpio_update_reg(gpio_base + port->intc_ctl,
805 OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
806
807 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
808}
809
810static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
811{
812 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
813 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
814
815 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
816 irq_set_handler_locked(data, handle_level_irq);
817 else
818 irq_set_handler_locked(data, handle_edge_irq);
819
820 irq_set_type(pctrl, data->hwirq, type);
821
822 return 0;
823}
824
825static void owl_gpio_irq_handler(struct irq_desc *desc)
826{
827 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
828 struct irq_chip *chip = irq_desc_get_chip(desc);
829 struct irq_domain *domain = pctrl->chip.irq.domain;
830 unsigned int parent = irq_desc_get_irq(desc);
831 const struct owl_gpio_port *port;
832 void __iomem *base;
833 unsigned int pin, irq, offset = 0, i;
834 unsigned long pending_irq;
835
836 chained_irq_enter(chip, desc);
837
838 for (i = 0; i < pctrl->soc->nports; i++) {
839 port = &pctrl->soc->ports[i];
840 base = pctrl->base + port->offset;
841
842
843 if (parent != pctrl->irq[i])
844 goto skip;
845
846 pending_irq = readl_relaxed(base + port->intc_pd);
847
848 for_each_set_bit(pin, &pending_irq, port->pins) {
849 irq = irq_find_mapping(domain, offset + pin);
850 generic_handle_irq(irq);
851
852
853 owl_gpio_update_reg(base + port->intc_pd, pin, true);
854 }
855
856skip:
857 offset += port->pins;
858 }
859
860 chained_irq_exit(chip, desc);
861}
862
863static int owl_gpio_init(struct owl_pinctrl *pctrl)
864{
865 struct gpio_chip *chip;
866 struct gpio_irq_chip *gpio_irq;
867 int ret, i, j, offset;
868
869 chip = &pctrl->chip;
870 chip->base = -1;
871 chip->ngpio = pctrl->soc->ngpios;
872 chip->label = dev_name(pctrl->dev);
873 chip->parent = pctrl->dev;
874 chip->owner = THIS_MODULE;
875 chip->of_node = pctrl->dev->of_node;
876
877 pctrl->irq_chip.name = chip->of_node->name;
878 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
879 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
880 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
881 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
882
883 gpio_irq = &chip->irq;
884 gpio_irq->chip = &pctrl->irq_chip;
885 gpio_irq->handler = handle_simple_irq;
886 gpio_irq->default_type = IRQ_TYPE_NONE;
887 gpio_irq->parent_handler = owl_gpio_irq_handler;
888 gpio_irq->parent_handler_data = pctrl;
889 gpio_irq->num_parents = pctrl->num_irq;
890 gpio_irq->parents = pctrl->irq;
891
892 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
893 sizeof(*gpio_irq->map), GFP_KERNEL);
894 if (!gpio_irq->map)
895 return -ENOMEM;
896
897 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
898 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
899
900 for (j = 0; j < port->pins; j++)
901 gpio_irq->map[offset + j] = gpio_irq->parents[i];
902
903 offset += port->pins;
904 }
905
906 ret = gpiochip_add_data(&pctrl->chip, pctrl);
907 if (ret) {
908 dev_err(pctrl->dev, "failed to register gpiochip\n");
909 return ret;
910 }
911
912 return 0;
913}
914
915int owl_pinctrl_probe(struct platform_device *pdev,
916 struct owl_pinctrl_soc_data *soc_data)
917{
918 struct owl_pinctrl *pctrl;
919 int ret, i;
920
921 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
922 if (!pctrl)
923 return -ENOMEM;
924
925 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
926 if (IS_ERR(pctrl->base))
927 return PTR_ERR(pctrl->base);
928
929
930 pctrl->clk = devm_clk_get(&pdev->dev, NULL);
931 if (IS_ERR(pctrl->clk)) {
932 dev_err(&pdev->dev, "no clock defined\n");
933 return PTR_ERR(pctrl->clk);
934 }
935
936 ret = clk_prepare_enable(pctrl->clk);
937 if (ret) {
938 dev_err(&pdev->dev, "clk enable failed\n");
939 return ret;
940 }
941
942 raw_spin_lock_init(&pctrl->lock);
943
944 owl_pinctrl_desc.name = dev_name(&pdev->dev);
945 owl_pinctrl_desc.pins = soc_data->pins;
946 owl_pinctrl_desc.npins = soc_data->npins;
947
948 pctrl->chip.direction_input = owl_gpio_direction_input;
949 pctrl->chip.direction_output = owl_gpio_direction_output;
950 pctrl->chip.get = owl_gpio_get;
951 pctrl->chip.set = owl_gpio_set;
952 pctrl->chip.request = owl_gpio_request;
953 pctrl->chip.free = owl_gpio_free;
954
955 pctrl->soc = soc_data;
956 pctrl->dev = &pdev->dev;
957
958 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
959 &owl_pinctrl_desc, pctrl);
960 if (IS_ERR(pctrl->pctrldev)) {
961 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
962 ret = PTR_ERR(pctrl->pctrldev);
963 goto err_exit;
964 }
965
966 ret = platform_irq_count(pdev);
967 if (ret < 0)
968 goto err_exit;
969
970 pctrl->num_irq = ret;
971
972 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
973 sizeof(*pctrl->irq), GFP_KERNEL);
974 if (!pctrl->irq) {
975 ret = -ENOMEM;
976 goto err_exit;
977 }
978
979 for (i = 0; i < pctrl->num_irq ; i++) {
980 ret = platform_get_irq(pdev, i);
981 if (ret < 0)
982 goto err_exit;
983 pctrl->irq[i] = ret;
984 }
985
986 ret = owl_gpio_init(pctrl);
987 if (ret)
988 goto err_exit;
989
990 platform_set_drvdata(pdev, pctrl);
991
992 return 0;
993
994err_exit:
995 clk_disable_unprepare(pctrl->clk);
996
997 return ret;
998}
999
