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10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/device.h>
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/gpio/driver.h>
18#include <linux/spinlock.h>
19#include <linux/interrupt.h>
20#include <linux/slab.h>
21#include <linux/of_device.h>
22#include <linux/of_address.h>
23#include <linux/bitops.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinmux.h>
27#include <linux/pinctrl/pinconf.h>
28
29#include <linux/pinctrl/consumer.h>
30#include "pinctrl-nomadik.h"
31#include "../core.h"
32#include "../pinctrl-utils.h"
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72typedef unsigned long pin_cfg_t;
73
74#define PIN_NUM_MASK 0x1ff
75#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
76
77#define PIN_ALT_SHIFT 9
78#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
79#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
80#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
81#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
82#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
83#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
84
85#define PIN_PULL_SHIFT 11
86#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
87#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
88#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
89#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
90#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
91
92#define PIN_SLPM_SHIFT 13
93#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
94#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
95#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
96#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
97
98#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
99#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
100#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
101
102#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE
103#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE
104
105#define PIN_DIR_SHIFT 14
106#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
107#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
108#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
109#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
110
111#define PIN_VAL_SHIFT 15
112#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
113#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
114#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
115#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
116
117#define PIN_SLPM_PULL_SHIFT 16
118#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
119#define PIN_SLPM_PULL(x) \
120 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
121#define PIN_SLPM_PULL_NONE \
122 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
123#define PIN_SLPM_PULL_UP \
124 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
125#define PIN_SLPM_PULL_DOWN \
126 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
127
128#define PIN_SLPM_DIR_SHIFT 19
129#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
130#define PIN_SLPM_DIR(x) \
131 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
132#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
133#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
134
135#define PIN_SLPM_VAL_SHIFT 21
136#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
137#define PIN_SLPM_VAL(x) \
138 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
139#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
140#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
141
142#define PIN_SLPM_PDIS_SHIFT 23
143#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
144#define PIN_SLPM_PDIS(x) \
145 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
146#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
147#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
148#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
149
150#define PIN_LOWEMI_SHIFT 25
151#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
152#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
153#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
154#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
155
156#define PIN_GPIOMODE_SHIFT 26
157#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
158#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
159#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
160#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
161
162#define PIN_SLEEPMODE_SHIFT 27
163#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
164#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
165#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
166#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
167
168
169
170#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
171#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
172#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
173#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
174#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
175
176#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
177#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
178#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
179#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
180#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
181
182#define PIN_CFG_DEFAULT (0)
183
184#define PIN_CFG(num, alt) \
185 (PIN_CFG_DEFAULT |\
186 (PIN_NUM(num) | PIN_##alt))
187
188#define PIN_CFG_INPUT(num, alt, pull) \
189 (PIN_CFG_DEFAULT |\
190 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
191
192#define PIN_CFG_OUTPUT(num, alt, val) \
193 (PIN_CFG_DEFAULT |\
194 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
195
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200
201#define GPIO_BLOCK_SHIFT 5
202#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
203#define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
204
205
206#define NMK_GPIO_DAT 0x00
207#define NMK_GPIO_DATS 0x04
208#define NMK_GPIO_DATC 0x08
209#define NMK_GPIO_PDIS 0x0c
210#define NMK_GPIO_DIR 0x10
211#define NMK_GPIO_DIRS 0x14
212#define NMK_GPIO_DIRC 0x18
213#define NMK_GPIO_SLPC 0x1c
214#define NMK_GPIO_AFSLA 0x20
215#define NMK_GPIO_AFSLB 0x24
216#define NMK_GPIO_LOWEMI 0x28
217
218#define NMK_GPIO_RIMSC 0x40
219#define NMK_GPIO_FIMSC 0x44
220#define NMK_GPIO_IS 0x48
221#define NMK_GPIO_IC 0x4c
222#define NMK_GPIO_RWIMSC 0x50
223#define NMK_GPIO_FWIMSC 0x54
224#define NMK_GPIO_WKS 0x58
225
226#define NMK_GPIO_EDGELEVEL 0x5C
227#define NMK_GPIO_LEVEL 0x60
228
229
230
231enum nmk_gpio_pull {
232 NMK_GPIO_PULL_NONE,
233 NMK_GPIO_PULL_UP,
234 NMK_GPIO_PULL_DOWN,
235};
236
237
238enum nmk_gpio_slpm {
239 NMK_GPIO_SLPM_INPUT,
240 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
241 NMK_GPIO_SLPM_NOCHANGE,
242 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
243};
244
245struct nmk_gpio_chip {
246 struct gpio_chip chip;
247 struct irq_chip irqchip;
248 void __iomem *addr;
249 struct clk *clk;
250 unsigned int bank;
251 void (*set_ioforce)(bool enable);
252 spinlock_t lock;
253 bool sleepmode;
254
255 u32 edge_rising;
256 u32 edge_falling;
257 u32 real_wake;
258 u32 rwimsc;
259 u32 fwimsc;
260 u32 rimsc;
261 u32 fimsc;
262 u32 pull_up;
263 u32 lowemi;
264};
265
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271
272
273struct nmk_pinctrl {
274 struct device *dev;
275 struct pinctrl_dev *pctl;
276 const struct nmk_pinctrl_soc_data *soc;
277 void __iomem *prcm_base;
278};
279
280static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
281
282static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
283
284#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
285
286static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
287 unsigned offset, int gpio_mode)
288{
289 u32 afunc, bfunc;
290
291 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
292 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
293 if (gpio_mode & NMK_GPIO_ALT_A)
294 afunc |= BIT(offset);
295 if (gpio_mode & NMK_GPIO_ALT_B)
296 bfunc |= BIT(offset);
297 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
298 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
299}
300
301static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
302 unsigned offset, enum nmk_gpio_slpm mode)
303{
304 u32 slpm;
305
306 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
307 if (mode == NMK_GPIO_SLPM_NOCHANGE)
308 slpm |= BIT(offset);
309 else
310 slpm &= ~BIT(offset);
311 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
312}
313
314static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
315 unsigned offset, enum nmk_gpio_pull pull)
316{
317 u32 pdis;
318
319 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
320 if (pull == NMK_GPIO_PULL_NONE) {
321 pdis |= BIT(offset);
322 nmk_chip->pull_up &= ~BIT(offset);
323 } else {
324 pdis &= ~BIT(offset);
325 }
326
327 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
328
329 if (pull == NMK_GPIO_PULL_UP) {
330 nmk_chip->pull_up |= BIT(offset);
331 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
332 } else if (pull == NMK_GPIO_PULL_DOWN) {
333 nmk_chip->pull_up &= ~BIT(offset);
334 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
335 }
336}
337
338static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
339 unsigned offset, bool lowemi)
340{
341 bool enabled = nmk_chip->lowemi & BIT(offset);
342
343 if (lowemi == enabled)
344 return;
345
346 if (lowemi)
347 nmk_chip->lowemi |= BIT(offset);
348 else
349 nmk_chip->lowemi &= ~BIT(offset);
350
351 writel_relaxed(nmk_chip->lowemi,
352 nmk_chip->addr + NMK_GPIO_LOWEMI);
353}
354
355static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
356 unsigned offset)
357{
358 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
359}
360
361static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
362 unsigned offset, int val)
363{
364 if (val)
365 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
366 else
367 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
368}
369
370static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
371 unsigned offset, int val)
372{
373 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
374 __nmk_gpio_set_output(nmk_chip, offset, val);
375}
376
377static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
378 unsigned offset, int gpio_mode,
379 bool glitch)
380{
381 u32 rwimsc = nmk_chip->rwimsc;
382 u32 fwimsc = nmk_chip->fwimsc;
383
384 if (glitch && nmk_chip->set_ioforce) {
385 u32 bit = BIT(offset);
386
387
388 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
389 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
390
391 nmk_chip->set_ioforce(true);
392 }
393
394 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
395
396 if (glitch && nmk_chip->set_ioforce) {
397 nmk_chip->set_ioforce(false);
398
399 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
400 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
401 }
402}
403
404static void
405nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
406{
407 u32 falling = nmk_chip->fimsc & BIT(offset);
408 u32 rising = nmk_chip->rimsc & BIT(offset);
409 int gpio = nmk_chip->chip.base + offset;
410 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
411 struct irq_data *d = irq_get_irq_data(irq);
412
413 if (!rising && !falling)
414 return;
415
416 if (!d || !irqd_irq_disabled(d))
417 return;
418
419 if (rising) {
420 nmk_chip->rimsc &= ~BIT(offset);
421 writel_relaxed(nmk_chip->rimsc,
422 nmk_chip->addr + NMK_GPIO_RIMSC);
423 }
424
425 if (falling) {
426 nmk_chip->fimsc &= ~BIT(offset);
427 writel_relaxed(nmk_chip->fimsc,
428 nmk_chip->addr + NMK_GPIO_FIMSC);
429 }
430
431 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
432}
433
434static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
435{
436 u32 val;
437
438 val = readl(reg);
439 val = ((val & ~mask) | (value & mask));
440 writel(val, reg);
441}
442
443static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
444 unsigned offset, unsigned alt_num)
445{
446 int i;
447 u16 reg;
448 u8 bit;
449 u8 alt_index;
450 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
451 const u16 *gpiocr_regs;
452
453 if (!npct->prcm_base)
454 return;
455
456 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
457 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
458 alt_num);
459 return;
460 }
461
462 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
463 if (npct->soc->altcx_pins[i].pin == offset)
464 break;
465 }
466 if (i == npct->soc->npins_altcx) {
467 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
468 offset);
469 return;
470 }
471
472 pin_desc = npct->soc->altcx_pins + i;
473 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
474
475
476
477
478
479 if (!alt_num) {
480 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
481 if (pin_desc->altcx[i].used == true) {
482 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
483 bit = pin_desc->altcx[i].control_bit;
484 if (readl(npct->prcm_base + reg) & BIT(bit)) {
485 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
486 dev_dbg(npct->dev,
487 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
488 offset, i+1);
489 }
490 }
491 }
492 return;
493 }
494
495 alt_index = alt_num - 1;
496 if (pin_desc->altcx[alt_index].used == false) {
497 dev_warn(npct->dev,
498 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
499 offset, alt_num);
500 return;
501 }
502
503
504
505
506
507 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
508 if (i == alt_index)
509 continue;
510 if (pin_desc->altcx[i].used == true) {
511 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
512 bit = pin_desc->altcx[i].control_bit;
513 if (readl(npct->prcm_base + reg) & BIT(bit)) {
514 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
515 dev_dbg(npct->dev,
516 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
517 offset, i+1);
518 }
519 }
520 }
521
522 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
523 bit = pin_desc->altcx[alt_index].control_bit;
524 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
525 offset, alt_index+1);
526 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
527}
528
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540
541static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
542{
543 int i;
544
545 for (i = 0; i < NUM_BANKS; i++) {
546 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
547 unsigned int temp = slpm[i];
548
549 if (!chip)
550 break;
551
552 clk_enable(chip->clk);
553
554 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
555 writel(temp, chip->addr + NMK_GPIO_SLPC);
556 }
557}
558
559static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
560{
561 int i;
562
563 for (i = 0; i < NUM_BANKS; i++) {
564 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
565
566 if (!chip)
567 break;
568
569 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
570
571 clk_disable(chip->clk);
572 }
573}
574
575static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
576{
577 int i;
578 u16 reg;
579 u8 bit;
580 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
581 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
582 const u16 *gpiocr_regs;
583
584 if (!npct->prcm_base)
585 return NMK_GPIO_ALT_C;
586
587 for (i = 0; i < npct->soc->npins_altcx; i++) {
588 if (npct->soc->altcx_pins[i].pin == gpio)
589 break;
590 }
591 if (i == npct->soc->npins_altcx)
592 return NMK_GPIO_ALT_C;
593
594 pin_desc = npct->soc->altcx_pins + i;
595 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
596 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
597 if (pin_desc->altcx[i].used == true) {
598 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
599 bit = pin_desc->altcx[i].control_bit;
600 if (readl(npct->prcm_base + reg) & BIT(bit))
601 return NMK_GPIO_ALT_C+i+1;
602 }
603 }
604 return NMK_GPIO_ALT_C;
605}
606
607
608
609static void nmk_gpio_irq_ack(struct irq_data *d)
610{
611 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
612 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
613
614 clk_enable(nmk_chip->clk);
615 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
616 clk_disable(nmk_chip->clk);
617}
618
619enum nmk_gpio_irq_type {
620 NORMAL,
621 WAKE,
622};
623
624static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
625 int offset, enum nmk_gpio_irq_type which,
626 bool enable)
627{
628 u32 *rimscval;
629 u32 *fimscval;
630 u32 rimscreg;
631 u32 fimscreg;
632
633 if (which == NORMAL) {
634 rimscreg = NMK_GPIO_RIMSC;
635 fimscreg = NMK_GPIO_FIMSC;
636 rimscval = &nmk_chip->rimsc;
637 fimscval = &nmk_chip->fimsc;
638 } else {
639 rimscreg = NMK_GPIO_RWIMSC;
640 fimscreg = NMK_GPIO_FWIMSC;
641 rimscval = &nmk_chip->rwimsc;
642 fimscval = &nmk_chip->fwimsc;
643 }
644
645
646 if (nmk_chip->edge_rising & BIT(offset)) {
647 if (enable)
648 *rimscval |= BIT(offset);
649 else
650 *rimscval &= ~BIT(offset);
651 writel(*rimscval, nmk_chip->addr + rimscreg);
652 }
653 if (nmk_chip->edge_falling & BIT(offset)) {
654 if (enable)
655 *fimscval |= BIT(offset);
656 else
657 *fimscval &= ~BIT(offset);
658 writel(*fimscval, nmk_chip->addr + fimscreg);
659 }
660}
661
662static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
663 int offset, bool on)
664{
665
666
667
668
669
670 if (nmk_chip->sleepmode && on) {
671 __nmk_gpio_set_slpm(nmk_chip, offset,
672 NMK_GPIO_SLPM_WAKEUP_ENABLE);
673 }
674
675 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
676}
677
678static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
679{
680 struct nmk_gpio_chip *nmk_chip;
681 unsigned long flags;
682
683 nmk_chip = irq_data_get_irq_chip_data(d);
684 if (!nmk_chip)
685 return -EINVAL;
686
687 clk_enable(nmk_chip->clk);
688 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
689 spin_lock(&nmk_chip->lock);
690
691 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
692
693 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
694 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
695
696 spin_unlock(&nmk_chip->lock);
697 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
698 clk_disable(nmk_chip->clk);
699
700 return 0;
701}
702
703static void nmk_gpio_irq_mask(struct irq_data *d)
704{
705 nmk_gpio_irq_maskunmask(d, false);
706}
707
708static void nmk_gpio_irq_unmask(struct irq_data *d)
709{
710 nmk_gpio_irq_maskunmask(d, true);
711}
712
713static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
714{
715 struct nmk_gpio_chip *nmk_chip;
716 unsigned long flags;
717
718 nmk_chip = irq_data_get_irq_chip_data(d);
719 if (!nmk_chip)
720 return -EINVAL;
721
722 clk_enable(nmk_chip->clk);
723 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
724 spin_lock(&nmk_chip->lock);
725
726 if (irqd_irq_disabled(d))
727 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
728
729 if (on)
730 nmk_chip->real_wake |= BIT(d->hwirq);
731 else
732 nmk_chip->real_wake &= ~BIT(d->hwirq);
733
734 spin_unlock(&nmk_chip->lock);
735 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
736 clk_disable(nmk_chip->clk);
737
738 return 0;
739}
740
741static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
742{
743 bool enabled = !irqd_irq_disabled(d);
744 bool wake = irqd_is_wakeup_set(d);
745 struct nmk_gpio_chip *nmk_chip;
746 unsigned long flags;
747
748 nmk_chip = irq_data_get_irq_chip_data(d);
749 if (!nmk_chip)
750 return -EINVAL;
751 if (type & IRQ_TYPE_LEVEL_HIGH)
752 return -EINVAL;
753 if (type & IRQ_TYPE_LEVEL_LOW)
754 return -EINVAL;
755
756 clk_enable(nmk_chip->clk);
757 spin_lock_irqsave(&nmk_chip->lock, flags);
758
759 if (enabled)
760 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
761
762 if (enabled || wake)
763 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
764
765 nmk_chip->edge_rising &= ~BIT(d->hwirq);
766 if (type & IRQ_TYPE_EDGE_RISING)
767 nmk_chip->edge_rising |= BIT(d->hwirq);
768
769 nmk_chip->edge_falling &= ~BIT(d->hwirq);
770 if (type & IRQ_TYPE_EDGE_FALLING)
771 nmk_chip->edge_falling |= BIT(d->hwirq);
772
773 if (enabled)
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
775
776 if (enabled || wake)
777 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
778
779 spin_unlock_irqrestore(&nmk_chip->lock, flags);
780 clk_disable(nmk_chip->clk);
781
782 return 0;
783}
784
785static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
786{
787 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
788
789 clk_enable(nmk_chip->clk);
790 nmk_gpio_irq_unmask(d);
791 return 0;
792}
793
794static void nmk_gpio_irq_shutdown(struct irq_data *d)
795{
796 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
797
798 nmk_gpio_irq_mask(d);
799 clk_disable(nmk_chip->clk);
800}
801
802static void nmk_gpio_irq_handler(struct irq_desc *desc)
803{
804 struct irq_chip *host_chip = irq_desc_get_chip(desc);
805 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
806 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
807 u32 status;
808
809 chained_irq_enter(host_chip, desc);
810
811 clk_enable(nmk_chip->clk);
812 status = readl(nmk_chip->addr + NMK_GPIO_IS);
813 clk_disable(nmk_chip->clk);
814
815 while (status) {
816 int bit = __ffs(status);
817
818 generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
819 status &= ~BIT(bit);
820 }
821
822 chained_irq_exit(host_chip, desc);
823}
824
825
826
827static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
828{
829 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
830 int dir;
831
832 clk_enable(nmk_chip->clk);
833
834 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
835
836 clk_disable(nmk_chip->clk);
837
838 if (dir)
839 return GPIO_LINE_DIRECTION_OUT;
840
841 return GPIO_LINE_DIRECTION_IN;
842}
843
844static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
845{
846 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
847
848 clk_enable(nmk_chip->clk);
849
850 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
851
852 clk_disable(nmk_chip->clk);
853
854 return 0;
855}
856
857static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
858{
859 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
860 int value;
861
862 clk_enable(nmk_chip->clk);
863
864 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
865
866 clk_disable(nmk_chip->clk);
867
868 return value;
869}
870
871static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
872 int val)
873{
874 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
875
876 clk_enable(nmk_chip->clk);
877
878 __nmk_gpio_set_output(nmk_chip, offset, val);
879
880 clk_disable(nmk_chip->clk);
881}
882
883static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
884 int val)
885{
886 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
887
888 clk_enable(nmk_chip->clk);
889
890 __nmk_gpio_make_output(nmk_chip, offset, val);
891
892 clk_disable(nmk_chip->clk);
893
894 return 0;
895}
896
897#ifdef CONFIG_DEBUG_FS
898static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
899{
900 u32 afunc, bfunc;
901
902 clk_enable(nmk_chip->clk);
903
904 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
905 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
906
907 clk_disable(nmk_chip->clk);
908
909 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
910}
911
912#include <linux/seq_file.h>
913
914static void nmk_gpio_dbg_show_one(struct seq_file *s,
915 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
916 unsigned offset, unsigned gpio)
917{
918 const char *label = gpiochip_is_requested(chip, offset);
919 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
920 int mode;
921 bool is_out;
922 bool data_out;
923 bool pull;
924 const char *modes[] = {
925 [NMK_GPIO_ALT_GPIO] = "gpio",
926 [NMK_GPIO_ALT_A] = "altA",
927 [NMK_GPIO_ALT_B] = "altB",
928 [NMK_GPIO_ALT_C] = "altC",
929 [NMK_GPIO_ALT_C+1] = "altC1",
930 [NMK_GPIO_ALT_C+2] = "altC2",
931 [NMK_GPIO_ALT_C+3] = "altC3",
932 [NMK_GPIO_ALT_C+4] = "altC4",
933 };
934 const char *pulls[] = {
935 "none ",
936 "pull down",
937 "pull up ",
938 };
939
940 clk_enable(nmk_chip->clk);
941 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
942 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
943 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
944 mode = nmk_gpio_get_mode(nmk_chip, offset);
945 if ((mode == NMK_GPIO_ALT_C) && pctldev)
946 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
947
948 if (is_out) {
949 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
950 gpio,
951 label ?: "(none)",
952 data_out ? "hi" : "lo",
953 (mode < 0) ? "unknown" : modes[mode]);
954 } else {
955 int irq = chip->to_irq(chip, offset);
956 struct irq_desc *desc = irq_to_desc(irq);
957 int pullidx = 0;
958 int val;
959
960 if (pull)
961 pullidx = data_out ? 2 : 1;
962
963 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
964 gpio,
965 label ?: "(none)",
966 pulls[pullidx],
967 (mode < 0) ? "unknown" : modes[mode]);
968
969 val = nmk_gpio_get_input(chip, offset);
970 seq_printf(s, " VAL %d", val);
971
972
973
974
975
976 if (irq > 0 && desc && desc->action) {
977 char *trigger;
978
979 if (nmk_chip->edge_rising & BIT(offset))
980 trigger = "edge-rising";
981 else if (nmk_chip->edge_falling & BIT(offset))
982 trigger = "edge-falling";
983 else
984 trigger = "edge-undefined";
985
986 seq_printf(s, " irq-%d %s%s",
987 irq, trigger,
988 irqd_is_wakeup_set(&desc->irq_data)
989 ? " wakeup" : "");
990 }
991 }
992 clk_disable(nmk_chip->clk);
993}
994
995static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
996{
997 unsigned i;
998 unsigned gpio = chip->base;
999
1000 for (i = 0; i < chip->ngpio; i++, gpio++) {
1001 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1002 seq_printf(s, "\n");
1003 }
1004}
1005
1006#else
1007static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1008 struct pinctrl_dev *pctldev,
1009 struct gpio_chip *chip,
1010 unsigned offset, unsigned gpio)
1011{
1012}
1013#define nmk_gpio_dbg_show NULL
1014#endif
1015
1016
1017
1018
1019
1020
1021
1022static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1023 struct platform_device *pdev)
1024{
1025 struct nmk_gpio_chip *nmk_chip;
1026 struct platform_device *gpio_pdev;
1027 struct gpio_chip *chip;
1028 struct resource *res;
1029 struct clk *clk;
1030 void __iomem *base;
1031 u32 id;
1032
1033 gpio_pdev = of_find_device_by_node(np);
1034 if (!gpio_pdev) {
1035 pr_err("populate \"%pOFn\": device not found\n", np);
1036 return ERR_PTR(-ENODEV);
1037 }
1038 if (of_property_read_u32(np, "gpio-bank", &id)) {
1039 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1040 platform_device_put(gpio_pdev);
1041 return ERR_PTR(-EINVAL);
1042 }
1043
1044
1045 nmk_chip = nmk_gpio_chips[id];
1046 if (nmk_chip) {
1047 platform_device_put(gpio_pdev);
1048 return nmk_chip;
1049 }
1050
1051 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1052 if (!nmk_chip) {
1053 platform_device_put(gpio_pdev);
1054 return ERR_PTR(-ENOMEM);
1055 }
1056
1057 nmk_chip->bank = id;
1058 chip = &nmk_chip->chip;
1059 chip->base = id * NMK_GPIO_PER_CHIP;
1060 chip->ngpio = NMK_GPIO_PER_CHIP;
1061 chip->label = dev_name(&gpio_pdev->dev);
1062 chip->parent = &gpio_pdev->dev;
1063
1064 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1065 base = devm_ioremap_resource(&pdev->dev, res);
1066 if (IS_ERR(base)) {
1067 platform_device_put(gpio_pdev);
1068 return ERR_CAST(base);
1069 }
1070 nmk_chip->addr = base;
1071
1072 clk = clk_get(&gpio_pdev->dev, NULL);
1073 if (IS_ERR(clk)) {
1074 platform_device_put(gpio_pdev);
1075 return (void *) clk;
1076 }
1077 clk_prepare(clk);
1078 nmk_chip->clk = clk;
1079
1080 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1081 nmk_gpio_chips[id] = nmk_chip;
1082 return nmk_chip;
1083}
1084
1085static int nmk_gpio_probe(struct platform_device *dev)
1086{
1087 struct device_node *np = dev->dev.of_node;
1088 struct nmk_gpio_chip *nmk_chip;
1089 struct gpio_chip *chip;
1090 struct gpio_irq_chip *girq;
1091 struct irq_chip *irqchip;
1092 bool supports_sleepmode;
1093 int irq;
1094 int ret;
1095
1096 nmk_chip = nmk_gpio_populate_chip(np, dev);
1097 if (IS_ERR(nmk_chip)) {
1098 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1099 return PTR_ERR(nmk_chip);
1100 }
1101
1102 supports_sleepmode =
1103 of_property_read_bool(np, "st,supports-sleepmode");
1104
1105
1106 dev->id = nmk_chip->bank;
1107
1108 irq = platform_get_irq(dev, 0);
1109 if (irq < 0)
1110 return irq;
1111
1112
1113
1114
1115
1116 nmk_chip->sleepmode = supports_sleepmode;
1117 spin_lock_init(&nmk_chip->lock);
1118
1119 chip = &nmk_chip->chip;
1120 chip->request = gpiochip_generic_request;
1121 chip->free = gpiochip_generic_free;
1122 chip->get_direction = nmk_gpio_get_dir;
1123 chip->direction_input = nmk_gpio_make_input;
1124 chip->get = nmk_gpio_get_input;
1125 chip->direction_output = nmk_gpio_make_output;
1126 chip->set = nmk_gpio_set_output;
1127 chip->dbg_show = nmk_gpio_dbg_show;
1128 chip->can_sleep = false;
1129 chip->owner = THIS_MODULE;
1130
1131 irqchip = &nmk_chip->irqchip;
1132 irqchip->irq_ack = nmk_gpio_irq_ack;
1133 irqchip->irq_mask = nmk_gpio_irq_mask;
1134 irqchip->irq_unmask = nmk_gpio_irq_unmask;
1135 irqchip->irq_set_type = nmk_gpio_irq_set_type;
1136 irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1137 irqchip->irq_startup = nmk_gpio_irq_startup;
1138 irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1139 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1140 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1141 dev->id,
1142 chip->base,
1143 chip->base + chip->ngpio - 1);
1144
1145 girq = &chip->irq;
1146 girq->chip = irqchip;
1147 girq->parent_handler = nmk_gpio_irq_handler;
1148 girq->num_parents = 1;
1149 girq->parents = devm_kcalloc(&dev->dev, 1,
1150 sizeof(*girq->parents),
1151 GFP_KERNEL);
1152 if (!girq->parents)
1153 return -ENOMEM;
1154 girq->parents[0] = irq;
1155 girq->default_type = IRQ_TYPE_NONE;
1156 girq->handler = handle_edge_irq;
1157
1158 clk_enable(nmk_chip->clk);
1159 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1160 clk_disable(nmk_chip->clk);
1161 chip->of_node = np;
1162
1163 ret = gpiochip_add_data(chip, nmk_chip);
1164 if (ret)
1165 return ret;
1166
1167 platform_set_drvdata(dev, nmk_chip);
1168
1169 dev_info(&dev->dev, "chip registered\n");
1170
1171 return 0;
1172}
1173
1174static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1175{
1176 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1177
1178 return npct->soc->ngroups;
1179}
1180
1181static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1182 unsigned selector)
1183{
1184 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1185
1186 return npct->soc->groups[selector].name;
1187}
1188
1189static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1190 const unsigned **pins,
1191 unsigned *num_pins)
1192{
1193 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1194
1195 *pins = npct->soc->groups[selector].pins;
1196 *num_pins = npct->soc->groups[selector].npins;
1197 return 0;
1198}
1199
1200static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1201{
1202 int i;
1203 struct nmk_gpio_chip *nmk_gpio;
1204
1205 for(i = 0; i < NMK_MAX_BANKS; i++) {
1206 nmk_gpio = nmk_gpio_chips[i];
1207 if (!nmk_gpio)
1208 continue;
1209 if (pin >= nmk_gpio->chip.base &&
1210 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1211 return nmk_gpio;
1212 }
1213 return NULL;
1214}
1215
1216static struct gpio_chip *find_gc_from_pin(unsigned pin)
1217{
1218 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1219
1220 if (nmk_gpio)
1221 return &nmk_gpio->chip;
1222 return NULL;
1223}
1224
1225static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1226 unsigned offset)
1227{
1228 struct gpio_chip *chip = find_gc_from_pin(offset);
1229
1230 if (!chip) {
1231 seq_printf(s, "invalid pin offset");
1232 return;
1233 }
1234 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1235}
1236
1237static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1238 unsigned *num_maps, const char *group,
1239 const char *function)
1240{
1241 if (*num_maps == *reserved_maps)
1242 return -ENOSPC;
1243
1244 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1245 (*map)[*num_maps].data.mux.group = group;
1246 (*map)[*num_maps].data.mux.function = function;
1247 (*num_maps)++;
1248
1249 return 0;
1250}
1251
1252static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1253 unsigned *reserved_maps,
1254 unsigned *num_maps, const char *group,
1255 unsigned long *configs, unsigned num_configs)
1256{
1257 unsigned long *dup_configs;
1258
1259 if (*num_maps == *reserved_maps)
1260 return -ENOSPC;
1261
1262 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1263 GFP_KERNEL);
1264 if (!dup_configs)
1265 return -ENOMEM;
1266
1267 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1268
1269 (*map)[*num_maps].data.configs.group_or_pin = group;
1270 (*map)[*num_maps].data.configs.configs = dup_configs;
1271 (*map)[*num_maps].data.configs.num_configs = num_configs;
1272 (*num_maps)++;
1273
1274 return 0;
1275}
1276
1277#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1278#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1279 .size = ARRAY_SIZE(y), }
1280
1281static const unsigned long nmk_pin_input_modes[] = {
1282 PIN_INPUT_NOPULL,
1283 PIN_INPUT_PULLUP,
1284 PIN_INPUT_PULLDOWN,
1285};
1286
1287static const unsigned long nmk_pin_output_modes[] = {
1288 PIN_OUTPUT_LOW,
1289 PIN_OUTPUT_HIGH,
1290 PIN_DIR_OUTPUT,
1291};
1292
1293static const unsigned long nmk_pin_sleep_modes[] = {
1294 PIN_SLEEPMODE_DISABLED,
1295 PIN_SLEEPMODE_ENABLED,
1296};
1297
1298static const unsigned long nmk_pin_sleep_input_modes[] = {
1299 PIN_SLPM_INPUT_NOPULL,
1300 PIN_SLPM_INPUT_PULLUP,
1301 PIN_SLPM_INPUT_PULLDOWN,
1302 PIN_SLPM_DIR_INPUT,
1303};
1304
1305static const unsigned long nmk_pin_sleep_output_modes[] = {
1306 PIN_SLPM_OUTPUT_LOW,
1307 PIN_SLPM_OUTPUT_HIGH,
1308 PIN_SLPM_DIR_OUTPUT,
1309};
1310
1311static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1312 PIN_SLPM_WAKEUP_DISABLE,
1313 PIN_SLPM_WAKEUP_ENABLE,
1314};
1315
1316static const unsigned long nmk_pin_gpio_modes[] = {
1317 PIN_GPIOMODE_DISABLED,
1318 PIN_GPIOMODE_ENABLED,
1319};
1320
1321static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1322 PIN_SLPM_PDIS_DISABLED,
1323 PIN_SLPM_PDIS_ENABLED,
1324};
1325
1326struct nmk_cfg_param {
1327 const char *property;
1328 unsigned long config;
1329 const unsigned long *choice;
1330 int size;
1331};
1332
1333static const struct nmk_cfg_param nmk_cfg_params[] = {
1334 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1335 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1336 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1337 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1338 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1339 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1340 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1341 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1342};
1343
1344static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1345{
1346 if (nmk_cfg_params[index].choice == NULL)
1347 *config = nmk_cfg_params[index].config;
1348 else {
1349
1350 if (val < nmk_cfg_params[index].size) {
1351 *config = nmk_cfg_params[index].config |
1352 nmk_cfg_params[index].choice[val];
1353 }
1354 }
1355 return 0;
1356}
1357
1358static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1359{
1360 int i, pin_number;
1361 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1362
1363 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1364 for (i = 0; i < npct->soc->npins; i++)
1365 if (npct->soc->pins[i].number == pin_number)
1366 return npct->soc->pins[i].name;
1367 return NULL;
1368}
1369
1370static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1371 unsigned long *configs)
1372{
1373 bool has_config = 0;
1374 unsigned long cfg = 0;
1375 int i, val, ret;
1376
1377 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1378 ret = of_property_read_u32(np,
1379 nmk_cfg_params[i].property, &val);
1380 if (ret != -EINVAL) {
1381 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1382 *configs |= cfg;
1383 has_config = 1;
1384 }
1385 }
1386 }
1387
1388 return has_config;
1389}
1390
1391static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1392 struct device_node *np,
1393 struct pinctrl_map **map,
1394 unsigned *reserved_maps,
1395 unsigned *num_maps)
1396{
1397 int ret;
1398 const char *function = NULL;
1399 unsigned long configs = 0;
1400 bool has_config = 0;
1401 struct property *prop;
1402 struct device_node *np_config;
1403
1404 ret = of_property_read_string(np, "function", &function);
1405 if (ret >= 0) {
1406 const char *group;
1407
1408 ret = of_property_count_strings(np, "groups");
1409 if (ret < 0)
1410 goto exit;
1411
1412 ret = pinctrl_utils_reserve_map(pctldev, map,
1413 reserved_maps,
1414 num_maps, ret);
1415 if (ret < 0)
1416 goto exit;
1417
1418 of_property_for_each_string(np, "groups", prop, group) {
1419 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1420 group, function);
1421 if (ret < 0)
1422 goto exit;
1423 }
1424 }
1425
1426 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1427 np_config = of_parse_phandle(np, "ste,config", 0);
1428 if (np_config)
1429 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1430 if (has_config) {
1431 const char *gpio_name;
1432 const char *pin;
1433
1434 ret = of_property_count_strings(np, "pins");
1435 if (ret < 0)
1436 goto exit;
1437 ret = pinctrl_utils_reserve_map(pctldev, map,
1438 reserved_maps,
1439 num_maps, ret);
1440 if (ret < 0)
1441 goto exit;
1442
1443 of_property_for_each_string(np, "pins", prop, pin) {
1444 gpio_name = nmk_find_pin_name(pctldev, pin);
1445
1446 ret = nmk_dt_add_map_configs(map, reserved_maps,
1447 num_maps,
1448 gpio_name, &configs, 1);
1449 if (ret < 0)
1450 goto exit;
1451 }
1452 }
1453
1454exit:
1455 return ret;
1456}
1457
1458static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1459 struct device_node *np_config,
1460 struct pinctrl_map **map, unsigned *num_maps)
1461{
1462 unsigned reserved_maps;
1463 struct device_node *np;
1464 int ret;
1465
1466 reserved_maps = 0;
1467 *map = NULL;
1468 *num_maps = 0;
1469
1470 for_each_child_of_node(np_config, np) {
1471 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1472 &reserved_maps, num_maps);
1473 if (ret < 0) {
1474 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1475 of_node_put(np);
1476 return ret;
1477 }
1478 }
1479
1480 return 0;
1481}
1482
1483static const struct pinctrl_ops nmk_pinctrl_ops = {
1484 .get_groups_count = nmk_get_groups_cnt,
1485 .get_group_name = nmk_get_group_name,
1486 .get_group_pins = nmk_get_group_pins,
1487 .pin_dbg_show = nmk_pin_dbg_show,
1488 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1489 .dt_free_map = pinctrl_utils_free_map,
1490};
1491
1492static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1493{
1494 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1495
1496 return npct->soc->nfunctions;
1497}
1498
1499static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1500 unsigned function)
1501{
1502 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1503
1504 return npct->soc->functions[function].name;
1505}
1506
1507static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1508 unsigned function,
1509 const char * const **groups,
1510 unsigned * const num_groups)
1511{
1512 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1513
1514 *groups = npct->soc->functions[function].groups;
1515 *num_groups = npct->soc->functions[function].ngroups;
1516
1517 return 0;
1518}
1519
1520static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1521 unsigned group)
1522{
1523 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1524 const struct nmk_pingroup *g;
1525 static unsigned int slpm[NUM_BANKS];
1526 unsigned long flags = 0;
1527 bool glitch;
1528 int ret = -EINVAL;
1529 int i;
1530
1531 g = &npct->soc->groups[group];
1532
1533 if (g->altsetting < 0)
1534 return -EINVAL;
1535
1536 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1560
1561 if (glitch) {
1562 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1563
1564
1565 memset(slpm, 0xff, sizeof(slpm));
1566
1567
1568
1569
1570
1571 for (i = 0; i < g->npins; i++)
1572 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1573 nmk_gpio_glitch_slpm_init(slpm);
1574 }
1575
1576 for (i = 0; i < g->npins; i++) {
1577 struct nmk_gpio_chip *nmk_chip;
1578 unsigned bit;
1579
1580 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1581 if (!nmk_chip) {
1582 dev_err(npct->dev,
1583 "invalid pin offset %d in group %s at index %d\n",
1584 g->pins[i], g->name, i);
1585 goto out_glitch;
1586 }
1587 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1588
1589 clk_enable(nmk_chip->clk);
1590 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1591
1592
1593
1594
1595
1596
1597
1598 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1599
1600 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1601 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1602 clk_disable(nmk_chip->clk);
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1613 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1614 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1615 }
1616
1617
1618 ret = 0;
1619
1620out_glitch:
1621 if (glitch) {
1622 nmk_gpio_glitch_slpm_restore(slpm);
1623 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1624 }
1625
1626 return ret;
1627}
1628
1629static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1630 struct pinctrl_gpio_range *range,
1631 unsigned offset)
1632{
1633 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1634 struct nmk_gpio_chip *nmk_chip;
1635 struct gpio_chip *chip;
1636 unsigned bit;
1637
1638 if (!range) {
1639 dev_err(npct->dev, "invalid range\n");
1640 return -EINVAL;
1641 }
1642 if (!range->gc) {
1643 dev_err(npct->dev, "missing GPIO chip in range\n");
1644 return -EINVAL;
1645 }
1646 chip = range->gc;
1647 nmk_chip = gpiochip_get_data(chip);
1648
1649 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1650
1651 clk_enable(nmk_chip->clk);
1652 bit = offset % NMK_GPIO_PER_CHIP;
1653
1654 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1655 clk_disable(nmk_chip->clk);
1656
1657 return 0;
1658}
1659
1660static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1661 struct pinctrl_gpio_range *range,
1662 unsigned offset)
1663{
1664 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1665
1666 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1667
1668}
1669
1670static const struct pinmux_ops nmk_pinmux_ops = {
1671 .get_functions_count = nmk_pmx_get_funcs_cnt,
1672 .get_function_name = nmk_pmx_get_func_name,
1673 .get_function_groups = nmk_pmx_get_func_groups,
1674 .set_mux = nmk_pmx_set,
1675 .gpio_request_enable = nmk_gpio_request_enable,
1676 .gpio_disable_free = nmk_gpio_disable_free,
1677 .strict = true,
1678};
1679
1680static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1681 unsigned long *config)
1682{
1683
1684 return -EINVAL;
1685}
1686
1687static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1688 unsigned long *configs, unsigned num_configs)
1689{
1690 static const char *pullnames[] = {
1691 [NMK_GPIO_PULL_NONE] = "none",
1692 [NMK_GPIO_PULL_UP] = "up",
1693 [NMK_GPIO_PULL_DOWN] = "down",
1694 [3] = "??"
1695 };
1696 static const char *slpmnames[] = {
1697 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1698 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1699 };
1700 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1701 struct nmk_gpio_chip *nmk_chip;
1702 unsigned bit;
1703 pin_cfg_t cfg;
1704 int pull, slpm, output, val, i;
1705 bool lowemi, gpiomode, sleep;
1706
1707 nmk_chip = find_nmk_gpio_from_pin(pin);
1708 if (!nmk_chip) {
1709 dev_err(npct->dev,
1710 "invalid pin offset %d\n", pin);
1711 return -EINVAL;
1712 }
1713
1714 for (i = 0; i < num_configs; i++) {
1715
1716
1717
1718
1719
1720 cfg = (pin_cfg_t) configs[i];
1721 pull = PIN_PULL(cfg);
1722 slpm = PIN_SLPM(cfg);
1723 output = PIN_DIR(cfg);
1724 val = PIN_VAL(cfg);
1725 lowemi = PIN_LOWEMI(cfg);
1726 gpiomode = PIN_GPIOMODE(cfg);
1727 sleep = PIN_SLEEPMODE(cfg);
1728
1729 if (sleep) {
1730 int slpm_pull = PIN_SLPM_PULL(cfg);
1731 int slpm_output = PIN_SLPM_DIR(cfg);
1732 int slpm_val = PIN_SLPM_VAL(cfg);
1733
1734
1735 gpiomode = true;
1736
1737
1738
1739
1740
1741 if (slpm_pull)
1742 pull = slpm_pull - 1;
1743 if (slpm_output)
1744 output = slpm_output - 1;
1745 if (slpm_val)
1746 val = slpm_val - 1;
1747
1748 dev_dbg(nmk_chip->chip.parent,
1749 "pin %d: sleep pull %s, dir %s, val %s\n",
1750 pin,
1751 slpm_pull ? pullnames[pull] : "same",
1752 slpm_output ? (output ? "output" : "input")
1753 : "same",
1754 slpm_val ? (val ? "high" : "low") : "same");
1755 }
1756
1757 dev_dbg(nmk_chip->chip.parent,
1758 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1759 pin, cfg, pullnames[pull], slpmnames[slpm],
1760 output ? "output " : "input",
1761 output ? (val ? "high" : "low") : "",
1762 lowemi ? "on" : "off");
1763
1764 clk_enable(nmk_chip->clk);
1765 bit = pin % NMK_GPIO_PER_CHIP;
1766 if (gpiomode)
1767
1768 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1769 if (output)
1770 __nmk_gpio_make_output(nmk_chip, bit, val);
1771 else {
1772 __nmk_gpio_make_input(nmk_chip, bit);
1773 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1774 }
1775
1776 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1777
1778 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1779 clk_disable(nmk_chip->clk);
1780 }
1781
1782 return 0;
1783}
1784
1785static const struct pinconf_ops nmk_pinconf_ops = {
1786 .pin_config_get = nmk_pin_config_get,
1787 .pin_config_set = nmk_pin_config_set,
1788};
1789
1790static struct pinctrl_desc nmk_pinctrl_desc = {
1791 .name = "pinctrl-nomadik",
1792 .pctlops = &nmk_pinctrl_ops,
1793 .pmxops = &nmk_pinmux_ops,
1794 .confops = &nmk_pinconf_ops,
1795 .owner = THIS_MODULE,
1796};
1797
1798static const struct of_device_id nmk_pinctrl_match[] = {
1799 {
1800 .compatible = "stericsson,stn8815-pinctrl",
1801 .data = (void *)PINCTRL_NMK_STN8815,
1802 },
1803 {
1804 .compatible = "stericsson,db8500-pinctrl",
1805 .data = (void *)PINCTRL_NMK_DB8500,
1806 },
1807 {
1808 .compatible = "stericsson,db8540-pinctrl",
1809 .data = (void *)PINCTRL_NMK_DB8540,
1810 },
1811 {},
1812};
1813
1814#ifdef CONFIG_PM_SLEEP
1815static int nmk_pinctrl_suspend(struct device *dev)
1816{
1817 struct nmk_pinctrl *npct;
1818
1819 npct = dev_get_drvdata(dev);
1820 if (!npct)
1821 return -EINVAL;
1822
1823 return pinctrl_force_sleep(npct->pctl);
1824}
1825
1826static int nmk_pinctrl_resume(struct device *dev)
1827{
1828 struct nmk_pinctrl *npct;
1829
1830 npct = dev_get_drvdata(dev);
1831 if (!npct)
1832 return -EINVAL;
1833
1834 return pinctrl_force_default(npct->pctl);
1835}
1836#endif
1837
1838static int nmk_pinctrl_probe(struct platform_device *pdev)
1839{
1840 const struct of_device_id *match;
1841 struct device_node *np = pdev->dev.of_node;
1842 struct device_node *prcm_np;
1843 struct nmk_pinctrl *npct;
1844 unsigned int version = 0;
1845 int i;
1846
1847 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1848 if (!npct)
1849 return -ENOMEM;
1850
1851 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1852 if (!match)
1853 return -ENODEV;
1854 version = (unsigned int) match->data;
1855
1856
1857 if (version == PINCTRL_NMK_STN8815)
1858 nmk_pinctrl_stn8815_init(&npct->soc);
1859 if (version == PINCTRL_NMK_DB8500)
1860 nmk_pinctrl_db8500_init(&npct->soc);
1861 if (version == PINCTRL_NMK_DB8540)
1862 nmk_pinctrl_db8540_init(&npct->soc);
1863
1864
1865
1866
1867
1868
1869
1870
1871 for (i = 0; i < NMK_MAX_BANKS; i++) {
1872 struct device_node *gpio_np;
1873 struct nmk_gpio_chip *nmk_chip;
1874
1875 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1876 if (gpio_np) {
1877 dev_info(&pdev->dev,
1878 "populate NMK GPIO %d \"%pOFn\"\n",
1879 i, gpio_np);
1880 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1881 if (IS_ERR(nmk_chip))
1882 dev_err(&pdev->dev,
1883 "could not populate nmk chip struct "
1884 "- continue anyway\n");
1885 of_node_put(gpio_np);
1886 }
1887 }
1888
1889 prcm_np = of_parse_phandle(np, "prcm", 0);
1890 if (prcm_np)
1891 npct->prcm_base = of_iomap(prcm_np, 0);
1892 if (!npct->prcm_base) {
1893 if (version == PINCTRL_NMK_STN8815) {
1894 dev_info(&pdev->dev,
1895 "No PRCM base, "
1896 "assuming no ALT-Cx control is available\n");
1897 } else {
1898 dev_err(&pdev->dev, "missing PRCM base address\n");
1899 return -EINVAL;
1900 }
1901 }
1902
1903 nmk_pinctrl_desc.pins = npct->soc->pins;
1904 nmk_pinctrl_desc.npins = npct->soc->npins;
1905 npct->dev = &pdev->dev;
1906
1907 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1908 if (IS_ERR(npct->pctl)) {
1909 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1910 return PTR_ERR(npct->pctl);
1911 }
1912
1913 platform_set_drvdata(pdev, npct);
1914 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1915
1916 return 0;
1917}
1918
1919static const struct of_device_id nmk_gpio_match[] = {
1920 { .compatible = "st,nomadik-gpio", },
1921 {}
1922};
1923
1924static struct platform_driver nmk_gpio_driver = {
1925 .driver = {
1926 .name = "gpio",
1927 .of_match_table = nmk_gpio_match,
1928 },
1929 .probe = nmk_gpio_probe,
1930};
1931
1932static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1933 nmk_pinctrl_suspend,
1934 nmk_pinctrl_resume);
1935
1936static struct platform_driver nmk_pinctrl_driver = {
1937 .driver = {
1938 .name = "pinctrl-nomadik",
1939 .of_match_table = nmk_pinctrl_match,
1940 .pm = &nmk_pinctrl_pm_ops,
1941 },
1942 .probe = nmk_pinctrl_probe,
1943};
1944
1945static int __init nmk_gpio_init(void)
1946{
1947 return platform_driver_register(&nmk_gpio_driver);
1948}
1949subsys_initcall(nmk_gpio_init);
1950
1951static int __init nmk_pinctrl_init(void)
1952{
1953 return platform_driver_register(&nmk_pinctrl_driver);
1954}
1955core_initcall(nmk_pinctrl_init);
1956