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9#ifndef _PINCTRL_AMD_H
10#define _PINCTRL_AMD_H
11
12#define AMD_GPIO_PINS_PER_BANK 64
13
14#define AMD_GPIO_PINS_BANK0 63
15#define AMD_GPIO_PINS_BANK1 64
16#define AMD_GPIO_PINS_BANK2 56
17#define AMD_GPIO_PINS_BANK3 32
18
19#define WAKE_INT_MASTER_REG 0xfc
20#define EOI_MASK (1 << 29)
21
22#define WAKE_INT_STATUS_REG0 0x2f8
23#define WAKE_INT_STATUS_REG1 0x2fc
24
25#define DB_TMR_OUT_OFF 0
26#define DB_TMR_OUT_UNIT_OFF 4
27#define DB_CNTRL_OFF 5
28#define DB_TMR_LARGE_OFF 7
29#define LEVEL_TRIG_OFF 8
30#define ACTIVE_LEVEL_OFF 9
31#define INTERRUPT_ENABLE_OFF 11
32#define INTERRUPT_MASK_OFF 12
33#define WAKE_CNTRL_OFF_S0I3 13
34#define WAKE_CNTRL_OFF_S3 14
35#define WAKE_CNTRL_OFF_S4 15
36#define PIN_STS_OFF 16
37#define DRV_STRENGTH_SEL_OFF 17
38#define PULL_UP_SEL_OFF 19
39#define PULL_UP_ENABLE_OFF 20
40#define PULL_DOWN_ENABLE_OFF 21
41#define OUTPUT_VALUE_OFF 22
42#define OUTPUT_ENABLE_OFF 23
43#define SW_CNTRL_IN_OFF 24
44#define SW_CNTRL_EN_OFF 25
45#define INTERRUPT_STS_OFF 28
46#define WAKE_STS_OFF 29
47
48#define DB_TMR_OUT_MASK 0xFUL
49#define DB_CNTRl_MASK 0x3UL
50#define ACTIVE_LEVEL_MASK 0x3UL
51#define DRV_STRENGTH_SEL_MASK 0x3UL
52
53#define ACTIVE_LEVEL_HIGH 0x0UL
54#define ACTIVE_LEVEL_LOW 0x1UL
55#define ACTIVE_LEVEL_BOTH 0x2UL
56
57#define DB_TYPE_NO_DEBOUNCE 0x0UL
58#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
59#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL
60#define DB_TYPE_REMOVE_GLITCH 0x3UL
61
62#define EDGE_TRAGGER 0x0UL
63#define LEVEL_TRIGGER 0x1UL
64
65#define ACTIVE_HIGH 0x0UL
66#define ACTIVE_LOW 0x1UL
67#define BOTH_EADGE 0x2UL
68
69#define ENABLE_INTERRUPT 0x1UL
70#define DISABLE_INTERRUPT 0x0UL
71
72#define ENABLE_INTERRUPT_MASK 0x0UL
73#define DISABLE_INTERRUPT_MASK 0x1UL
74
75#define CLR_INTR_STAT 0x1UL
76
77struct amd_pingroup {
78 const char *name;
79 const unsigned *pins;
80 unsigned npins;
81};
82
83struct amd_function {
84 const char *name;
85 const char * const *groups;
86 unsigned ngroups;
87};
88
89struct amd_gpio {
90 raw_spinlock_t lock;
91 void __iomem *base;
92
93 const struct amd_pingroup *groups;
94 u32 ngroups;
95 struct pinctrl_dev *pctrl;
96 struct gpio_chip gc;
97 unsigned int hwbank_num;
98 struct resource *res;
99 struct platform_device *pdev;
100 u32 *saved_regs;
101};
102
103
104static const struct pinctrl_pin_desc kerncz_pins[] = {
105 PINCTRL_PIN(0, "GPIO_0"),
106 PINCTRL_PIN(1, "GPIO_1"),
107 PINCTRL_PIN(2, "GPIO_2"),
108 PINCTRL_PIN(3, "GPIO_3"),
109 PINCTRL_PIN(4, "GPIO_4"),
110 PINCTRL_PIN(5, "GPIO_5"),
111 PINCTRL_PIN(6, "GPIO_6"),
112 PINCTRL_PIN(7, "GPIO_7"),
113 PINCTRL_PIN(8, "GPIO_8"),
114 PINCTRL_PIN(9, "GPIO_9"),
115 PINCTRL_PIN(10, "GPIO_10"),
116 PINCTRL_PIN(11, "GPIO_11"),
117 PINCTRL_PIN(12, "GPIO_12"),
118 PINCTRL_PIN(13, "GPIO_13"),
119 PINCTRL_PIN(14, "GPIO_14"),
120 PINCTRL_PIN(15, "GPIO_15"),
121 PINCTRL_PIN(16, "GPIO_16"),
122 PINCTRL_PIN(17, "GPIO_17"),
123 PINCTRL_PIN(18, "GPIO_18"),
124 PINCTRL_PIN(19, "GPIO_19"),
125 PINCTRL_PIN(20, "GPIO_20"),
126 PINCTRL_PIN(23, "GPIO_23"),
127 PINCTRL_PIN(24, "GPIO_24"),
128 PINCTRL_PIN(25, "GPIO_25"),
129 PINCTRL_PIN(26, "GPIO_26"),
130 PINCTRL_PIN(39, "GPIO_39"),
131 PINCTRL_PIN(40, "GPIO_40"),
132 PINCTRL_PIN(43, "GPIO_42"),
133 PINCTRL_PIN(46, "GPIO_46"),
134 PINCTRL_PIN(47, "GPIO_47"),
135 PINCTRL_PIN(48, "GPIO_48"),
136 PINCTRL_PIN(49, "GPIO_49"),
137 PINCTRL_PIN(50, "GPIO_50"),
138 PINCTRL_PIN(51, "GPIO_51"),
139 PINCTRL_PIN(52, "GPIO_52"),
140 PINCTRL_PIN(53, "GPIO_53"),
141 PINCTRL_PIN(54, "GPIO_54"),
142 PINCTRL_PIN(55, "GPIO_55"),
143 PINCTRL_PIN(56, "GPIO_56"),
144 PINCTRL_PIN(57, "GPIO_57"),
145 PINCTRL_PIN(58, "GPIO_58"),
146 PINCTRL_PIN(59, "GPIO_59"),
147 PINCTRL_PIN(60, "GPIO_60"),
148 PINCTRL_PIN(61, "GPIO_61"),
149 PINCTRL_PIN(62, "GPIO_62"),
150 PINCTRL_PIN(64, "GPIO_64"),
151 PINCTRL_PIN(65, "GPIO_65"),
152 PINCTRL_PIN(66, "GPIO_66"),
153 PINCTRL_PIN(68, "GPIO_68"),
154 PINCTRL_PIN(69, "GPIO_69"),
155 PINCTRL_PIN(70, "GPIO_70"),
156 PINCTRL_PIN(71, "GPIO_71"),
157 PINCTRL_PIN(72, "GPIO_72"),
158 PINCTRL_PIN(74, "GPIO_74"),
159 PINCTRL_PIN(75, "GPIO_75"),
160 PINCTRL_PIN(76, "GPIO_76"),
161 PINCTRL_PIN(84, "GPIO_84"),
162 PINCTRL_PIN(85, "GPIO_85"),
163 PINCTRL_PIN(86, "GPIO_86"),
164 PINCTRL_PIN(87, "GPIO_87"),
165 PINCTRL_PIN(88, "GPIO_88"),
166 PINCTRL_PIN(89, "GPIO_89"),
167 PINCTRL_PIN(90, "GPIO_90"),
168 PINCTRL_PIN(91, "GPIO_91"),
169 PINCTRL_PIN(92, "GPIO_92"),
170 PINCTRL_PIN(93, "GPIO_93"),
171 PINCTRL_PIN(95, "GPIO_95"),
172 PINCTRL_PIN(96, "GPIO_96"),
173 PINCTRL_PIN(97, "GPIO_97"),
174 PINCTRL_PIN(98, "GPIO_98"),
175 PINCTRL_PIN(99, "GPIO_99"),
176 PINCTRL_PIN(100, "GPIO_100"),
177 PINCTRL_PIN(101, "GPIO_101"),
178 PINCTRL_PIN(102, "GPIO_102"),
179 PINCTRL_PIN(113, "GPIO_113"),
180 PINCTRL_PIN(114, "GPIO_114"),
181 PINCTRL_PIN(115, "GPIO_115"),
182 PINCTRL_PIN(116, "GPIO_116"),
183 PINCTRL_PIN(117, "GPIO_117"),
184 PINCTRL_PIN(118, "GPIO_118"),
185 PINCTRL_PIN(119, "GPIO_119"),
186 PINCTRL_PIN(120, "GPIO_120"),
187 PINCTRL_PIN(121, "GPIO_121"),
188 PINCTRL_PIN(122, "GPIO_122"),
189 PINCTRL_PIN(126, "GPIO_126"),
190 PINCTRL_PIN(129, "GPIO_129"),
191 PINCTRL_PIN(130, "GPIO_130"),
192 PINCTRL_PIN(131, "GPIO_131"),
193 PINCTRL_PIN(132, "GPIO_132"),
194 PINCTRL_PIN(133, "GPIO_133"),
195 PINCTRL_PIN(135, "GPIO_135"),
196 PINCTRL_PIN(136, "GPIO_136"),
197 PINCTRL_PIN(137, "GPIO_137"),
198 PINCTRL_PIN(138, "GPIO_138"),
199 PINCTRL_PIN(139, "GPIO_139"),
200 PINCTRL_PIN(140, "GPIO_140"),
201 PINCTRL_PIN(141, "GPIO_141"),
202 PINCTRL_PIN(142, "GPIO_142"),
203 PINCTRL_PIN(143, "GPIO_143"),
204 PINCTRL_PIN(144, "GPIO_144"),
205 PINCTRL_PIN(145, "GPIO_145"),
206 PINCTRL_PIN(146, "GPIO_146"),
207 PINCTRL_PIN(147, "GPIO_147"),
208 PINCTRL_PIN(148, "GPIO_148"),
209 PINCTRL_PIN(166, "GPIO_166"),
210 PINCTRL_PIN(167, "GPIO_167"),
211 PINCTRL_PIN(168, "GPIO_168"),
212 PINCTRL_PIN(169, "GPIO_169"),
213 PINCTRL_PIN(170, "GPIO_170"),
214 PINCTRL_PIN(171, "GPIO_171"),
215 PINCTRL_PIN(172, "GPIO_172"),
216 PINCTRL_PIN(173, "GPIO_173"),
217 PINCTRL_PIN(174, "GPIO_174"),
218 PINCTRL_PIN(175, "GPIO_175"),
219 PINCTRL_PIN(176, "GPIO_176"),
220 PINCTRL_PIN(177, "GPIO_177"),
221};
222
223static const unsigned i2c0_pins[] = {145, 146};
224static const unsigned i2c1_pins[] = {147, 148};
225static const unsigned i2c2_pins[] = {113, 114};
226static const unsigned i2c3_pins[] = {19, 20};
227
228static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
229static const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
230
231static const struct amd_pingroup kerncz_groups[] = {
232 {
233 .name = "i2c0",
234 .pins = i2c0_pins,
235 .npins = 2,
236 },
237 {
238 .name = "i2c1",
239 .pins = i2c1_pins,
240 .npins = 2,
241 },
242 {
243 .name = "i2c2",
244 .pins = i2c2_pins,
245 .npins = 2,
246 },
247 {
248 .name = "i2c3",
249 .pins = i2c3_pins,
250 .npins = 2,
251 },
252 {
253 .name = "uart0",
254 .pins = uart0_pins,
255 .npins = 5,
256 },
257 {
258 .name = "uart1",
259 .pins = uart1_pins,
260 .npins = 5,
261 },
262};
263
264#endif
265
