1
2
3
4
5
6
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
23#include <linux/interrupt.h>
24#include <linux/workqueue.h>
25#include <linux/firmware.h>
26#include <linux/aer.h>
27#include <linux/mutex.h>
28#include <linux/btree.h>
29
30#include <scsi/scsi.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_transport_fc.h>
35#include <scsi/scsi_bsg_fc.h>
36
37
38typedef struct {
39 uint8_t domain;
40 uint8_t area;
41 uint8_t al_pa;
42} be_id_t;
43
44
45typedef struct {
46 uint8_t al_pa;
47 uint8_t area;
48 uint8_t domain;
49} le_id_t;
50
51#include "qla_bsg.h"
52#include "qla_dsd.h"
53#include "qla_nx.h"
54#include "qla_nx2.h"
55#include "qla_nvme.h"
56#define QLA2XXX_DRIVER_NAME "qla2xxx"
57#define QLA2XXX_APIDEV "ql2xapidev"
58#define QLA2XXX_MANUFACTURER "QLogic Corporation"
59
60
61
62
63
64
65#define MAILBOX_REGISTER_COUNT_2100 8
66#define MAILBOX_REGISTER_COUNT_2200 24
67#define MAILBOX_REGISTER_COUNT 32
68
69#define QLA2200A_RISC_ROM_VER 4
70#define FPM_2300 6
71#define FPM_2310 7
72
73#include "qla_settings.h"
74
75#define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
76
77
78
79
80#define BIT_0 0x1
81#define BIT_1 0x2
82#define BIT_2 0x4
83#define BIT_3 0x8
84#define BIT_4 0x10
85#define BIT_5 0x20
86#define BIT_6 0x40
87#define BIT_7 0x80
88#define BIT_8 0x100
89#define BIT_9 0x200
90#define BIT_10 0x400
91#define BIT_11 0x800
92#define BIT_12 0x1000
93#define BIT_13 0x2000
94#define BIT_14 0x4000
95#define BIT_15 0x8000
96#define BIT_16 0x10000
97#define BIT_17 0x20000
98#define BIT_18 0x40000
99#define BIT_19 0x80000
100#define BIT_20 0x100000
101#define BIT_21 0x200000
102#define BIT_22 0x400000
103#define BIT_23 0x800000
104#define BIT_24 0x1000000
105#define BIT_25 0x2000000
106#define BIT_26 0x4000000
107#define BIT_27 0x8000000
108#define BIT_28 0x10000000
109#define BIT_29 0x20000000
110#define BIT_30 0x40000000
111#define BIT_31 0x80000000
112
113#define LSB(x) ((uint8_t)(x))
114#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
115
116#define LSW(x) ((uint16_t)(x))
117#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
118
119#define LSD(x) ((uint32_t)((uint64_t)(x)))
120#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
121
122static inline uint32_t make_handle(uint16_t x, uint16_t y)
123{
124 return ((uint32_t)x << 16) | y;
125}
126
127
128
129
130
131static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
132{
133 return readb(addr);
134}
135
136static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
137{
138 return readw(addr);
139}
140
141static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
142{
143 return readl(addr);
144}
145
146static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
147{
148 return readb_relaxed(addr);
149}
150
151static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
152{
153 return readw_relaxed(addr);
154}
155
156static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
157{
158 return readl_relaxed(addr);
159}
160
161static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
162{
163 return writeb(data, addr);
164}
165
166static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
167{
168 return writew(data, addr);
169}
170
171static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
172{
173 return writel(data, addr);
174}
175
176
177
178
179#define QLA83XX_LED_PORT0 0x00201320
180#define QLA83XX_LED_PORT1 0x00201328
181#define QLA83XX_IDC_DEV_STATE 0x22102384
182#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
183#define QLA83XX_IDC_MINOR_VERSION 0x22102398
184#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
185#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
186#define QLA83XX_IDC_CONTROL 0x22102390
187#define QLA83XX_IDC_AUDIT 0x22102394
188#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
189#define QLA83XX_DRIVER_LOCKID 0x22102104
190#define QLA83XX_DRIVER_LOCK 0x8111c028
191#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
192#define QLA83XX_FLASH_LOCKID 0x22102100
193#define QLA83XX_FLASH_LOCK 0x8111c010
194#define QLA83XX_FLASH_UNLOCK 0x8111c014
195#define QLA83XX_DEV_PARTINFO1 0x221023e0
196#define QLA83XX_DEV_PARTINFO2 0x221023e4
197#define QLA83XX_FW_HEARTBEAT 0x221020b0
198#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
199#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
200
201
202#define IDC_DEVICE_STATE_CHANGE BIT_0
203#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
204#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
205#define IDC_HEARTBEAT_FAILURE BIT_3
206
207
208#define ERR_LEVEL_NON_FATAL 0x1
209#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
210#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
211
212
213#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
214#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
215
216
217#define QLA83XX_NIC_CORE_RESET 0x1
218#define QLA83XX_IDC_STATE_HANDLER 0x2
219#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
220
221
222#define QLA83XX_IDC_RESET_DISABLED BIT_0
223#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
224
225
226#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
227#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
228#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
229
230
231#define QLA83XX_CLASS_TYPE_NONE 0x0
232#define QLA83XX_CLASS_TYPE_NIC 0x1
233#define QLA83XX_CLASS_TYPE_FCOE 0x2
234#define QLA83XX_CLASS_TYPE_ISCSI 0x3
235
236
237#define IDC_LOCK_RECOVERY_STAGE1 0x1
238
239
240#define IDC_LOCK_RECOVERY_STAGE2 0x2
241
242
243#define IDC_AUDIT_TIMESTAMP 0x0
244
245
246
247#define IDC_AUDIT_COMPLETION 0x1
248
249
250
251
252#define PORT_0_2031 0x00201340
253#define PORT_1_2031 0x00201350
254#define LASER_ON_2031 0x01800100
255#define LASER_OFF_2031 0x01800180
256
257
258
259
260
261#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
262#define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
263
264
265
266
267#define WWN_SIZE 8
268#define MAX_FIBRE_DEVICES_2100 512
269#define MAX_FIBRE_DEVICES_2400 2048
270#define MAX_FIBRE_DEVICES_LOOP 128
271#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
272#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
273#define MAX_FIBRE_LUNS 0xFFFF
274#define MAX_HOST_COUNT 16
275
276
277
278
279#define MAX_BUSES 1
280#define MIN_LUNS 8
281#define MAX_LUNS MAX_FIBRE_LUNS
282#define MAX_CMDS_PER_LUN 255
283
284
285
286
287#define SNS_LAST_LOOP_ID_2100 0xfe
288#define SNS_LAST_LOOP_ID_2300 0x7ff
289
290#define LAST_LOCAL_LOOP_ID 0x7d
291#define SNS_FL_PORT 0x7e
292#define FABRIC_CONTROLLER 0x7f
293#define SIMPLE_NAME_SERVER 0x80
294#define SNS_FIRST_LOOP_ID 0x81
295#define MANAGEMENT_SERVER 0xfe
296#define BROADCAST 0xff
297
298
299
300
301
302#define NPH_LAST_HANDLE 0x7ee
303#define NPH_MGMT_SERVER 0x7ef
304#define NPH_SNS 0x7fc
305#define NPH_FABRIC_CONTROLLER 0x7fd
306#define NPH_F_PORT 0x7fe
307#define NPH_IP_BROADCAST 0x7ff
308
309#define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
310
311#define MAX_CMDSZ 16
312#include "qla_fw.h"
313
314struct name_list_extended {
315 struct get_name_list_extended *l;
316 dma_addr_t ldma;
317 struct list_head fcports;
318 u32 size;
319 u8 sent;
320};
321
322
323
324#define PORT_RETRY_TIME 1
325#define LOOP_DOWN_TIMEOUT 60
326#define LOOP_DOWN_TIME 255
327#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
328
329#define DEFAULT_OUTSTANDING_COMMANDS 4096
330#define MIN_OUTSTANDING_COMMANDS 128
331
332
333#define REQUEST_ENTRY_CNT_2100 128
334#define REQUEST_ENTRY_CNT_2200 2048
335#define REQUEST_ENTRY_CNT_24XX 2048
336#define REQUEST_ENTRY_CNT_83XX 8192
337#define RESPONSE_ENTRY_CNT_83XX 4096
338#define RESPONSE_ENTRY_CNT_2100 64
339#define RESPONSE_ENTRY_CNT_2300 512
340#define RESPONSE_ENTRY_CNT_MQ 128
341#define ATIO_ENTRY_CNT_24XX 4096
342#define RESPONSE_ENTRY_CNT_FX00 256
343#define FW_DEF_EXCHANGES_CNT 2048
344#define FW_MAX_EXCHANGES_CNT (32 * 1024)
345#define REDUCE_EXCHANGES_CNT (8 * 1024)
346
347struct req_que;
348struct qla_tgt_sess;
349
350
351
352
353struct srb_cmd {
354 struct scsi_cmnd *cmd;
355 uint32_t request_sense_length;
356 uint32_t fw_sense_length;
357 uint8_t *request_sense_ptr;
358 struct ct6_dsd *ct6_ctx;
359 struct crc_context *crc_ctx;
360};
361
362
363
364
365#define SRB_DMA_VALID BIT_0
366#define SRB_FCP_CMND_DMA_VALID BIT_12
367#define SRB_CRC_CTX_DMA_VALID BIT_2
368#define SRB_CRC_PROT_DMA_VALID BIT_4
369#define SRB_CRC_CTX_DSD_VALID BIT_5
370#define SRB_WAKEUP_ON_COMP BIT_6
371#define SRB_DIF_BUNDL_DMA_VALID BIT_7
372
373
374#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
375
376
377
378
379typedef union {
380 uint32_t b24 : 24;
381
382 struct {
383#ifdef __BIG_ENDIAN
384 uint8_t domain;
385 uint8_t area;
386 uint8_t al_pa;
387#elif defined(__LITTLE_ENDIAN)
388 uint8_t al_pa;
389 uint8_t area;
390 uint8_t domain;
391#else
392#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
393#endif
394 uint8_t rsvd_1;
395 } b;
396} port_id_t;
397#define INVALID_PORT_ID 0xFFFFFF
398
399static inline le_id_t be_id_to_le(be_id_t id)
400{
401 le_id_t res;
402
403 res.domain = id.domain;
404 res.area = id.area;
405 res.al_pa = id.al_pa;
406
407 return res;
408}
409
410static inline be_id_t le_id_to_be(le_id_t id)
411{
412 be_id_t res;
413
414 res.domain = id.domain;
415 res.area = id.area;
416 res.al_pa = id.al_pa;
417
418 return res;
419}
420
421static inline port_id_t be_to_port_id(be_id_t id)
422{
423 port_id_t res;
424
425 res.b.domain = id.domain;
426 res.b.area = id.area;
427 res.b.al_pa = id.al_pa;
428 res.b.rsvd_1 = 0;
429
430 return res;
431}
432
433static inline be_id_t port_id_to_be_id(port_id_t port_id)
434{
435 be_id_t res;
436
437 res.domain = port_id.b.domain;
438 res.area = port_id.b.area;
439 res.al_pa = port_id.b.al_pa;
440
441 return res;
442}
443
444struct els_logo_payload {
445 uint8_t opcode;
446 uint8_t rsvd[3];
447 uint8_t s_id[3];
448 uint8_t rsvd1[1];
449 uint8_t wwpn[WWN_SIZE];
450};
451
452struct els_plogi_payload {
453 uint8_t opcode;
454 uint8_t rsvd[3];
455 __be32 data[112 / 4];
456};
457
458struct ct_arg {
459 void *iocb;
460 u16 nport_handle;
461 dma_addr_t req_dma;
462 dma_addr_t rsp_dma;
463 u32 req_size;
464 u32 rsp_size;
465 u32 req_allocated_size;
466 u32 rsp_allocated_size;
467 void *req;
468 void *rsp;
469 port_id_t id;
470};
471
472
473
474
475struct srb_iocb {
476 union {
477 struct {
478 uint16_t flags;
479#define SRB_LOGIN_RETRIED BIT_0
480#define SRB_LOGIN_COND_PLOGI BIT_1
481#define SRB_LOGIN_SKIP_PRLI BIT_2
482#define SRB_LOGIN_NVME_PRLI BIT_3
483#define SRB_LOGIN_PRLI_ONLY BIT_4
484 uint16_t data[2];
485 u32 iop[2];
486 } logio;
487 struct {
488#define ELS_DCMD_TIMEOUT 20
489#define ELS_DCMD_LOGO 0x5
490 uint32_t flags;
491 uint32_t els_cmd;
492 struct completion comp;
493 struct els_logo_payload *els_logo_pyld;
494 dma_addr_t els_logo_pyld_dma;
495 } els_logo;
496 struct els_plogi {
497#define ELS_DCMD_PLOGI 0x3
498 uint32_t flags;
499 uint32_t els_cmd;
500 struct completion comp;
501 struct els_plogi_payload *els_plogi_pyld;
502 struct els_plogi_payload *els_resp_pyld;
503 u32 tx_size;
504 u32 rx_size;
505 dma_addr_t els_plogi_pyld_dma;
506 dma_addr_t els_resp_pyld_dma;
507 __le32 fw_status[3];
508 __le16 comp_status;
509 __le16 len;
510 } els_plogi;
511 struct {
512
513
514
515
516
517 uint64_t lun;
518 uint32_t flags;
519 uint32_t data;
520 struct completion comp;
521 __le16 comp_status;
522 } tmf;
523 struct {
524#define SRB_FXDISC_REQ_DMA_VALID BIT_0
525#define SRB_FXDISC_RESP_DMA_VALID BIT_1
526#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
527#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
528#define FXDISC_TIMEOUT 20
529 uint8_t flags;
530 uint32_t req_len;
531 uint32_t rsp_len;
532 void *req_addr;
533 void *rsp_addr;
534 dma_addr_t req_dma_handle;
535 dma_addr_t rsp_dma_handle;
536 __le32 adapter_id;
537 __le32 adapter_id_hi;
538 __le16 req_func_type;
539 __le32 req_data;
540 __le32 req_data_extra;
541 __le32 result;
542 __le32 seq_number;
543 __le16 fw_flags;
544 struct completion fxiocb_comp;
545 __le32 reserved_0;
546 uint8_t reserved_1;
547 } fxiocb;
548 struct {
549 uint32_t cmd_hndl;
550 __le16 comp_status;
551 __le16 req_que_no;
552 struct completion comp;
553 } abt;
554 struct ct_arg ctarg;
555#define MAX_IOCB_MB_REG 28
556#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
557 struct {
558 u16 in_mb[MAX_IOCB_MB_REG];
559 u16 out_mb[MAX_IOCB_MB_REG];
560 void *out, *in;
561 dma_addr_t out_dma, in_dma;
562 struct completion comp;
563 int rc;
564 } mbx;
565 struct {
566 struct imm_ntfy_from_isp *ntfy;
567 } nack;
568 struct {
569 __le16 comp_status;
570 __le16 rsp_pyld_len;
571 uint8_t aen_op;
572 void *desc;
573
574
575 int cmd_len;
576 int rsp_len;
577 dma_addr_t cmd_dma;
578 dma_addr_t rsp_dma;
579 enum nvmefc_fcp_datadir dir;
580 uint32_t dl;
581 uint32_t timeout_sec;
582 struct list_head entry;
583 } nvme;
584 struct {
585 u16 cmd;
586 u16 vp_index;
587 } ctrlvp;
588 } u;
589
590 struct timer_list timer;
591 void (*timeout)(void *);
592};
593
594
595#define SRB_LOGIN_CMD 1
596#define SRB_LOGOUT_CMD 2
597#define SRB_ELS_CMD_RPT 3
598#define SRB_ELS_CMD_HST 4
599#define SRB_CT_CMD 5
600#define SRB_ADISC_CMD 6
601#define SRB_TM_CMD 7
602#define SRB_SCSI_CMD 8
603#define SRB_BIDI_CMD 9
604#define SRB_FXIOCB_DCMD 10
605#define SRB_FXIOCB_BCMD 11
606#define SRB_ABT_CMD 12
607#define SRB_ELS_DCMD 13
608#define SRB_MB_IOCB 14
609#define SRB_CT_PTHRU_CMD 15
610#define SRB_NACK_PLOGI 16
611#define SRB_NACK_PRLI 17
612#define SRB_NACK_LOGO 18
613#define SRB_NVME_CMD 19
614#define SRB_NVME_LS 20
615#define SRB_PRLI_CMD 21
616#define SRB_CTRL_VP 22
617#define SRB_PRLO_CMD 23
618
619enum {
620 TYPE_SRB,
621 TYPE_TGT_CMD,
622 TYPE_TGT_TMCMD,
623};
624
625typedef struct srb {
626
627
628
629
630 uint8_t cmd_type;
631 uint8_t pad[3];
632 struct kref cmd_kref;
633 void *priv;
634 wait_queue_head_t nvme_ls_waitq;
635 struct fc_port *fcport;
636 struct scsi_qla_host *vha;
637 unsigned int start_timer:1;
638
639 uint32_t handle;
640 uint16_t flags;
641 uint16_t type;
642 const char *name;
643 int iocbs;
644 struct qla_qpair *qpair;
645 struct srb *cmd_sp;
646 struct list_head elem;
647 u32 gen1;
648 u32 gen2;
649 int rc;
650 int retry_count;
651 struct completion *comp;
652 union {
653 struct srb_iocb iocb_cmd;
654 struct bsg_job *bsg_job;
655 struct srb_cmd scmd;
656 } u;
657
658
659
660
661
662 void (*done)(struct srb *sp, int res);
663
664 void (*free)(struct srb *sp);
665
666
667
668
669 void (*put_fn)(struct kref *kref);
670} srb_t;
671
672#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
673
674#define GET_CMD_SENSE_LEN(sp) \
675 (sp->u.scmd.request_sense_length)
676#define SET_CMD_SENSE_LEN(sp, len) \
677 (sp->u.scmd.request_sense_length = len)
678#define GET_CMD_SENSE_PTR(sp) \
679 (sp->u.scmd.request_sense_ptr)
680#define SET_CMD_SENSE_PTR(sp, ptr) \
681 (sp->u.scmd.request_sense_ptr = ptr)
682#define GET_FW_SENSE_LEN(sp) \
683 (sp->u.scmd.fw_sense_length)
684#define SET_FW_SENSE_LEN(sp, len) \
685 (sp->u.scmd.fw_sense_length = len)
686
687struct msg_echo_lb {
688 dma_addr_t send_dma;
689 dma_addr_t rcv_dma;
690 uint16_t req_sg_cnt;
691 uint16_t rsp_sg_cnt;
692 uint16_t options;
693 uint32_t transfer_size;
694 uint32_t iteration_count;
695};
696
697
698
699
700struct device_reg_2xxx {
701 __le16 flash_address;
702 __le16 flash_data;
703 __le16 unused_1[1];
704 __le16 ctrl_status;
705#define CSR_FLASH_64K_BANK BIT_3
706#define CSR_FLASH_ENABLE BIT_1
707#define CSR_ISP_SOFT_RESET BIT_0
708
709 __le16 ictrl;
710#define ICR_EN_INT BIT_15
711#define ICR_EN_RISC BIT_3
712
713 __le16 istatus;
714#define ISR_RISC_INT BIT_3
715
716 __le16 semaphore;
717 __le16 nvram;
718#define NVR_DESELECT 0
719#define NVR_BUSY BIT_15
720#define NVR_WRT_ENABLE BIT_14
721#define NVR_PR_ENABLE BIT_13
722#define NVR_DATA_IN BIT_3
723#define NVR_DATA_OUT BIT_2
724#define NVR_SELECT BIT_1
725#define NVR_CLOCK BIT_0
726
727#define NVR_WAIT_CNT 20000
728
729 union {
730 struct {
731 __le16 mailbox0;
732 __le16 mailbox1;
733 __le16 mailbox2;
734 __le16 mailbox3;
735 __le16 mailbox4;
736 __le16 mailbox5;
737 __le16 mailbox6;
738 __le16 mailbox7;
739 __le16 unused_2[59];
740 } __attribute__((packed)) isp2100;
741 struct {
742
743 __le16 req_q_in;
744 __le16 req_q_out;
745
746 __le16 rsp_q_in;
747 __le16 rsp_q_out;
748
749
750 __le32 host_status;
751#define HSR_RISC_INT BIT_15
752#define HSR_RISC_PAUSED BIT_8
753
754
755 __le16 host_semaphore;
756 __le16 unused_3[17];
757 __le16 mailbox0;
758 __le16 mailbox1;
759 __le16 mailbox2;
760 __le16 mailbox3;
761 __le16 mailbox4;
762 __le16 mailbox5;
763 __le16 mailbox6;
764 __le16 mailbox7;
765 __le16 mailbox8;
766 __le16 mailbox9;
767 __le16 mailbox10;
768 __le16 mailbox11;
769 __le16 mailbox12;
770 __le16 mailbox13;
771 __le16 mailbox14;
772 __le16 mailbox15;
773 __le16 mailbox16;
774 __le16 mailbox17;
775 __le16 mailbox18;
776 __le16 mailbox19;
777 __le16 mailbox20;
778 __le16 mailbox21;
779 __le16 mailbox22;
780 __le16 mailbox23;
781 __le16 mailbox24;
782 __le16 mailbox25;
783 __le16 mailbox26;
784 __le16 mailbox27;
785 __le16 mailbox28;
786 __le16 mailbox29;
787 __le16 mailbox30;
788 __le16 mailbox31;
789 __le16 fb_cmd;
790 __le16 unused_4[10];
791 } __attribute__((packed)) isp2300;
792 } u;
793
794 __le16 fpm_diag_config;
795 __le16 unused_5[0x4];
796 __le16 risc_hw;
797 __le16 unused_5_1;
798 __le16 pcr;
799 __le16 unused_6[0x5];
800 __le16 mctr;
801 __le16 unused_7[0x3];
802 __le16 fb_cmd_2100;
803 __le16 unused_8[0x3];
804 __le16 hccr;
805#define HCCR_HOST_INT BIT_7
806#define HCCR_RISC_PAUSE BIT_5
807
808#define HCCR_RESET_RISC 0x1000
809#define HCCR_PAUSE_RISC 0x2000
810#define HCCR_RELEASE_RISC 0x3000
811#define HCCR_SET_HOST_INT 0x5000
812#define HCCR_CLR_HOST_INT 0x6000
813#define HCCR_CLR_RISC_INT 0x7000
814#define HCCR_DISABLE_PARITY_PAUSE 0x4001
815#define HCCR_ENABLE_PARITY 0xA000
816
817 __le16 unused_9[5];
818 __le16 gpiod;
819 __le16 gpioe;
820#define GPIO_LED_MASK 0x00C0
821#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
822#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
823#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
824#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
825#define GPIO_LED_ALL_OFF 0x0000
826#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
827#define GPIO_LED_RGA_ON 0x00C1
828
829 union {
830 struct {
831 __le16 unused_10[8];
832 __le16 mailbox8;
833 __le16 mailbox9;
834 __le16 mailbox10;
835 __le16 mailbox11;
836 __le16 mailbox12;
837 __le16 mailbox13;
838 __le16 mailbox14;
839 __le16 mailbox15;
840 __le16 mailbox16;
841 __le16 mailbox17;
842 __le16 mailbox18;
843 __le16 mailbox19;
844 __le16 mailbox20;
845 __le16 mailbox21;
846 __le16 mailbox22;
847 __le16 mailbox23;
848 } __attribute__((packed)) isp2200;
849 } u_end;
850};
851
852struct device_reg_25xxmq {
853 __le32 req_q_in;
854 __le32 req_q_out;
855 __le32 rsp_q_in;
856 __le32 rsp_q_out;
857 __le32 atio_q_in;
858 __le32 atio_q_out;
859};
860
861
862struct device_reg_fx00 {
863 __le32 mailbox0;
864 __le32 mailbox1;
865 __le32 mailbox2;
866 __le32 mailbox3;
867 __le32 mailbox4;
868 __le32 mailbox5;
869 __le32 mailbox6;
870 __le32 mailbox7;
871 __le32 mailbox8;
872 __le32 mailbox9;
873 __le32 mailbox10;
874 __le32 mailbox11;
875 __le32 mailbox12;
876 __le32 mailbox13;
877 __le32 mailbox14;
878 __le32 mailbox15;
879 __le32 mailbox16;
880 __le32 mailbox17;
881 __le32 mailbox18;
882 __le32 mailbox19;
883 __le32 mailbox20;
884 __le32 mailbox21;
885 __le32 mailbox22;
886 __le32 mailbox23;
887 __le32 mailbox24;
888 __le32 mailbox25;
889 __le32 mailbox26;
890 __le32 mailbox27;
891 __le32 mailbox28;
892 __le32 mailbox29;
893 __le32 mailbox30;
894 __le32 mailbox31;
895 __le32 aenmailbox0;
896 __le32 aenmailbox1;
897 __le32 aenmailbox2;
898 __le32 aenmailbox3;
899 __le32 aenmailbox4;
900 __le32 aenmailbox5;
901 __le32 aenmailbox6;
902 __le32 aenmailbox7;
903
904 __le32 req_q_in;
905 __le32 req_q_out;
906
907 __le32 rsp_q_in;
908 __le32 rsp_q_out;
909
910 __le32 initval0;
911 __le32 initval1;
912 __le32 initval2;
913 __le32 initval3;
914 __le32 initval4;
915 __le32 initval5;
916 __le32 initval6;
917 __le32 initval7;
918 __le32 fwheartbeat;
919 __le32 pseudoaen;
920};
921
922
923
924typedef union {
925 struct device_reg_2xxx isp;
926 struct device_reg_24xx isp24;
927 struct device_reg_25xxmq isp25mq;
928 struct device_reg_82xx isp82;
929 struct device_reg_fx00 ispfx00;
930} __iomem device_reg_t;
931
932#define ISP_REQ_Q_IN(ha, reg) \
933 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
934 &(reg)->u.isp2100.mailbox4 : \
935 &(reg)->u.isp2300.req_q_in)
936#define ISP_REQ_Q_OUT(ha, reg) \
937 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
938 &(reg)->u.isp2100.mailbox4 : \
939 &(reg)->u.isp2300.req_q_out)
940#define ISP_RSP_Q_IN(ha, reg) \
941 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
942 &(reg)->u.isp2100.mailbox5 : \
943 &(reg)->u.isp2300.rsp_q_in)
944#define ISP_RSP_Q_OUT(ha, reg) \
945 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
946 &(reg)->u.isp2100.mailbox5 : \
947 &(reg)->u.isp2300.rsp_q_out)
948
949#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
950#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
951
952#define MAILBOX_REG(ha, reg, num) \
953 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
954 (num < 8 ? \
955 &(reg)->u.isp2100.mailbox0 + (num) : \
956 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
957 &(reg)->u.isp2300.mailbox0 + (num))
958#define RD_MAILBOX_REG(ha, reg, num) \
959 rd_reg_word(MAILBOX_REG(ha, reg, num))
960#define WRT_MAILBOX_REG(ha, reg, num, data) \
961 wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
962
963#define FB_CMD_REG(ha, reg) \
964 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
965 &(reg)->fb_cmd_2100 : \
966 &(reg)->u.isp2300.fb_cmd)
967#define RD_FB_CMD_REG(ha, reg) \
968 rd_reg_word(FB_CMD_REG(ha, reg))
969#define WRT_FB_CMD_REG(ha, reg, data) \
970 wrt_reg_word(FB_CMD_REG(ha, reg), data)
971
972typedef struct {
973 uint32_t out_mb;
974 uint32_t in_mb;
975 uint16_t mb[MAILBOX_REGISTER_COUNT];
976 long buf_size;
977 void *bufp;
978 uint32_t tov;
979 uint8_t flags;
980#define MBX_DMA_IN BIT_0
981#define MBX_DMA_OUT BIT_1
982#define IOCTL_CMD BIT_2
983} mbx_cmd_t;
984
985struct mbx_cmd_32 {
986 uint32_t out_mb;
987 uint32_t in_mb;
988 uint32_t mb[MAILBOX_REGISTER_COUNT];
989 long buf_size;
990 void *bufp;
991 uint32_t tov;
992 uint8_t flags;
993#define MBX_DMA_IN BIT_0
994#define MBX_DMA_OUT BIT_1
995#define IOCTL_CMD BIT_2
996};
997
998
999#define MBX_TOV_SECONDS 30
1000
1001
1002
1003
1004#define PROD_ID_1 0x4953
1005#define PROD_ID_2 0x0000
1006#define PROD_ID_2a 0x5020
1007#define PROD_ID_3 0x2020
1008
1009
1010
1011
1012#define MBS_FRM_ALIVE 0
1013#define MBS_CHKSUM_ERR 1
1014#define MBS_BUSY 4
1015
1016
1017
1018
1019#define MBS_COMMAND_COMPLETE 0x4000
1020#define MBS_INVALID_COMMAND 0x4001
1021#define MBS_HOST_INTERFACE_ERROR 0x4002
1022#define MBS_TEST_FAILED 0x4003
1023#define MBS_COMMAND_ERROR 0x4005
1024#define MBS_COMMAND_PARAMETER_ERROR 0x4006
1025#define MBS_PORT_ID_USED 0x4007
1026#define MBS_LOOP_ID_USED 0x4008
1027#define MBS_ALL_IDS_IN_USE 0x4009
1028#define MBS_NOT_LOGGED_IN 0x400A
1029#define MBS_LINK_DOWN_ERROR 0x400B
1030#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1031
1032static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
1033{
1034 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1035}
1036
1037
1038
1039
1040#define MBA_ASYNC_EVENT 0x8000
1041#define MBA_RESET 0x8001
1042#define MBA_SYSTEM_ERR 0x8002
1043#define MBA_REQ_TRANSFER_ERR 0x8003
1044#define MBA_RSP_TRANSFER_ERR 0x8004
1045#define MBA_WAKEUP_THRES 0x8005
1046#define MBA_LIP_OCCURRED 0x8010
1047
1048#define MBA_LOOP_UP 0x8011
1049#define MBA_LOOP_DOWN 0x8012
1050#define MBA_LIP_RESET 0x8013
1051#define MBA_PORT_UPDATE 0x8014
1052#define MBA_RSCN_UPDATE 0x8015
1053#define MBA_LIP_F8 0x8016
1054#define MBA_LOOP_INIT_ERR 0x8017
1055#define MBA_FABRIC_AUTH_REQ 0x801b
1056#define MBA_SCSI_COMPLETION 0x8020
1057#define MBA_CTIO_COMPLETION 0x8021
1058#define MBA_IP_COMPLETION 0x8022
1059#define MBA_IP_RECEIVE 0x8023
1060#define MBA_IP_BROADCAST 0x8024
1061#define MBA_IP_LOW_WATER_MARK 0x8025
1062#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
1063#define MBA_IP_HDR_DATA_SPLIT 0x8027
1064
1065#define MBA_TRACE_NOTIFICATION 0x8028
1066#define MBA_POINT_TO_POINT 0x8030
1067#define MBA_CMPLT_1_16BIT 0x8031
1068#define MBA_CMPLT_2_16BIT 0x8032
1069#define MBA_CMPLT_3_16BIT 0x8033
1070#define MBA_CMPLT_4_16BIT 0x8034
1071#define MBA_CMPLT_5_16BIT 0x8035
1072#define MBA_CHG_IN_CONNECTION 0x8036
1073#define MBA_RIO_RESPONSE 0x8040
1074#define MBA_ZIO_RESPONSE 0x8040
1075#define MBA_CMPLT_2_32BIT 0x8042
1076#define MBA_BYPASS_NOTIFICATION 0x8043
1077#define MBA_DISCARD_RND_FRAME 0x8048
1078#define MBA_REJECTED_FCP_CMD 0x8049
1079#define MBA_FW_NOT_STARTED 0x8050
1080#define MBA_FW_STARTING 0x8051
1081#define MBA_FW_RESTART_CMPLT 0x8060
1082#define MBA_INIT_REQUIRED 0x8061
1083#define MBA_SHUTDOWN_REQUESTED 0x8062
1084#define MBA_TEMPERATURE_ALERT 0x8070
1085#define MBA_DPORT_DIAGNOSTICS 0x8080
1086#define MBA_TRANS_INSERT 0x8130
1087#define MBA_TRANS_REMOVE 0x8131
1088#define MBA_FW_INIT_FAILURE 0x8401
1089#define MBA_MIRROR_LUN_CHANGE 0x8402
1090
1091#define MBA_FW_POLL_STATE 0x8600
1092#define MBA_FW_RESET_FCT 0x8502
1093#define MBA_FW_INIT_INPROGRESS 0x8500
1094
1095#define MBA_IDC_AEN 0x8200
1096
1097
1098#define INTR_ROM_MB_SUCCESS 0x1
1099#define INTR_ROM_MB_FAILED 0x2
1100#define INTR_MB_SUCCESS 0x10
1101#define INTR_MB_FAILED 0x11
1102#define INTR_ASYNC_EVENT 0x12
1103#define INTR_RSP_QUE_UPDATE 0x13
1104#define INTR_RSP_QUE_UPDATE_83XX 0x14
1105#define INTR_ATIO_QUE_UPDATE 0x1C
1106#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1107#define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1108
1109
1110#define MBS_LB_RESET 0x17
1111
1112
1113
1114#define FO1_AE_ON_LIPF8 BIT_0
1115#define FO1_AE_ALL_LIP_RESET BIT_1
1116#define FO1_CTIO_RETRY BIT_3
1117#define FO1_DISABLE_LIP_F7_SW BIT_4
1118#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1119#define FO1_DISABLE_GPIO6_7 BIT_6
1120#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1121#define FO1_SET_EMPHASIS_SWING BIT_8
1122#define FO1_AE_AUTO_BYPASS BIT_9
1123#define FO1_ENABLE_PURE_IOCB BIT_10
1124#define FO1_AE_PLOGI_RJT BIT_11
1125#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1126#define FO1_AE_QUEUE_FULL BIT_13
1127
1128#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1129#define FO2_REV_LOOPBACK BIT_1
1130
1131#define FO3_ENABLE_EMERG_IOCB BIT_0
1132#define FO3_AE_RND_ERROR BIT_1
1133
1134
1135#define ADD_FO_COUNT 3
1136#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
1137#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1138
1139#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1140
1141#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1142
1143
1144
1145
1146#define MBC_LOAD_RAM 1
1147#define MBC_EXECUTE_FIRMWARE 2
1148#define MBC_READ_RAM_WORD 5
1149#define MBC_MAILBOX_REGISTER_TEST 6
1150#define MBC_VERIFY_CHECKSUM 7
1151#define MBC_GET_FIRMWARE_VERSION 8
1152#define MBC_LOAD_RISC_RAM 9
1153#define MBC_DUMP_RISC_RAM 0xa
1154#define MBC_SECURE_FLASH_UPDATE 0xa
1155#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
1156#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
1157#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
1158#define MBC_READ_RAM_EXTENDED 0xf
1159#define MBC_IOCB_COMMAND 0x12
1160#define MBC_STOP_FIRMWARE 0x14
1161#define MBC_ABORT_COMMAND 0x15
1162#define MBC_ABORT_DEVICE 0x16
1163#define MBC_ABORT_TARGET 0x17
1164#define MBC_RESET 0x18
1165#define MBC_GET_ADAPTER_LOOP_ID 0x20
1166#define MBC_GET_SET_ZIO_THRESHOLD 0x21
1167#define MBC_GET_RETRY_COUNT 0x22
1168#define MBC_DISABLE_VI 0x24
1169#define MBC_ENABLE_VI 0x25
1170#define MBC_GET_FIRMWARE_OPTION 0x28
1171#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34
1172#define MBC_SET_FIRMWARE_OPTION 0x38
1173#define MBC_SET_GET_FC_LED_CONFIG 0x3b
1174#define MBC_LOOP_PORT_BYPASS 0x40
1175#define MBC_LOOP_PORT_ENABLE 0x41
1176#define MBC_GET_RESOURCE_COUNTS 0x42
1177#define MBC_NON_PARTICIPATE 0x43
1178#define MBC_DIAGNOSTIC_ECHO 0x44
1179#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
1180#define MBC_ONLINE_SELF_TEST 0x46
1181#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
1182#define MBC_CONFIGURE_VF 0x4b
1183#define MBC_RESET_LINK_STATUS 0x52
1184#define MBC_IOCB_COMMAND_A64 0x54
1185#define MBC_PORT_LOGOUT 0x56
1186#define MBC_SEND_RNID_ELS 0x57
1187#define MBC_SET_RNID_PARAMS 0x59
1188#define MBC_GET_RNID_PARAMS 0x5a
1189#define MBC_DATA_RATE 0x5d
1190#define MBC_INITIALIZE_FIRMWARE 0x60
1191#define MBC_INITIATE_LIP 0x62
1192
1193#define MBC_GET_FC_AL_POSITION_MAP 0x63
1194#define MBC_GET_PORT_DATABASE 0x64
1195#define MBC_CLEAR_ACA 0x65
1196#define MBC_TARGET_RESET 0x66
1197#define MBC_CLEAR_TASK_SET 0x67
1198#define MBC_ABORT_TASK_SET 0x68
1199#define MBC_GET_FIRMWARE_STATE 0x69
1200#define MBC_GET_PORT_NAME 0x6a
1201#define MBC_GET_LINK_STATUS 0x6b
1202#define MBC_LIP_RESET 0x6c
1203#define MBC_SEND_SNS_COMMAND 0x6e
1204
1205#define MBC_LOGIN_FABRIC_PORT 0x6f
1206#define MBC_SEND_CHANGE_REQUEST 0x70
1207#define MBC_LOGOUT_FABRIC_PORT 0x71
1208#define MBC_LIP_FULL_LOGIN 0x72
1209#define MBC_LOGIN_LOOP_PORT 0x74
1210#define MBC_PORT_NODE_NAME_LIST 0x75
1211#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
1212#define MBC_UNLOAD_IP 0x79
1213#define MBC_GET_ID_LIST 0x7C
1214#define MBC_SEND_LFA_COMMAND 0x7D
1215#define MBC_LUN_RESET 0x7E
1216
1217
1218
1219
1220
1221#define MBC_MR_DRV_SHUTDOWN 0x6A
1222
1223
1224
1225
1226#define MBC_WRITE_SERDES 0x3
1227#define MBC_READ_SERDES 0x4
1228#define MBC_LOAD_DUMP_MPI_RAM 0x5
1229#define MBC_SERDES_PARAMS 0x10
1230#define MBC_GET_IOCB_STATUS 0x12
1231#define MBC_PORT_PARAMS 0x1A
1232#define MBC_GET_TIMEOUT_PARAMS 0x22
1233#define MBC_TRACE_CONTROL 0x27
1234#define MBC_GEN_SYSTEM_ERROR 0x2a
1235#define MBC_WRITE_SFP 0x30
1236#define MBC_READ_SFP 0x31
1237#define MBC_SET_TIMEOUT_PARAMS 0x32
1238#define MBC_DPORT_DIAGNOSTICS 0x47
1239#define MBC_MID_INITIALIZE_FIRMWARE 0x48
1240#define MBC_MID_GET_VP_DATABASE 0x49
1241#define MBC_MID_GET_VP_ENTRY 0x4a
1242#define MBC_HOST_MEMORY_COPY 0x53
1243#define MBC_SEND_RNFT_ELS 0x5e
1244#define MBC_GET_LINK_PRIV_STATS 0x6d
1245#define MBC_LINK_INITIALIZATION 0x72
1246#define MBC_SET_VENDOR_ID 0x76
1247#define MBC_PORT_RESET 0x120
1248#define MBC_SET_PORT_CONFIG 0x122
1249#define MBC_GET_PORT_CONFIG 0x123
1250
1251
1252
1253
1254#define MBC_WRITE_MPI_REGISTER 0x01
1255
1256
1257
1258
1259#define MBC_SET_GET_ETH_SERDES_REG 0x150
1260#define HCS_WRITE_SERDES 0x3
1261#define HCS_READ_SERDES 0x4
1262
1263
1264#define FCAL_MAP_SIZE 128
1265
1266
1267#define MBX_31 BIT_31
1268#define MBX_30 BIT_30
1269#define MBX_29 BIT_29
1270#define MBX_28 BIT_28
1271#define MBX_27 BIT_27
1272#define MBX_26 BIT_26
1273#define MBX_25 BIT_25
1274#define MBX_24 BIT_24
1275#define MBX_23 BIT_23
1276#define MBX_22 BIT_22
1277#define MBX_21 BIT_21
1278#define MBX_20 BIT_20
1279#define MBX_19 BIT_19
1280#define MBX_18 BIT_18
1281#define MBX_17 BIT_17
1282#define MBX_16 BIT_16
1283#define MBX_15 BIT_15
1284#define MBX_14 BIT_14
1285#define MBX_13 BIT_13
1286#define MBX_12 BIT_12
1287#define MBX_11 BIT_11
1288#define MBX_10 BIT_10
1289#define MBX_9 BIT_9
1290#define MBX_8 BIT_8
1291#define MBX_7 BIT_7
1292#define MBX_6 BIT_6
1293#define MBX_5 BIT_5
1294#define MBX_4 BIT_4
1295#define MBX_3 BIT_3
1296#define MBX_2 BIT_2
1297#define MBX_1 BIT_1
1298#define MBX_0 BIT_0
1299
1300#define RNID_TYPE_ELS_CMD 0x5
1301#define RNID_TYPE_PORT_LOGIN 0x7
1302#define RNID_BUFFER_CREDITS 0x8
1303#define RNID_TYPE_SET_VERSION 0x9
1304#define RNID_TYPE_ASIC_TEMP 0xC
1305
1306#define ELS_CMD_MAP_SIZE 32
1307#define ELS_COMMAND_RDP 0x18
1308
1309
1310
1311
1312#define FSTATE_CONFIG_WAIT 0
1313#define FSTATE_WAIT_AL_PA 1
1314#define FSTATE_WAIT_LOGIN 2
1315#define FSTATE_READY 3
1316#define FSTATE_LOSS_OF_SYNC 4
1317#define FSTATE_ERROR 5
1318#define FSTATE_REINIT 6
1319#define FSTATE_NON_PART 7
1320
1321#define FSTATE_CONFIG_CORRECT 0
1322#define FSTATE_P2P_RCV_LIP 1
1323#define FSTATE_P2P_CHOOSE_LOOP 2
1324#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1325#define FSTATE_FATAL_ERROR 4
1326#define FSTATE_LOOP_BACK_CONN 5
1327
1328#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1329#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1330#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1331#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1332#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1333#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1334#define QLA27XX_DEFAULT_IMAGE 0
1335#define QLA27XX_PRIMARY_IMAGE 1
1336#define QLA27XX_SECONDARY_IMAGE 2
1337
1338
1339
1340
1341
1342#define PORT_DATABASE_SIZE 128
1343typedef struct {
1344 uint8_t options;
1345 uint8_t control;
1346 uint8_t master_state;
1347 uint8_t slave_state;
1348 uint8_t reserved[2];
1349 uint8_t hard_address;
1350 uint8_t reserved_1;
1351 uint8_t port_id[4];
1352 uint8_t node_name[WWN_SIZE];
1353 uint8_t port_name[WWN_SIZE];
1354 __le16 execution_throttle;
1355 uint16_t execution_count;
1356 uint8_t reset_count;
1357 uint8_t reserved_2;
1358 uint16_t resource_allocation;
1359 uint16_t current_allocation;
1360 uint16_t queue_head;
1361 uint16_t queue_tail;
1362 uint16_t transmit_execution_list_next;
1363 uint16_t transmit_execution_list_previous;
1364 uint16_t common_features;
1365 uint16_t total_concurrent_sequences;
1366 uint16_t RO_by_information_category;
1367 uint8_t recipient;
1368 uint8_t initiator;
1369 uint16_t receive_data_size;
1370 uint16_t concurrent_sequences;
1371 uint16_t open_sequences_per_exchange;
1372 uint16_t lun_abort_flags;
1373 uint16_t lun_stop_flags;
1374 uint16_t stop_queue_head;
1375 uint16_t stop_queue_tail;
1376 uint16_t port_retry_timer;
1377 uint16_t next_sequence_id;
1378 uint16_t frame_count;
1379 uint16_t PRLI_payload_length;
1380 uint8_t prli_svc_param_word_0[2];
1381
1382 uint8_t prli_svc_param_word_3[2];
1383
1384 uint16_t loop_id;
1385 uint16_t extended_lun_info_list_pointer;
1386 uint16_t extended_lun_stop_list_pointer;
1387} port_database_t;
1388
1389
1390
1391
1392#define PD_STATE_DISCOVERY 0
1393#define PD_STATE_WAIT_DISCOVERY_ACK 1
1394#define PD_STATE_PORT_LOGIN 2
1395#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1396#define PD_STATE_PROCESS_LOGIN 4
1397#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1398#define PD_STATE_PORT_LOGGED_IN 6
1399#define PD_STATE_PORT_UNAVAILABLE 7
1400#define PD_STATE_PROCESS_LOGOUT 8
1401#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1402#define PD_STATE_PORT_LOGOUT 10
1403#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1404
1405
1406#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1407#define QLA_ZIO_DISABLED 0
1408#define QLA_ZIO_DEFAULT_TIMER 2
1409
1410
1411
1412
1413
1414#define ICB_VERSION 1
1415typedef struct {
1416 uint8_t version;
1417 uint8_t reserved_1;
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438 uint8_t firmware_options[2];
1439
1440 __le16 frame_payload_size;
1441 __le16 max_iocb_allocation;
1442 __le16 execution_throttle;
1443 uint8_t retry_count;
1444 uint8_t retry_delay;
1445 uint8_t port_name[WWN_SIZE];
1446 uint16_t hard_address;
1447 uint8_t inquiry_data;
1448 uint8_t login_timeout;
1449 uint8_t node_name[WWN_SIZE];
1450
1451 __le16 request_q_outpointer;
1452 __le16 response_q_inpointer;
1453 __le16 request_q_length;
1454 __le16 response_q_length;
1455 __le64 request_q_address __packed;
1456 __le64 response_q_address __packed;
1457
1458 __le16 lun_enables;
1459 uint8_t command_resource_count;
1460 uint8_t immediate_notify_resource_count;
1461 __le16 timeout;
1462 uint8_t reserved_2[2];
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483 uint8_t add_firmware_options[2];
1484
1485 uint8_t response_accumulation_timer;
1486 uint8_t interrupt_delay_timer;
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507 uint8_t special_options[2];
1508
1509 uint8_t reserved_3[26];
1510} init_cb_t;
1511
1512
1513
1514
1515#define GLSO_SEND_RPS BIT_0
1516#define GLSO_USE_DID BIT_3
1517
1518struct link_statistics {
1519 __le32 link_fail_cnt;
1520 __le32 loss_sync_cnt;
1521 __le32 loss_sig_cnt;
1522 __le32 prim_seq_err_cnt;
1523 __le32 inval_xmit_word_cnt;
1524 __le32 inval_crc_cnt;
1525 __le32 lip_cnt;
1526 __le32 link_up_cnt;
1527 __le32 link_down_loop_init_tmo;
1528 __le32 link_down_los;
1529 __le32 link_down_loss_rcv_clk;
1530 uint32_t reserved0[5];
1531 __le32 port_cfg_chg;
1532 uint32_t reserved1[11];
1533 __le32 rsp_q_full;
1534 __le32 atio_q_full;
1535 __le32 drop_ae;
1536 __le32 els_proto_err;
1537 __le32 reserved2;
1538 __le32 tx_frames;
1539 __le32 rx_frames;
1540 __le32 discarded_frames;
1541 __le32 dropped_frames;
1542 uint32_t reserved3;
1543 __le32 nos_rcvd;
1544 uint32_t reserved4[4];
1545 __le32 tx_prjt;
1546 __le32 rcv_exfail;
1547 __le32 rcv_abts;
1548 __le32 seq_frm_miss;
1549 __le32 corr_err;
1550 __le32 mb_rqst;
1551 __le32 nport_full;
1552 __le32 eofa;
1553 uint32_t reserved5;
1554 __le64 fpm_recv_word_cnt;
1555 __le64 fpm_disc_word_cnt;
1556 __le64 fpm_xmit_word_cnt;
1557 uint32_t reserved6[70];
1558};
1559
1560
1561
1562
1563#define NV_START_BIT BIT_2
1564#define NV_WRITE_OP (BIT_26+BIT_24)
1565#define NV_READ_OP (BIT_26+BIT_25)
1566#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1567#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1568#define NV_DELAY_COUNT 10
1569
1570
1571
1572
1573typedef struct {
1574
1575
1576
1577 uint8_t id[4];
1578 uint8_t nvram_version;
1579 uint8_t reserved_0;
1580
1581
1582
1583
1584 uint8_t parameter_block_version;
1585 uint8_t reserved_1;
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606 uint8_t firmware_options[2];
1607
1608 uint16_t frame_payload_size;
1609 __le16 max_iocb_allocation;
1610 __le16 execution_throttle;
1611 uint8_t retry_count;
1612 uint8_t retry_delay;
1613 uint8_t port_name[WWN_SIZE];
1614 uint16_t hard_address;
1615 uint8_t inquiry_data;
1616 uint8_t login_timeout;
1617 uint8_t node_name[WWN_SIZE];
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638 uint8_t add_firmware_options[2];
1639
1640 uint8_t response_accumulation_timer;
1641 uint8_t interrupt_delay_timer;
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662 uint8_t special_options[2];
1663
1664
1665 uint8_t reserved_2[22];
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704 uint8_t seriallink_options[4];
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727 uint8_t host_p[2];
1728
1729 uint8_t boot_node_name[WWN_SIZE];
1730 uint8_t boot_lun_number;
1731 uint8_t reset_delay;
1732 uint8_t port_down_retry_count;
1733 uint8_t boot_id_number;
1734 __le16 max_luns_per_target;
1735 uint8_t fcode_boot_port_name[WWN_SIZE];
1736 uint8_t alternate_port_name[WWN_SIZE];
1737 uint8_t alternate_node_name[WWN_SIZE];
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749 uint8_t efi_parameters;
1750
1751 uint8_t link_down_timeout;
1752
1753 uint8_t adapter_id[16];
1754
1755 uint8_t alt1_boot_node_name[WWN_SIZE];
1756 uint16_t alt1_boot_lun_number;
1757 uint8_t alt2_boot_node_name[WWN_SIZE];
1758 uint16_t alt2_boot_lun_number;
1759 uint8_t alt3_boot_node_name[WWN_SIZE];
1760 uint16_t alt3_boot_lun_number;
1761 uint8_t alt4_boot_node_name[WWN_SIZE];
1762 uint16_t alt4_boot_lun_number;
1763 uint8_t alt5_boot_node_name[WWN_SIZE];
1764 uint16_t alt5_boot_lun_number;
1765 uint8_t alt6_boot_node_name[WWN_SIZE];
1766 uint16_t alt6_boot_lun_number;
1767 uint8_t alt7_boot_node_name[WWN_SIZE];
1768 uint16_t alt7_boot_lun_number;
1769
1770 uint8_t reserved_3[2];
1771
1772
1773 uint8_t model_number[16];
1774
1775
1776 uint8_t oem_specific[16];
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799 uint8_t adapter_features[2];
1800
1801 uint8_t reserved_4[16];
1802
1803
1804 uint16_t subsystem_vendor_id_2200;
1805
1806
1807 uint16_t subsystem_device_id_2200;
1808
1809 uint8_t reserved_5;
1810 uint8_t checksum;
1811} nvram_t;
1812
1813
1814
1815
1816typedef struct {
1817 uint8_t entry_type;
1818 uint8_t entry_count;
1819 uint8_t sys_define;
1820 uint8_t entry_status;
1821 uint32_t handle;
1822 uint8_t data[52];
1823 uint32_t signature;
1824#define RESPONSE_PROCESSED 0xDEADDEAD
1825} response_t;
1826
1827
1828
1829
1830struct atio {
1831 uint8_t entry_type;
1832 uint8_t entry_count;
1833 __le16 attr_n_length;
1834 uint8_t data[56];
1835 uint32_t signature;
1836#define ATIO_PROCESSED 0xDEADDEAD
1837};
1838
1839typedef union {
1840 __le16 extended;
1841 struct {
1842 uint8_t reserved;
1843 uint8_t standard;
1844 } id;
1845} target_id_t;
1846
1847#define SET_TARGET_ID(ha, to, from) \
1848do { \
1849 if (HAS_EXTENDED_IDS(ha)) \
1850 to.extended = cpu_to_le16(from); \
1851 else \
1852 to.id.standard = (uint8_t)from; \
1853} while (0)
1854
1855
1856
1857
1858#define COMMAND_TYPE 0x11
1859typedef struct {
1860 uint8_t entry_type;
1861 uint8_t entry_count;
1862 uint8_t sys_define;
1863 uint8_t entry_status;
1864 uint32_t handle;
1865 target_id_t target;
1866 __le16 lun;
1867 __le16 control_flags;
1868#define CF_WRITE BIT_6
1869#define CF_READ BIT_5
1870#define CF_SIMPLE_TAG BIT_3
1871#define CF_ORDERED_TAG BIT_2
1872#define CF_HEAD_TAG BIT_1
1873 uint16_t reserved_1;
1874 __le16 timeout;
1875 __le16 dseg_count;
1876 uint8_t scsi_cdb[MAX_CMDSZ];
1877 __le32 byte_count;
1878 union {
1879 struct dsd32 dsd32[3];
1880 struct dsd64 dsd64[2];
1881 };
1882} cmd_entry_t;
1883
1884
1885
1886
1887#define COMMAND_A64_TYPE 0x19
1888typedef struct {
1889 uint8_t entry_type;
1890 uint8_t entry_count;
1891 uint8_t sys_define;
1892 uint8_t entry_status;
1893 uint32_t handle;
1894 target_id_t target;
1895 __le16 lun;
1896 __le16 control_flags;
1897 uint16_t reserved_1;
1898 __le16 timeout;
1899 __le16 dseg_count;
1900 uint8_t scsi_cdb[MAX_CMDSZ];
1901 uint32_t byte_count;
1902 struct dsd64 dsd[2];
1903} cmd_a64_entry_t, request_t;
1904
1905
1906
1907
1908#define CONTINUE_TYPE 0x02
1909typedef struct {
1910 uint8_t entry_type;
1911 uint8_t entry_count;
1912 uint8_t sys_define;
1913 uint8_t entry_status;
1914 uint32_t reserved;
1915 struct dsd32 dsd[7];
1916} cont_entry_t;
1917
1918
1919
1920
1921#define CONTINUE_A64_TYPE 0x0A
1922typedef struct {
1923 uint8_t entry_type;
1924 uint8_t entry_count;
1925 uint8_t sys_define;
1926 uint8_t entry_status;
1927 struct dsd64 dsd[5];
1928} cont_a64_entry_t;
1929
1930#define PO_MODE_DIF_INSERT 0
1931#define PO_MODE_DIF_REMOVE 1
1932#define PO_MODE_DIF_PASS 2
1933#define PO_MODE_DIF_REPLACE 3
1934#define PO_MODE_DIF_TCP_CKSUM 6
1935#define PO_ENABLE_INCR_GUARD_SEED BIT_3
1936#define PO_DISABLE_GUARD_CHECK BIT_4
1937#define PO_DISABLE_INCR_REF_TAG BIT_5
1938#define PO_DIS_HEADER_MODE BIT_7
1939#define PO_ENABLE_DIF_BUNDLING BIT_8
1940#define PO_DIS_FRAME_MODE BIT_9
1941#define PO_DIS_VALD_APP_ESC BIT_10
1942#define PO_DIS_VALD_APP_REF_ESC BIT_11
1943
1944#define PO_DIS_APP_TAG_REPL BIT_12
1945#define PO_DIS_REF_TAG_REPL BIT_13
1946#define PO_DIS_APP_TAG_VALD BIT_14
1947#define PO_DIS_REF_TAG_VALD BIT_15
1948
1949
1950
1951
1952struct crc_context {
1953 uint32_t handle;
1954 __le32 ref_tag;
1955 __le16 app_tag;
1956 uint8_t ref_tag_mask[4];
1957 uint8_t app_tag_mask[2];
1958 __le16 guard_seed;
1959 __le16 prot_opts;
1960 __le16 blk_size;
1961 __le16 runt_blk_guard;
1962
1963 __le32 byte_count;
1964
1965 union {
1966 struct {
1967 uint32_t reserved_1;
1968 uint16_t reserved_2;
1969 uint16_t reserved_3;
1970 uint32_t reserved_4;
1971 struct dsd64 data_dsd[1];
1972 uint32_t reserved_5[2];
1973 uint32_t reserved_6;
1974 } nobundling;
1975 struct {
1976 __le32 dif_byte_count;
1977
1978 uint16_t reserved_1;
1979 __le16 dseg_count;
1980 uint32_t reserved_2;
1981 struct dsd64 data_dsd[1];
1982 struct dsd64 dif_dsd;
1983 } bundling;
1984 } u;
1985
1986 struct fcp_cmnd fcp_cmnd;
1987 dma_addr_t crc_ctx_dma;
1988
1989 struct list_head dsd_list;
1990
1991
1992 struct list_head ldif_dsd_list;
1993 u8 no_ldif_dsd;
1994
1995 struct list_head ldif_dma_hndl_list;
1996 u32 dif_bundl_len;
1997 u8 no_dif_bundl;
1998
1999};
2000
2001#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
2002#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
2003
2004
2005
2006
2007#define STATUS_TYPE 0x03
2008typedef struct {
2009 uint8_t entry_type;
2010 uint8_t entry_count;
2011 uint8_t sys_define;
2012 uint8_t entry_status;
2013 uint32_t handle;
2014 __le16 scsi_status;
2015 __le16 comp_status;
2016 __le16 state_flags;
2017 __le16 status_flags;
2018 __le16 rsp_info_len;
2019 __le16 req_sense_length;
2020 __le32 residual_length;
2021 uint8_t rsp_info[8];
2022 uint8_t req_sense_data[32];
2023} sts_entry_t;
2024
2025
2026
2027
2028#define RF_RQ_DMA_ERROR BIT_6
2029#define RF_INV_E_ORDER BIT_5
2030#define RF_INV_E_COUNT BIT_4
2031#define RF_INV_E_PARAM BIT_3
2032#define RF_INV_E_TYPE BIT_2
2033#define RF_BUSY BIT_1
2034#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2035 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2036#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2037 RF_INV_E_TYPE)
2038
2039
2040
2041
2042#define SS_MASK 0xfff
2043#define SS_RESIDUAL_UNDER BIT_11
2044#define SS_RESIDUAL_OVER BIT_10
2045#define SS_SENSE_LEN_VALID BIT_9
2046#define SS_RESPONSE_INFO_LEN_VALID BIT_8
2047#define SS_SCSI_STATUS_BYTE 0xff
2048
2049#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2050#define SS_BUSY_CONDITION BIT_3
2051#define SS_CONDITION_MET BIT_2
2052#define SS_CHECK_CONDITION BIT_1
2053
2054
2055
2056
2057#define CS_COMPLETE 0x0
2058#define CS_INCOMPLETE 0x1
2059#define CS_DMA 0x2
2060#define CS_TRANSPORT 0x3
2061#define CS_RESET 0x4
2062#define CS_ABORTED 0x5
2063#define CS_TIMEOUT 0x6
2064#define CS_DATA_OVERRUN 0x7
2065#define CS_DIF_ERROR 0xC
2066
2067#define CS_DATA_UNDERRUN 0x15
2068#define CS_QUEUE_FULL 0x1C
2069#define CS_PORT_UNAVAILABLE 0x28
2070
2071#define CS_PORT_LOGGED_OUT 0x29
2072#define CS_PORT_CONFIG_CHG 0x2A
2073#define CS_PORT_BUSY 0x2B
2074#define CS_COMPLETE_CHKCOND 0x30
2075#define CS_IOCB_ERROR 0x31
2076
2077#define CS_BAD_PAYLOAD 0x80
2078#define CS_UNKNOWN 0x81
2079#define CS_RETRY 0x82
2080#define CS_LOOP_DOWN_ABORT 0x83
2081
2082#define CS_BIDIR_RD_OVERRUN 0x700
2083#define CS_BIDIR_RD_WR_OVERRUN 0x707
2084#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2085#define CS_BIDIR_RD_UNDERRUN 0x1500
2086#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2087#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2088#define CS_BIDIR_DMA 0x200
2089
2090
2091
2092#define SF_ABTS_TERMINATED BIT_10
2093#define SF_LOGOUT_SENT BIT_13
2094
2095
2096
2097
2098#define STATUS_CONT_TYPE 0x10
2099typedef struct {
2100 uint8_t entry_type;
2101 uint8_t entry_count;
2102 uint8_t sys_define;
2103 uint8_t entry_status;
2104 uint8_t data[60];
2105} sts_cont_entry_t;
2106
2107
2108
2109
2110
2111#define STATUS_TYPE_21 0x21
2112typedef struct {
2113 uint8_t entry_type;
2114 uint8_t entry_count;
2115 uint8_t handle_count;
2116 uint8_t entry_status;
2117 uint32_t handle[15];
2118} sts21_entry_t;
2119
2120
2121
2122
2123
2124#define STATUS_TYPE_22 0x22
2125typedef struct {
2126 uint8_t entry_type;
2127 uint8_t entry_count;
2128 uint8_t handle_count;
2129 uint8_t entry_status;
2130 uint16_t handle[30];
2131} sts22_entry_t;
2132
2133
2134
2135
2136#define MARKER_TYPE 0x04
2137typedef struct {
2138 uint8_t entry_type;
2139 uint8_t entry_count;
2140 uint8_t handle_count;
2141 uint8_t entry_status;
2142 uint32_t sys_define_2;
2143 target_id_t target;
2144 uint8_t modifier;
2145#define MK_SYNC_ID_LUN 0
2146#define MK_SYNC_ID 1
2147#define MK_SYNC_ALL 2
2148#define MK_SYNC_LIP 3
2149
2150
2151 uint8_t reserved_1;
2152 __le16 sequence_number;
2153 __le16 lun;
2154 uint8_t reserved_2[48];
2155} mrk_entry_t;
2156
2157
2158
2159
2160#define MS_IOCB_TYPE 0x29
2161typedef struct {
2162 uint8_t entry_type;
2163 uint8_t entry_count;
2164 uint8_t handle_count;
2165 uint8_t entry_status;
2166 uint32_t handle1;
2167 target_id_t loop_id;
2168 __le16 status;
2169 __le16 control_flags;
2170 uint16_t reserved2;
2171 __le16 timeout;
2172 __le16 cmd_dsd_count;
2173 __le16 total_dsd_count;
2174 uint8_t type;
2175 uint8_t r_ctl;
2176 __le16 rx_id;
2177 uint16_t reserved3;
2178 uint32_t handle2;
2179 __le32 rsp_bytecount;
2180 __le32 req_bytecount;
2181 struct dsd64 req_dsd;
2182 struct dsd64 rsp_dsd;
2183} ms_iocb_entry_t;
2184
2185
2186
2187
2188
2189#define MBX_IOCB_TYPE 0x39
2190struct mbx_entry {
2191 uint8_t entry_type;
2192 uint8_t entry_count;
2193 uint8_t sys_define1;
2194
2195#define SOURCE_SCSI 0x00
2196#define SOURCE_IP 0x01
2197#define SOURCE_VI 0x02
2198#define SOURCE_SCTP 0x03
2199#define SOURCE_MP 0x04
2200#define SOURCE_MPIOCTL 0x05
2201#define SOURCE_ASYNC_IOCB 0x07
2202
2203 uint8_t entry_status;
2204
2205 uint32_t handle;
2206 target_id_t loop_id;
2207
2208 __le16 status;
2209 __le16 state_flags;
2210 __le16 status_flags;
2211
2212 uint32_t sys_define2[2];
2213
2214 __le16 mb0;
2215 __le16 mb1;
2216 __le16 mb2;
2217 __le16 mb3;
2218 __le16 mb6;
2219 __le16 mb7;
2220 __le16 mb9;
2221 __le16 mb10;
2222 uint32_t reserved_2[2];
2223 uint8_t node_name[WWN_SIZE];
2224 uint8_t port_name[WWN_SIZE];
2225};
2226
2227#ifndef IMMED_NOTIFY_TYPE
2228#define IMMED_NOTIFY_TYPE 0x0D
2229
2230
2231
2232
2233
2234
2235
2236struct imm_ntfy_from_isp {
2237 uint8_t entry_type;
2238 uint8_t entry_count;
2239 uint8_t sys_define;
2240 uint8_t entry_status;
2241 union {
2242 struct {
2243 __le32 sys_define_2;
2244 target_id_t target;
2245 __le16 lun;
2246 uint8_t target_id;
2247 uint8_t reserved_1;
2248 __le16 status_modifier;
2249 __le16 status;
2250 __le16 task_flags;
2251 __le16 seq_id;
2252 __le16 srr_rx_id;
2253 __le32 srr_rel_offs;
2254 __le16 srr_ui;
2255#define SRR_IU_DATA_IN 0x1
2256#define SRR_IU_DATA_OUT 0x5
2257#define SRR_IU_STATUS 0x7
2258 __le16 srr_ox_id;
2259 uint8_t reserved_2[28];
2260 } isp2x;
2261 struct {
2262 uint32_t reserved;
2263 __le16 nport_handle;
2264 uint16_t reserved_2;
2265 __le16 flags;
2266#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2267#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2268 __le16 srr_rx_id;
2269 __le16 status;
2270 uint8_t status_subcode;
2271 uint8_t fw_handle;
2272 __le32 exchange_address;
2273 __le32 srr_rel_offs;
2274 __le16 srr_ui;
2275 __le16 srr_ox_id;
2276 union {
2277 struct {
2278 uint8_t node_name[8];
2279 } plogi;
2280 struct {
2281
2282 __le16 wd3_lo;
2283 uint8_t resv0[6];
2284 } prli;
2285 struct {
2286 uint8_t port_id[3];
2287 uint8_t resv1;
2288 __le16 nport_handle;
2289 uint16_t resv2;
2290 } req_els;
2291 } u;
2292 uint8_t port_name[8];
2293 uint8_t resv3[3];
2294 uint8_t vp_index;
2295 uint32_t reserved_5;
2296 uint8_t port_id[3];
2297 uint8_t reserved_6;
2298 } isp24;
2299 } u;
2300 uint16_t reserved_7;
2301 __le16 ox_id;
2302} __packed;
2303#endif
2304
2305
2306
2307
2308#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2309#define REQUEST_ENTRY_SIZE (sizeof(request_t))
2310
2311
2312
2313
2314
2315
2316typedef struct {
2317 port_id_t d_id;
2318 uint8_t node_name[WWN_SIZE];
2319 uint8_t port_name[WWN_SIZE];
2320 uint8_t fabric_port_name[WWN_SIZE];
2321 uint16_t fp_speed;
2322 uint8_t fc4_type;
2323 uint8_t fc4_features;
2324} sw_info_t;
2325
2326
2327#define FC4_TYPE_FCP_SCSI 0x08
2328#define FC4_TYPE_NVME 0x28
2329#define FC4_TYPE_OTHER 0x0
2330#define FC4_TYPE_UNKNOWN 0xff
2331
2332
2333struct mbx_24xx_entry {
2334 uint8_t entry_type;
2335 uint8_t entry_count;
2336 uint8_t sys_define1;
2337 uint8_t entry_status;
2338 uint32_t handle;
2339 uint16_t mb[28];
2340};
2341
2342#define IOCB_SIZE 64
2343
2344
2345
2346
2347typedef enum {
2348 FCT_UNKNOWN,
2349 FCT_RSCN,
2350 FCT_SWITCH,
2351 FCT_BROADCAST,
2352 FCT_INITIATOR,
2353 FCT_TARGET,
2354 FCT_NVME_INITIATOR = 0x10,
2355 FCT_NVME_TARGET = 0x20,
2356 FCT_NVME_DISCOVERY = 0x40,
2357 FCT_NVME = 0xf0,
2358} fc_port_type_t;
2359
2360enum qla_sess_deletion {
2361 QLA_SESS_DELETION_NONE = 0,
2362 QLA_SESS_DELETION_IN_PROGRESS,
2363 QLA_SESS_DELETED,
2364};
2365
2366enum qlt_plogi_link_t {
2367 QLT_PLOGI_LINK_SAME_WWN,
2368 QLT_PLOGI_LINK_CONFLICT,
2369 QLT_PLOGI_LINK_MAX
2370};
2371
2372struct qlt_plogi_ack_t {
2373 struct list_head list;
2374 struct imm_ntfy_from_isp iocb;
2375 port_id_t id;
2376 int ref_count;
2377 void *fcport;
2378};
2379
2380struct ct_sns_desc {
2381 struct ct_sns_pkt *ct_sns;
2382 dma_addr_t ct_sns_dma;
2383};
2384
2385enum discovery_state {
2386 DSC_DELETED,
2387 DSC_GNN_ID,
2388 DSC_GNL,
2389 DSC_LOGIN_PEND,
2390 DSC_LOGIN_FAILED,
2391 DSC_GPDB,
2392 DSC_UPD_FCPORT,
2393 DSC_LOGIN_COMPLETE,
2394 DSC_ADISC,
2395 DSC_DELETE_PEND,
2396};
2397
2398enum login_state {
2399 DSC_LS_LLIOCB_SENT = 2,
2400 DSC_LS_PLOGI_PEND,
2401 DSC_LS_PLOGI_COMP,
2402 DSC_LS_PRLI_PEND,
2403 DSC_LS_PRLI_COMP,
2404 DSC_LS_PORT_UNAVAIL,
2405 DSC_LS_PRLO_PEND = 9,
2406 DSC_LS_LOGO_PEND,
2407};
2408
2409enum rscn_addr_format {
2410 RSCN_PORT_ADDR,
2411 RSCN_AREA_ADDR,
2412 RSCN_DOM_ADDR,
2413 RSCN_FAB_ADDR,
2414};
2415
2416
2417
2418
2419typedef struct fc_port {
2420 struct list_head list;
2421 struct scsi_qla_host *vha;
2422
2423 uint8_t node_name[WWN_SIZE];
2424 uint8_t port_name[WWN_SIZE];
2425 port_id_t d_id;
2426 uint16_t loop_id;
2427 uint16_t old_loop_id;
2428
2429 unsigned int conf_compl_supported:1;
2430 unsigned int deleted:2;
2431 unsigned int free_pending:1;
2432 unsigned int local:1;
2433 unsigned int logout_on_delete:1;
2434 unsigned int logo_ack_needed:1;
2435 unsigned int keep_nport_handle:1;
2436 unsigned int send_els_logo:1;
2437 unsigned int login_pause:1;
2438 unsigned int login_succ:1;
2439 unsigned int query:1;
2440 unsigned int id_changed:1;
2441 unsigned int scan_needed:1;
2442 unsigned int n2n_flag:1;
2443 unsigned int explicit_logout:1;
2444 unsigned int prli_pend_timer:1;
2445
2446 struct completion nvme_del_done;
2447 uint32_t nvme_prli_service_param;
2448#define NVME_PRLI_SP_CONF BIT_7
2449#define NVME_PRLI_SP_INITIATOR BIT_5
2450#define NVME_PRLI_SP_TARGET BIT_4
2451#define NVME_PRLI_SP_DISCOVERY BIT_3
2452#define NVME_PRLI_SP_FIRST_BURST BIT_0
2453 uint8_t nvme_flag;
2454 uint32_t nvme_first_burst_size;
2455#define NVME_FLAG_REGISTERED 4
2456#define NVME_FLAG_DELETING 2
2457#define NVME_FLAG_RESETTING 1
2458
2459 struct fc_port *conflict;
2460 unsigned char logout_completed;
2461 int generation;
2462
2463 struct se_session *se_sess;
2464 struct kref sess_kref;
2465 struct qla_tgt *tgt;
2466 unsigned long expires;
2467 struct list_head del_list_entry;
2468 struct work_struct free_work;
2469 struct work_struct reg_work;
2470 uint64_t jiffies_at_registration;
2471 unsigned long prli_expired;
2472 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2473
2474 uint16_t tgt_id;
2475 uint16_t old_tgt_id;
2476 uint16_t sec_since_registration;
2477
2478 uint8_t fcp_prio;
2479
2480 uint8_t fabric_port_name[WWN_SIZE];
2481 uint16_t fp_speed;
2482
2483 fc_port_type_t port_type;
2484
2485 atomic_t state;
2486 uint32_t flags;
2487
2488 int login_retry;
2489
2490 struct fc_rport *rport, *drport;
2491 u32 supported_classes;
2492
2493 uint8_t fc4_type;
2494 uint8_t fc4_features;
2495 uint8_t scan_state;
2496
2497 unsigned long last_queue_full;
2498 unsigned long last_ramp_up;
2499
2500 uint16_t port_id;
2501
2502 struct nvme_fc_remote_port *nvme_remote_port;
2503
2504 unsigned long retry_delay_timestamp;
2505 struct qla_tgt_sess *tgt_session;
2506 struct ct_sns_desc ct_desc;
2507 enum discovery_state disc_state;
2508 atomic_t shadow_disc_state;
2509 enum discovery_state next_disc_state;
2510 enum login_state fw_login_state;
2511 unsigned long dm_login_expire;
2512 unsigned long plogi_nack_done_deadline;
2513
2514 u32 login_gen, last_login_gen;
2515 u32 rscn_gen, last_rscn_gen;
2516 u32 chip_reset;
2517 struct list_head gnl_entry;
2518 struct work_struct del_work;
2519 u8 iocb[IOCB_SIZE];
2520 u8 current_login_state;
2521 u8 last_login_state;
2522 u16 n2n_link_reset_cnt;
2523 u16 n2n_chip_reset;
2524} fc_port_t;
2525
2526enum {
2527 FC4_PRIORITY_NVME = 1,
2528 FC4_PRIORITY_FCP = 2,
2529};
2530
2531#define QLA_FCPORT_SCAN 1
2532#define QLA_FCPORT_FOUND 2
2533
2534struct event_arg {
2535 fc_port_t *fcport;
2536 srb_t *sp;
2537 port_id_t id;
2538 u16 data[2], rc;
2539 u8 port_name[WWN_SIZE];
2540 u32 iop[2];
2541};
2542
2543#include "qla_mr.h"
2544
2545
2546
2547
2548#define FCS_UNCONFIGURED 1
2549#define FCS_DEVICE_DEAD 2
2550#define FCS_DEVICE_LOST 3
2551#define FCS_ONLINE 4
2552
2553extern const char *const port_state_str[5];
2554
2555static const char * const port_dstate_str[] = {
2556 "DELETED",
2557 "GNN_ID",
2558 "GNL",
2559 "LOGIN_PEND",
2560 "LOGIN_FAILED",
2561 "GPDB",
2562 "UPD_FCPORT",
2563 "LOGIN_COMPLETE",
2564 "ADISC",
2565 "DELETE_PEND"
2566};
2567
2568
2569
2570
2571#define FCF_FABRIC_DEVICE BIT_0
2572#define FCF_LOGIN_NEEDED BIT_1
2573#define FCF_FCP2_DEVICE BIT_2
2574#define FCF_ASYNC_SENT BIT_3
2575#define FCF_CONF_COMP_SUPPORTED BIT_4
2576#define FCF_ASYNC_ACTIVE BIT_5
2577
2578
2579#define FC_NO_LOOP_ID 0x1000
2580
2581
2582
2583
2584
2585
2586
2587#define CT_REJECT_RESPONSE 0x8001
2588#define CT_ACCEPT_RESPONSE 0x8002
2589#define CT_REASON_INVALID_COMMAND_CODE 0x01
2590#define CT_REASON_CANNOT_PERFORM 0x09
2591#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2592#define CT_EXPL_ALREADY_REGISTERED 0x10
2593#define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2594#define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2595#define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2596#define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2597#define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2598#define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2599#define CT_EXPL_HBA_NOT_REGISTERED 0x17
2600#define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2601#define CT_EXPL_PORT_NOT_REGISTERED 0x21
2602#define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2603#define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2604
2605#define NS_N_PORT_TYPE 0x01
2606#define NS_NL_PORT_TYPE 0x02
2607#define NS_NX_PORT_TYPE 0x7F
2608
2609#define GA_NXT_CMD 0x100
2610#define GA_NXT_REQ_SIZE (16 + 4)
2611#define GA_NXT_RSP_SIZE (16 + 620)
2612
2613#define GPN_FT_CMD 0x172
2614#define GPN_FT_REQ_SIZE (16 + 4)
2615#define GNN_FT_CMD 0x173
2616#define GNN_FT_REQ_SIZE (16 + 4)
2617
2618#define GID_PT_CMD 0x1A1
2619#define GID_PT_REQ_SIZE (16 + 4)
2620
2621#define GPN_ID_CMD 0x112
2622#define GPN_ID_REQ_SIZE (16 + 4)
2623#define GPN_ID_RSP_SIZE (16 + 8)
2624
2625#define GNN_ID_CMD 0x113
2626#define GNN_ID_REQ_SIZE (16 + 4)
2627#define GNN_ID_RSP_SIZE (16 + 8)
2628
2629#define GFT_ID_CMD 0x117
2630#define GFT_ID_REQ_SIZE (16 + 4)
2631#define GFT_ID_RSP_SIZE (16 + 32)
2632
2633#define GID_PN_CMD 0x121
2634#define GID_PN_REQ_SIZE (16 + 8)
2635#define GID_PN_RSP_SIZE (16 + 4)
2636
2637#define RFT_ID_CMD 0x217
2638#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2639#define RFT_ID_RSP_SIZE 16
2640
2641#define RFF_ID_CMD 0x21F
2642#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2643#define RFF_ID_RSP_SIZE 16
2644
2645#define RNN_ID_CMD 0x213
2646#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2647#define RNN_ID_RSP_SIZE 16
2648
2649#define RSNN_NN_CMD 0x239
2650#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2651#define RSNN_NN_RSP_SIZE 16
2652
2653#define GFPN_ID_CMD 0x11C
2654#define GFPN_ID_REQ_SIZE (16 + 4)
2655#define GFPN_ID_RSP_SIZE (16 + 8)
2656
2657#define GPSC_CMD 0x127
2658#define GPSC_REQ_SIZE (16 + 8)
2659#define GPSC_RSP_SIZE (16 + 2 + 2)
2660
2661#define GFF_ID_CMD 0x011F
2662#define GFF_ID_REQ_SIZE (16 + 4)
2663#define GFF_ID_RSP_SIZE (16 + 128)
2664
2665
2666
2667
2668#define FDMI1_HBA_ATTR_COUNT 9
2669#define FDMI2_HBA_ATTR_COUNT 17
2670
2671#define FDMI_HBA_NODE_NAME 0x1
2672#define FDMI_HBA_MANUFACTURER 0x2
2673#define FDMI_HBA_SERIAL_NUMBER 0x3
2674#define FDMI_HBA_MODEL 0x4
2675#define FDMI_HBA_MODEL_DESCRIPTION 0x5
2676#define FDMI_HBA_HARDWARE_VERSION 0x6
2677#define FDMI_HBA_DRIVER_VERSION 0x7
2678#define FDMI_HBA_OPTION_ROM_VERSION 0x8
2679#define FDMI_HBA_FIRMWARE_VERSION 0x9
2680#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2681#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2682
2683#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2684#define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2685#define FDMI_HBA_NUM_PORTS 0xe
2686#define FDMI_HBA_FABRIC_NAME 0xf
2687#define FDMI_HBA_BOOT_BIOS_NAME 0x10
2688#define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2689
2690struct ct_fdmi_hba_attr {
2691 __be16 type;
2692 __be16 len;
2693 union {
2694 uint8_t node_name[WWN_SIZE];
2695 uint8_t manufacturer[64];
2696 uint8_t serial_num[32];
2697 uint8_t model[16+1];
2698 uint8_t model_desc[80];
2699 uint8_t hw_version[32];
2700 uint8_t driver_version[32];
2701 uint8_t orom_version[16];
2702 uint8_t fw_version[32];
2703 uint8_t os_version[128];
2704 __be32 max_ct_len;
2705
2706 uint8_t sym_name[256];
2707 __be32 vendor_specific_info;
2708 __be32 num_ports;
2709 uint8_t fabric_name[WWN_SIZE];
2710 uint8_t bios_name[32];
2711 uint8_t vendor_identifier[8];
2712 } a;
2713};
2714
2715struct ct_fdmi1_hba_attributes {
2716 __be32 count;
2717 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2718};
2719
2720struct ct_fdmi2_hba_attributes {
2721 __be32 count;
2722 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2723};
2724
2725
2726
2727
2728#define FDMI1_PORT_ATTR_COUNT 6
2729#define FDMI2_PORT_ATTR_COUNT 16
2730#define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2731
2732#define FDMI_PORT_FC4_TYPES 0x1
2733#define FDMI_PORT_SUPPORT_SPEED 0x2
2734#define FDMI_PORT_CURRENT_SPEED 0x3
2735#define FDMI_PORT_MAX_FRAME_SIZE 0x4
2736#define FDMI_PORT_OS_DEVICE_NAME 0x5
2737#define FDMI_PORT_HOST_NAME 0x6
2738
2739#define FDMI_PORT_NODE_NAME 0x7
2740#define FDMI_PORT_NAME 0x8
2741#define FDMI_PORT_SYM_NAME 0x9
2742#define FDMI_PORT_TYPE 0xa
2743#define FDMI_PORT_SUPP_COS 0xb
2744#define FDMI_PORT_FABRIC_NAME 0xc
2745#define FDMI_PORT_FC4_TYPE 0xd
2746#define FDMI_PORT_STATE 0x101
2747#define FDMI_PORT_COUNT 0x102
2748#define FDMI_PORT_IDENTIFIER 0x103
2749
2750#define FDMI_SMARTSAN_SERVICE 0xF100
2751#define FDMI_SMARTSAN_GUID 0xF101
2752#define FDMI_SMARTSAN_VERSION 0xF102
2753#define FDMI_SMARTSAN_PROD_NAME 0xF103
2754#define FDMI_SMARTSAN_PORT_INFO 0xF104
2755#define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2756#define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2757
2758#define FDMI_PORT_SPEED_1GB 0x1
2759#define FDMI_PORT_SPEED_2GB 0x2
2760#define FDMI_PORT_SPEED_10GB 0x4
2761#define FDMI_PORT_SPEED_4GB 0x8
2762#define FDMI_PORT_SPEED_8GB 0x10
2763#define FDMI_PORT_SPEED_16GB 0x20
2764#define FDMI_PORT_SPEED_32GB 0x40
2765#define FDMI_PORT_SPEED_64GB 0x80
2766#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2767
2768#define FC_CLASS_2 0x04
2769#define FC_CLASS_3 0x08
2770#define FC_CLASS_2_3 0x0C
2771
2772struct ct_fdmi_port_attr {
2773 __be16 type;
2774 __be16 len;
2775 union {
2776 uint8_t fc4_types[32];
2777 __be32 sup_speed;
2778 __be32 cur_speed;
2779 __be32 max_frame_size;
2780 uint8_t os_dev_name[32];
2781 uint8_t host_name[256];
2782
2783 uint8_t node_name[WWN_SIZE];
2784 uint8_t port_name[WWN_SIZE];
2785 uint8_t port_sym_name[128];
2786 __be32 port_type;
2787 __be32 port_supported_cos;
2788 uint8_t fabric_name[WWN_SIZE];
2789 uint8_t port_fc4_type[32];
2790 __be32 port_state;
2791 __be32 num_ports;
2792 __be32 port_id;
2793
2794 uint8_t smartsan_service[24];
2795 uint8_t smartsan_guid[16];
2796 uint8_t smartsan_version[24];
2797 uint8_t smartsan_prod_name[16];
2798 __be32 smartsan_port_info;
2799 __be32 smartsan_qos_support;
2800 __be32 smartsan_security_support;
2801 } a;
2802};
2803
2804struct ct_fdmi1_port_attributes {
2805 __be32 count;
2806 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2807};
2808
2809struct ct_fdmi2_port_attributes {
2810 __be32 count;
2811 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2812};
2813
2814#define FDMI_ATTR_TYPELEN(obj) \
2815 (sizeof((obj)->type) + sizeof((obj)->len))
2816
2817#define FDMI_ATTR_ALIGNMENT(len) \
2818 (4 - ((len) & 3))
2819
2820
2821#define CALLOPT_FDMI1 0
2822#define CALLOPT_FDMI2 1
2823#define CALLOPT_FDMI2_SMARTSAN 2
2824
2825
2826#define GRHL_CMD 0x100
2827#define GHAT_CMD 0x101
2828#define GRPL_CMD 0x102
2829#define GPAT_CMD 0x110
2830
2831#define RHBA_CMD 0x200
2832#define RHBA_RSP_SIZE 16
2833
2834#define RHAT_CMD 0x201
2835
2836#define RPRT_CMD 0x210
2837#define RPRT_RSP_SIZE 24
2838
2839#define RPA_CMD 0x211
2840#define RPA_RSP_SIZE 16
2841#define SMARTSAN_RPA_RSP_SIZE 24
2842
2843#define DHBA_CMD 0x300
2844#define DHBA_REQ_SIZE (16 + 8)
2845#define DHBA_RSP_SIZE 16
2846
2847#define DHAT_CMD 0x301
2848#define DPRT_CMD 0x310
2849#define DPA_CMD 0x311
2850
2851
2852struct ct_cmd_hdr {
2853 uint8_t revision;
2854 uint8_t in_id[3];
2855 uint8_t gs_type;
2856 uint8_t gs_subtype;
2857 uint8_t options;
2858 uint8_t reserved;
2859};
2860
2861
2862struct ct_sns_req {
2863 struct ct_cmd_hdr header;
2864 __be16 command;
2865 __be16 max_rsp_size;
2866 uint8_t fragment_id;
2867 uint8_t reserved[3];
2868
2869 union {
2870
2871 struct {
2872 uint8_t reserved;
2873 be_id_t port_id;
2874 } port_id;
2875
2876 struct {
2877 uint8_t reserved;
2878 uint8_t domain;
2879 uint8_t area;
2880 uint8_t port_type;
2881 } gpn_ft;
2882
2883 struct {
2884 uint8_t port_type;
2885 uint8_t domain;
2886 uint8_t area;
2887 uint8_t reserved;
2888 } gid_pt;
2889
2890 struct {
2891 uint8_t reserved;
2892 be_id_t port_id;
2893 uint8_t fc4_types[32];
2894 } rft_id;
2895
2896 struct {
2897 uint8_t reserved;
2898 be_id_t port_id;
2899 uint16_t reserved2;
2900 uint8_t fc4_feature;
2901 uint8_t fc4_type;
2902 } rff_id;
2903
2904 struct {
2905 uint8_t reserved;
2906 be_id_t port_id;
2907 uint8_t node_name[8];
2908 } rnn_id;
2909
2910 struct {
2911 uint8_t node_name[8];
2912 uint8_t name_len;
2913 uint8_t sym_node_name[255];
2914 } rsnn_nn;
2915
2916 struct {
2917 uint8_t hba_identifier[8];
2918 } ghat;
2919
2920 struct {
2921 uint8_t hba_identifier[8];
2922 __be32 entry_count;
2923 uint8_t port_name[8];
2924 struct ct_fdmi2_hba_attributes attrs;
2925 } rhba;
2926
2927 struct {
2928 uint8_t hba_identifier[8];
2929 struct ct_fdmi1_hba_attributes attrs;
2930 } rhat;
2931
2932 struct {
2933 uint8_t port_name[8];
2934 struct ct_fdmi2_port_attributes attrs;
2935 } rpa;
2936
2937 struct {
2938 uint8_t hba_identifier[8];
2939 uint8_t port_name[8];
2940 struct ct_fdmi2_port_attributes attrs;
2941 } rprt;
2942
2943 struct {
2944 uint8_t port_name[8];
2945 } dhba;
2946
2947 struct {
2948 uint8_t port_name[8];
2949 } dhat;
2950
2951 struct {
2952 uint8_t port_name[8];
2953 } dprt;
2954
2955 struct {
2956 uint8_t port_name[8];
2957 } dpa;
2958
2959 struct {
2960 uint8_t port_name[8];
2961 } gpsc;
2962
2963 struct {
2964 uint8_t reserved;
2965 uint8_t port_id[3];
2966 } gff_id;
2967
2968 struct {
2969 uint8_t port_name[8];
2970 } gid_pn;
2971 } req;
2972};
2973
2974
2975struct ct_rsp_hdr {
2976 struct ct_cmd_hdr header;
2977 __be16 response;
2978 uint16_t residual;
2979 uint8_t fragment_id;
2980 uint8_t reason_code;
2981 uint8_t explanation_code;
2982 uint8_t vendor_unique;
2983};
2984
2985struct ct_sns_gid_pt_data {
2986 uint8_t control_byte;
2987 be_id_t port_id;
2988};
2989
2990
2991struct ct_sns_gpnft_rsp {
2992 struct {
2993 struct ct_cmd_hdr header;
2994 uint16_t response;
2995 uint16_t residual;
2996 uint8_t fragment_id;
2997 uint8_t reason_code;
2998 uint8_t explanation_code;
2999 uint8_t vendor_unique;
3000 };
3001
3002 struct ct_sns_gpn_ft_data {
3003 u8 control_byte;
3004 u8 port_id[3];
3005 u32 reserved;
3006 u8 port_name[8];
3007 } entries[1];
3008};
3009
3010
3011struct ct_sns_rsp {
3012 struct ct_rsp_hdr header;
3013
3014 union {
3015 struct {
3016 uint8_t port_type;
3017 be_id_t port_id;
3018 uint8_t port_name[8];
3019 uint8_t sym_port_name_len;
3020 uint8_t sym_port_name[255];
3021 uint8_t node_name[8];
3022 uint8_t sym_node_name_len;
3023 uint8_t sym_node_name[255];
3024 uint8_t init_proc_assoc[8];
3025 uint8_t node_ip_addr[16];
3026 uint8_t class_of_service[4];
3027 uint8_t fc4_types[32];
3028 uint8_t ip_address[16];
3029 uint8_t fabric_port_name[8];
3030 uint8_t reserved;
3031 uint8_t hard_address[3];
3032 } ga_nxt;
3033
3034 struct {
3035
3036 struct ct_sns_gid_pt_data
3037 entries[MAX_FIBRE_DEVICES_MAX];
3038 } gid_pt;
3039
3040 struct {
3041 uint8_t port_name[8];
3042 } gpn_id;
3043
3044 struct {
3045 uint8_t node_name[8];
3046 } gnn_id;
3047
3048 struct {
3049 uint8_t fc4_types[32];
3050 } gft_id;
3051
3052 struct {
3053 uint32_t entry_count;
3054 uint8_t port_name[8];
3055 struct ct_fdmi1_hba_attributes attrs;
3056 } ghat;
3057
3058 struct {
3059 uint8_t port_name[8];
3060 } gfpn_id;
3061
3062 struct {
3063 __be16 speeds;
3064 __be16 speed;
3065 } gpsc;
3066
3067#define GFF_FCP_SCSI_OFFSET 7
3068#define GFF_NVME_OFFSET 23
3069 struct {
3070 uint8_t fc4_features[128];
3071 } gff_id;
3072 struct {
3073 uint8_t reserved;
3074 uint8_t port_id[3];
3075 } gid_pn;
3076 } rsp;
3077};
3078
3079struct ct_sns_pkt {
3080 union {
3081 struct ct_sns_req req;
3082 struct ct_sns_rsp rsp;
3083 } p;
3084};
3085
3086struct ct_sns_gpnft_pkt {
3087 union {
3088 struct ct_sns_req req;
3089 struct ct_sns_gpnft_rsp rsp;
3090 } p;
3091};
3092
3093enum scan_flags_t {
3094 SF_SCANNING = BIT_0,
3095 SF_QUEUED = BIT_1,
3096};
3097
3098enum fc4type_t {
3099 FS_FC4TYPE_FCP = BIT_0,
3100 FS_FC4TYPE_NVME = BIT_1,
3101 FS_FCP_IS_N2N = BIT_7,
3102};
3103
3104struct fab_scan_rp {
3105 port_id_t id;
3106 enum fc4type_t fc4type;
3107 u8 port_name[8];
3108 u8 node_name[8];
3109};
3110
3111struct fab_scan {
3112 struct fab_scan_rp *l;
3113 u32 size;
3114 u16 scan_retry;
3115#define MAX_SCAN_RETRIES 5
3116 enum scan_flags_t scan_flags;
3117 struct delayed_work scan_work;
3118};
3119
3120
3121
3122
3123#define RFT_ID_SNS_SCMD_LEN 22
3124#define RFT_ID_SNS_CMD_SIZE 60
3125#define RFT_ID_SNS_DATA_SIZE 16
3126
3127#define RNN_ID_SNS_SCMD_LEN 10
3128#define RNN_ID_SNS_CMD_SIZE 36
3129#define RNN_ID_SNS_DATA_SIZE 16
3130
3131#define GA_NXT_SNS_SCMD_LEN 6
3132#define GA_NXT_SNS_CMD_SIZE 28
3133#define GA_NXT_SNS_DATA_SIZE (620 + 16)
3134
3135#define GID_PT_SNS_SCMD_LEN 6
3136#define GID_PT_SNS_CMD_SIZE 28
3137
3138
3139
3140
3141#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3142
3143#define GPN_ID_SNS_SCMD_LEN 6
3144#define GPN_ID_SNS_CMD_SIZE 28
3145#define GPN_ID_SNS_DATA_SIZE (8 + 16)
3146
3147#define GNN_ID_SNS_SCMD_LEN 6
3148#define GNN_ID_SNS_CMD_SIZE 28
3149#define GNN_ID_SNS_DATA_SIZE (8 + 16)
3150
3151struct sns_cmd_pkt {
3152 union {
3153 struct {
3154 __le16 buffer_length;
3155 __le16 reserved_1;
3156 __le64 buffer_address __packed;
3157 __le16 subcommand_length;
3158 __le16 reserved_2;
3159 __le16 subcommand;
3160 __le16 size;
3161 uint32_t reserved_3;
3162 uint8_t param[36];
3163 } cmd;
3164
3165 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3166 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3167 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3168 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3169 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3170 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3171 } p;
3172};
3173
3174struct fw_blob {
3175 char *name;
3176 uint32_t segs[4];
3177 const struct firmware *fw;
3178};
3179
3180
3181struct gid_list_info {
3182 uint8_t al_pa;
3183 uint8_t area;
3184 uint8_t domain;
3185 uint8_t loop_id_2100;
3186 __le16 loop_id;
3187 uint16_t reserved_1;
3188};
3189
3190
3191typedef struct vport_info {
3192 uint8_t port_name[WWN_SIZE];
3193 uint8_t node_name[WWN_SIZE];
3194 int vp_id;
3195 uint16_t loop_id;
3196 unsigned long host_no;
3197 uint8_t port_id[3];
3198 int loop_state;
3199} vport_info_t;
3200
3201typedef struct vport_params {
3202 uint8_t port_name[WWN_SIZE];
3203 uint8_t node_name[WWN_SIZE];
3204 uint32_t options;
3205#define VP_OPTS_RETRY_ENABLE BIT_0
3206#define VP_OPTS_VP_DISABLE BIT_1
3207} vport_params_t;
3208
3209
3210#define VP_RET_CODE_OK 0
3211#define VP_RET_CODE_FATAL 1
3212#define VP_RET_CODE_WRONG_ID 2
3213#define VP_RET_CODE_WWPN 3
3214#define VP_RET_CODE_RESOURCES 4
3215#define VP_RET_CODE_NO_MEM 5
3216#define VP_RET_CODE_NOT_FOUND 6
3217
3218struct qla_hw_data;
3219struct rsp_que;
3220
3221
3222
3223struct isp_operations {
3224
3225 int (*pci_config) (struct scsi_qla_host *);
3226 int (*reset_chip)(struct scsi_qla_host *);
3227 int (*chip_diag) (struct scsi_qla_host *);
3228 void (*config_rings) (struct scsi_qla_host *);
3229 int (*reset_adapter)(struct scsi_qla_host *);
3230 int (*nvram_config) (struct scsi_qla_host *);
3231 void (*update_fw_options) (struct scsi_qla_host *);
3232 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3233
3234 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3235 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3236
3237 irq_handler_t intr_handler;
3238 void (*enable_intrs) (struct qla_hw_data *);
3239 void (*disable_intrs) (struct qla_hw_data *);
3240
3241 int (*abort_command) (srb_t *);
3242 int (*target_reset) (struct fc_port *, uint64_t, int);
3243 int (*lun_reset) (struct fc_port *, uint64_t, int);
3244 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3245 uint8_t, uint8_t, uint16_t *, uint8_t);
3246 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3247 uint8_t, uint8_t);
3248
3249 uint16_t (*calc_req_entries) (uint16_t);
3250 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3251 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3252 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3253 uint32_t);
3254
3255 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3256 uint32_t, uint32_t);
3257 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3258 uint32_t);
3259
3260 void (*fw_dump)(struct scsi_qla_host *vha);
3261 void (*mpi_fw_dump)(struct scsi_qla_host *, int);
3262
3263 int (*beacon_on) (struct scsi_qla_host *);
3264 int (*beacon_off) (struct scsi_qla_host *);
3265 void (*beacon_blink) (struct scsi_qla_host *);
3266
3267 void *(*read_optrom)(struct scsi_qla_host *, void *,
3268 uint32_t, uint32_t);
3269 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3270 uint32_t);
3271
3272 int (*get_flash_version) (struct scsi_qla_host *, void *);
3273 int (*start_scsi) (srb_t *);
3274 int (*start_scsi_mq) (srb_t *);
3275 int (*abort_isp) (struct scsi_qla_host *);
3276 int (*iospace_config)(struct qla_hw_data *);
3277 int (*initialize_adapter)(struct scsi_qla_host *);
3278};
3279
3280
3281
3282#define QLA_MSIX_CHIP_REV_24XX 3
3283#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3284#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3285
3286#define QLA_BASE_VECTORS 2
3287#define QLA_MSIX_RSP_Q 0x01
3288#define QLA_ATIO_VECTOR 0x02
3289#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3290#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3291
3292#define QLA_MIDX_DEFAULT 0
3293#define QLA_MIDX_RSP_Q 1
3294#define QLA_PCI_MSIX_CONTROL 0xa2
3295#define QLA_83XX_PCI_MSIX_CONTROL 0x92
3296
3297struct scsi_qla_host;
3298
3299
3300#define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1
3301
3302struct qla_msix_entry {
3303 int have_irq;
3304 int in_use;
3305 uint32_t vector;
3306 uint16_t entry;
3307 char name[30];
3308 void *handle;
3309 int cpuid;
3310};
3311
3312#define WATCH_INTERVAL 1
3313
3314
3315enum qla_work_type {
3316 QLA_EVT_AEN,
3317 QLA_EVT_IDC_ACK,
3318 QLA_EVT_ASYNC_LOGIN,
3319 QLA_EVT_ASYNC_LOGOUT,
3320 QLA_EVT_ASYNC_ADISC,
3321 QLA_EVT_UEVENT,
3322 QLA_EVT_AENFX,
3323 QLA_EVT_GPNID,
3324 QLA_EVT_UNMAP,
3325 QLA_EVT_NEW_SESS,
3326 QLA_EVT_GPDB,
3327 QLA_EVT_PRLI,
3328 QLA_EVT_GPSC,
3329 QLA_EVT_GNL,
3330 QLA_EVT_NACK,
3331 QLA_EVT_RELOGIN,
3332 QLA_EVT_ASYNC_PRLO,
3333 QLA_EVT_ASYNC_PRLO_DONE,
3334 QLA_EVT_GPNFT,
3335 QLA_EVT_GPNFT_DONE,
3336 QLA_EVT_GNNFT_DONE,
3337 QLA_EVT_GNNID,
3338 QLA_EVT_GFPNID,
3339 QLA_EVT_SP_RETRY,
3340 QLA_EVT_IIDMA,
3341 QLA_EVT_ELS_PLOGI,
3342};
3343
3344
3345struct qla_work_evt {
3346 struct list_head list;
3347 enum qla_work_type type;
3348 u32 flags;
3349#define QLA_EVT_FLAG_FREE 0x1
3350
3351 union {
3352 struct {
3353 enum fc_host_event_code code;
3354 u32 data;
3355 } aen;
3356 struct {
3357#define QLA_IDC_ACK_REGS 7
3358 uint16_t mb[QLA_IDC_ACK_REGS];
3359 } idc_ack;
3360 struct {
3361 struct fc_port *fcport;
3362#define QLA_LOGIO_LOGIN_RETRIED BIT_0
3363 u16 data[2];
3364 } logio;
3365 struct {
3366 u32 code;
3367#define QLA_UEVENT_CODE_FW_DUMP 0
3368 } uevent;
3369 struct {
3370 uint32_t evtcode;
3371 uint32_t mbx[8];
3372 uint32_t count;
3373 } aenfx;
3374 struct {
3375 srb_t *sp;
3376 } iosb;
3377 struct {
3378 port_id_t id;
3379 } gpnid;
3380 struct {
3381 port_id_t id;
3382 u8 port_name[8];
3383 u8 node_name[8];
3384 void *pla;
3385 u8 fc4_type;
3386 } new_sess;
3387 struct {
3388 fc_port_t *fcport;
3389 u8 opt;
3390 } fcport;
3391 struct {
3392 fc_port_t *fcport;
3393 u8 iocb[IOCB_SIZE];
3394 int type;
3395 } nack;
3396 struct {
3397 u8 fc4_type;
3398 srb_t *sp;
3399 } gpnft;
3400 } u;
3401};
3402
3403struct qla_chip_state_84xx {
3404 struct list_head list;
3405 struct kref kref;
3406
3407 void *bus;
3408 spinlock_t access_lock;
3409 struct mutex fw_update_mutex;
3410 uint32_t fw_update;
3411 uint32_t op_fw_version;
3412 uint32_t op_fw_size;
3413 uint32_t op_fw_seq_size;
3414 uint32_t diag_fw_version;
3415 uint32_t gold_fw_version;
3416};
3417
3418struct qla_dif_statistics {
3419 uint64_t dif_input_bytes;
3420 uint64_t dif_output_bytes;
3421 uint64_t dif_input_requests;
3422 uint64_t dif_output_requests;
3423 uint32_t dif_guard_err;
3424 uint32_t dif_ref_tag_err;
3425 uint32_t dif_app_tag_err;
3426};
3427
3428struct qla_statistics {
3429 uint32_t total_isp_aborts;
3430 uint64_t input_bytes;
3431 uint64_t output_bytes;
3432 uint64_t input_requests;
3433 uint64_t output_requests;
3434 uint32_t control_requests;
3435
3436 uint64_t jiffies_at_last_reset;
3437 uint32_t stat_max_pend_cmds;
3438 uint32_t stat_max_qfull_cmds_alloc;
3439 uint32_t stat_max_qfull_cmds_dropped;
3440
3441 struct qla_dif_statistics qla_dif_stats;
3442};
3443
3444struct bidi_statistics {
3445 unsigned long long io_count;
3446 unsigned long long transfer_bytes;
3447};
3448
3449struct qla_tc_param {
3450 struct scsi_qla_host *vha;
3451 uint32_t blk_sz;
3452 uint32_t bufflen;
3453 struct scatterlist *sg;
3454 struct scatterlist *prot_sg;
3455 struct crc_context *ctx;
3456 uint8_t *ctx_dsd_alloced;
3457};
3458
3459
3460#define MBC_INITIALIZE_MULTIQ 0x1f
3461#define QLA_QUE_PAGE 0X1000
3462#define QLA_MQ_SIZE 32
3463#define QLA_MAX_QUEUES 256
3464#define ISP_QUE_REG(ha, id) \
3465 ((ha->mqenable || IS_QLA83XX(ha) || \
3466 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3467 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3468 ((void __iomem *)ha->iobase))
3469#define QLA_REQ_QUE_ID(tag) \
3470 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3471#define QLA_DEFAULT_QUE_QOS 5
3472#define QLA_PRECONFIG_VPORTS 32
3473#define QLA_MAX_VPORTS_QLA24XX 128
3474#define QLA_MAX_VPORTS_QLA25XX 256
3475
3476struct qla_tgt_counters {
3477 uint64_t qla_core_sbt_cmd;
3478 uint64_t core_qla_que_buf;
3479 uint64_t qla_core_ret_ctio;
3480 uint64_t core_qla_snd_status;
3481 uint64_t qla_core_ret_sta_ctio;
3482 uint64_t core_qla_free_cmd;
3483 uint64_t num_q_full_sent;
3484 uint64_t num_alloc_iocb_failed;
3485 uint64_t num_term_xchg_sent;
3486};
3487
3488struct qla_qpair;
3489
3490
3491struct rsp_que {
3492 dma_addr_t dma;
3493 response_t *ring;
3494 response_t *ring_ptr;
3495 __le32 __iomem *rsp_q_in;
3496 __le32 __iomem *rsp_q_out;
3497 uint16_t ring_index;
3498 uint16_t out_ptr;
3499 uint16_t *in_ptr;
3500 uint16_t length;
3501 uint16_t options;
3502 uint16_t rid;
3503 uint16_t id;
3504 uint16_t vp_idx;
3505 struct qla_hw_data *hw;
3506 struct qla_msix_entry *msix;
3507 struct req_que *req;
3508 srb_t *status_srb;
3509 struct qla_qpair *qpair;
3510
3511 dma_addr_t dma_fx00;
3512 response_t *ring_fx00;
3513 uint16_t length_fx00;
3514 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3515};
3516
3517
3518struct req_que {
3519 dma_addr_t dma;
3520 request_t *ring;
3521 request_t *ring_ptr;
3522 __le32 __iomem *req_q_in;
3523 __le32 __iomem *req_q_out;
3524 uint16_t ring_index;
3525 uint16_t in_ptr;
3526 uint16_t *out_ptr;
3527 uint16_t cnt;
3528 uint16_t length;
3529 uint16_t options;
3530 uint16_t rid;
3531 uint16_t id;
3532 uint16_t qos;
3533 uint16_t vp_idx;
3534 struct rsp_que *rsp;
3535 srb_t **outstanding_cmds;
3536 uint32_t current_outstanding_cmd;
3537 uint16_t num_outstanding_cmds;
3538 int max_q_depth;
3539
3540 dma_addr_t dma_fx00;
3541 request_t *ring_fx00;
3542 uint16_t length_fx00;
3543 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3544};
3545
3546
3547struct qla_qpair {
3548 spinlock_t qp_lock;
3549 atomic_t ref_count;
3550 uint32_t lun_cnt;
3551
3552
3553
3554
3555 spinlock_t *qp_lock_ptr;
3556 struct scsi_qla_host *vha;
3557 u32 chip_reset;
3558
3559
3560
3561
3562
3563
3564 uint32_t online:1;
3565
3566 uint32_t difdix_supported:1;
3567 uint32_t delete_in_progress:1;
3568 uint32_t fw_started:1;
3569 uint32_t enable_class_2:1;
3570 uint32_t enable_explicit_conf:1;
3571 uint32_t use_shadow_reg:1;
3572
3573 uint16_t id;
3574 uint16_t vp_idx;
3575 mempool_t *srb_mempool;
3576
3577 struct pci_dev *pdev;
3578 void (*reqq_start_iocbs)(struct qla_qpair *);
3579
3580
3581 struct req_que *req;
3582 struct rsp_que *rsp;
3583 struct atio_que *atio;
3584 struct qla_msix_entry *msix;
3585 struct qla_hw_data *hw;
3586 struct work_struct q_work;
3587 struct list_head qp_list_elem;
3588 struct list_head hints_list;
3589 uint16_t cpuid;
3590 uint16_t retry_term_cnt;
3591 __le32 retry_term_exchg_addr;
3592 uint64_t retry_term_jiff;
3593 struct qla_tgt_counters tgt_counters;
3594};
3595
3596
3597struct qlfc_fw {
3598 void *fw_buf;
3599 dma_addr_t fw_dma;
3600 uint32_t len;
3601};
3602
3603struct rdp_req_payload {
3604 uint32_t els_request;
3605 uint32_t desc_list_len;
3606
3607
3608 struct {
3609 uint32_t desc_tag;
3610 uint32_t desc_len;
3611 uint8_t reserved;
3612 uint8_t nport_id[3];
3613 } npiv_desc;
3614};
3615
3616struct rdp_rsp_payload {
3617 struct {
3618 __be32 cmd;
3619 __be32 len;
3620 } hdr;
3621
3622
3623 struct {
3624 __be32 desc_tag;
3625 __be32 desc_len;
3626 __be32 req_payload_word_0;
3627 } ls_req_info_desc;
3628
3629
3630 struct {
3631 __be32 desc_tag;
3632 __be32 desc_len;
3633 __be32 req_payload_word_0;
3634 } ls_req_info_desc2;
3635
3636
3637 struct {
3638 __be32 desc_tag;
3639 __be32 desc_len;
3640 __be16 temperature;
3641 __be16 vcc;
3642 __be16 tx_bias;
3643 __be16 tx_power;
3644 __be16 rx_power;
3645 __be16 sfp_flags;
3646 } sfp_diag_desc;
3647
3648
3649 struct {
3650 __be32 desc_tag;
3651 __be32 desc_len;
3652 __be16 speed_capab;
3653 __be16 operating_speed;
3654 } port_speed_desc;
3655
3656
3657 struct {
3658 __be32 desc_tag;
3659 __be32 desc_len;
3660 __be32 link_fail_cnt;
3661 __be32 loss_sync_cnt;
3662 __be32 loss_sig_cnt;
3663 __be32 prim_seq_err_cnt;
3664 __be32 inval_xmit_word_cnt;
3665 __be32 inval_crc_cnt;
3666 uint8_t pn_port_phy_type;
3667 uint8_t reserved[3];
3668 } ls_err_desc;
3669
3670
3671 struct {
3672 __be32 desc_tag;
3673 __be32 desc_len;
3674 uint8_t WWNN[WWN_SIZE];
3675 uint8_t WWPN[WWN_SIZE];
3676 } port_name_diag_desc;
3677
3678
3679 struct {
3680 __be32 desc_tag;
3681 __be32 desc_len;
3682 uint8_t WWNN[WWN_SIZE];
3683 uint8_t WWPN[WWN_SIZE];
3684 } port_name_direct_desc;
3685
3686
3687 struct {
3688 __be32 desc_tag;
3689 __be32 desc_len;
3690 __be32 fcport_b2b;
3691 __be32 attached_fcport_b2b;
3692 __be32 fcport_rtt;
3693 } buffer_credit_desc;
3694
3695
3696 struct {
3697 __be32 desc_tag;
3698 __be32 desc_len;
3699 __be16 high_alarm;
3700 __be16 low_alarm;
3701 __be16 high_warn;
3702 __be16 low_warn;
3703 __be32 element_flags;
3704 } optical_elmt_desc[5];
3705
3706
3707 struct {
3708 __be32 desc_tag;
3709 __be32 desc_len;
3710 uint8_t vendor_name[16];
3711 uint8_t part_number[16];
3712 uint8_t serial_number[16];
3713 uint8_t revision[4];
3714 uint8_t date[8];
3715 } optical_prod_desc;
3716};
3717
3718#define RDP_DESC_LEN(obj) \
3719 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3720
3721#define RDP_PORT_SPEED_1GB BIT_15
3722#define RDP_PORT_SPEED_2GB BIT_14
3723#define RDP_PORT_SPEED_4GB BIT_13
3724#define RDP_PORT_SPEED_10GB BIT_12
3725#define RDP_PORT_SPEED_8GB BIT_11
3726#define RDP_PORT_SPEED_16GB BIT_10
3727#define RDP_PORT_SPEED_32GB BIT_9
3728#define RDP_PORT_SPEED_64GB BIT_8
3729#define RDP_PORT_SPEED_UNKNOWN BIT_0
3730
3731struct scsi_qlt_host {
3732 void *target_lport_ptr;
3733 struct mutex tgt_mutex;
3734 struct mutex tgt_host_action_mutex;
3735 struct qla_tgt *qla_tgt;
3736};
3737
3738struct qlt_hw_data {
3739
3740 uint32_t node_name_set:1;
3741
3742 dma_addr_t atio_dma;
3743 struct atio *atio_ring;
3744 struct atio *atio_ring_ptr;
3745 uint16_t atio_ring_index;
3746 uint16_t atio_q_length;
3747 __le32 __iomem *atio_q_in;
3748 __le32 __iomem *atio_q_out;
3749
3750 struct qla_tgt_func_tmpl *tgt_ops;
3751 struct qla_tgt_vp_map *tgt_vp_map;
3752
3753 int saved_set;
3754 __le16 saved_exchange_count;
3755 __le32 saved_firmware_options_1;
3756 __le32 saved_firmware_options_2;
3757 __le32 saved_firmware_options_3;
3758 uint8_t saved_firmware_options[2];
3759 uint8_t saved_add_firmware_options[2];
3760
3761 uint8_t tgt_node_name[WWN_SIZE];
3762
3763 struct dentry *dfs_tgt_sess;
3764 struct dentry *dfs_tgt_port_database;
3765 struct dentry *dfs_naqp;
3766
3767 struct list_head q_full_list;
3768 uint32_t num_pend_cmds;
3769 uint32_t num_qfull_cmds_alloc;
3770 uint32_t num_qfull_cmds_dropped;
3771 spinlock_t q_full_lock;
3772 uint32_t leak_exchg_thresh_hold;
3773 spinlock_t sess_lock;
3774 int num_act_qpairs;
3775#define DEFAULT_NAQP 2
3776 spinlock_t atio_lock ____cacheline_aligned;
3777 struct btree_head32 host_map;
3778};
3779
3780#define MAX_QFULL_CMDS_ALLOC 8192
3781#define Q_FULL_THRESH_HOLD_PERCENT 90
3782#define Q_FULL_THRESH_HOLD(ha) \
3783 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3784
3785#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75
3786
3787struct qla_hw_data_stat {
3788 u32 num_fw_dump;
3789 u32 num_mpi_reset;
3790};
3791
3792
3793
3794
3795struct qla_hw_data {
3796 struct pci_dev *pdev;
3797
3798#define SRB_MIN_REQ 128
3799 mempool_t *srb_mempool;
3800
3801 volatile struct {
3802 uint32_t mbox_int :1;
3803 uint32_t mbox_busy :1;
3804 uint32_t disable_risc_code_load :1;
3805 uint32_t enable_64bit_addressing :1;
3806 uint32_t enable_lip_reset :1;
3807 uint32_t enable_target_reset :1;
3808 uint32_t enable_lip_full_login :1;
3809 uint32_t enable_led_scheme :1;
3810
3811 uint32_t msi_enabled :1;
3812 uint32_t msix_enabled :1;
3813 uint32_t disable_serdes :1;
3814 uint32_t gpsc_supported :1;
3815 uint32_t npiv_supported :1;
3816 uint32_t pci_channel_io_perm_failure :1;
3817 uint32_t fce_enabled :1;
3818 uint32_t fac_supported :1;
3819
3820 uint32_t chip_reset_done :1;
3821 uint32_t running_gold_fw :1;
3822 uint32_t eeh_busy :1;
3823 uint32_t disable_msix_handshake :1;
3824 uint32_t fcp_prio_enabled :1;
3825 uint32_t isp82xx_fw_hung:1;
3826 uint32_t nic_core_hung:1;
3827
3828 uint32_t quiesce_owner:1;
3829 uint32_t nic_core_reset_hdlr_active:1;
3830 uint32_t nic_core_reset_owner:1;
3831 uint32_t isp82xx_no_md_cap:1;
3832 uint32_t host_shutting_down:1;
3833 uint32_t idc_compl_status:1;
3834 uint32_t mr_reset_hdlr_active:1;
3835 uint32_t mr_intr_valid:1;
3836
3837 uint32_t dport_enabled:1;
3838 uint32_t fawwpn_enabled:1;
3839 uint32_t exlogins_enabled:1;
3840 uint32_t exchoffld_enabled:1;
3841
3842 uint32_t lip_ae:1;
3843 uint32_t n2n_ae:1;
3844 uint32_t fw_started:1;
3845 uint32_t fw_init_done:1;
3846
3847 uint32_t lr_detected:1;
3848
3849 uint32_t rida_fmt2:1;
3850 uint32_t purge_mbox:1;
3851 uint32_t n2n_bigger:1;
3852 uint32_t secure_adapter:1;
3853 uint32_t secure_fw:1;
3854 } flags;
3855
3856 uint16_t max_exchg;
3857 uint16_t lr_distance;
3858#define LR_DISTANCE_5K 1
3859#define LR_DISTANCE_10K 0
3860
3861
3862
3863
3864
3865
3866
3867
3868 spinlock_t hardware_lock ____cacheline_aligned;
3869 int bars;
3870 int mem_only;
3871 device_reg_t *iobase;
3872 resource_size_t pio_address;
3873
3874#define MIN_IOBASE_LEN 0x100
3875 dma_addr_t bar0_hdl;
3876
3877 void __iomem *cregbase;
3878 dma_addr_t bar2_hdl;
3879#define BAR0_LEN_FX00 (1024 * 1024)
3880#define BAR2_LEN_FX00 (128 * 1024)
3881
3882 uint32_t rqstq_intr_code;
3883 uint32_t mbx_intr_code;
3884 uint32_t req_que_len;
3885 uint32_t rsp_que_len;
3886 uint32_t req_que_off;
3887 uint32_t rsp_que_off;
3888
3889
3890 device_reg_t *mqiobase;
3891 device_reg_t *msixbase;
3892 uint16_t msix_count;
3893 uint8_t mqenable;
3894 struct req_que **req_q_map;
3895 struct rsp_que **rsp_q_map;
3896 struct qla_qpair **queue_pair_map;
3897 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3898 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3899 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3900 / sizeof(unsigned long)];
3901 uint8_t max_req_queues;
3902 uint8_t max_rsp_queues;
3903 uint8_t max_qpairs;
3904 uint8_t num_qpairs;
3905 struct qla_qpair *base_qpair;
3906 struct qla_npiv_entry *npiv_info;
3907 uint16_t nvram_npiv_size;
3908
3909 uint16_t switch_cap;
3910#define FLOGI_SEQ_DEL BIT_8
3911#define FLOGI_MID_SUPPORT BIT_10
3912#define FLOGI_VSAN_SUPPORT BIT_12
3913#define FLOGI_SP_SUPPORT BIT_13
3914
3915 uint8_t port_no;
3916 uint8_t exch_starvation;
3917
3918
3919 uint8_t loop_down_abort_time;
3920 atomic_t loop_down_timer;
3921 uint8_t link_down_timeout;
3922 uint16_t max_loop_id;
3923 uint16_t max_fibre_devices;
3924
3925 uint16_t fb_rev;
3926 uint16_t min_external_loopid;
3927
3928#define PORT_SPEED_UNKNOWN 0xFFFF
3929#define PORT_SPEED_1GB 0x00
3930#define PORT_SPEED_2GB 0x01
3931#define PORT_SPEED_AUTO 0x02
3932#define PORT_SPEED_4GB 0x03
3933#define PORT_SPEED_8GB 0x04
3934#define PORT_SPEED_16GB 0x05
3935#define PORT_SPEED_32GB 0x06
3936#define PORT_SPEED_64GB 0x07
3937#define PORT_SPEED_10GB 0x13
3938 uint16_t link_data_rate;
3939 uint16_t set_data_rate;
3940
3941 uint8_t current_topology;
3942 uint8_t prev_topology;
3943#define ISP_CFG_NL 1
3944#define ISP_CFG_N 2
3945#define ISP_CFG_FL 4
3946#define ISP_CFG_F 8
3947
3948 uint8_t operating_mode;
3949#define LOOP 0
3950#define P2P 1
3951#define LOOP_P2P 2
3952#define P2P_LOOP 3
3953 uint8_t interrupts_on;
3954 uint32_t isp_abort_cnt;
3955#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3956#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3957#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3958#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3959#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3960#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3961#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3962#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3963#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
3964#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
3965#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
3966#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
3967#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
3968
3969 uint32_t isp_type;
3970#define DT_ISP2100 BIT_0
3971#define DT_ISP2200 BIT_1
3972#define DT_ISP2300 BIT_2
3973#define DT_ISP2312 BIT_3
3974#define DT_ISP2322 BIT_4
3975#define DT_ISP6312 BIT_5
3976#define DT_ISP6322 BIT_6
3977#define DT_ISP2422 BIT_7
3978#define DT_ISP2432 BIT_8
3979#define DT_ISP5422 BIT_9
3980#define DT_ISP5432 BIT_10
3981#define DT_ISP2532 BIT_11
3982#define DT_ISP8432 BIT_12
3983#define DT_ISP8001 BIT_13
3984#define DT_ISP8021 BIT_14
3985#define DT_ISP2031 BIT_15
3986#define DT_ISP8031 BIT_16
3987#define DT_ISPFX00 BIT_17
3988#define DT_ISP8044 BIT_18
3989#define DT_ISP2071 BIT_19
3990#define DT_ISP2271 BIT_20
3991#define DT_ISP2261 BIT_21
3992#define DT_ISP2061 BIT_22
3993#define DT_ISP2081 BIT_23
3994#define DT_ISP2089 BIT_24
3995#define DT_ISP2281 BIT_25
3996#define DT_ISP2289 BIT_26
3997#define DT_ISP_LAST (DT_ISP2289 << 1)
3998
3999 uint32_t device_type;
4000#define DT_T10_PI BIT_25
4001#define DT_IIDMA BIT_26
4002#define DT_FWI2 BIT_27
4003#define DT_ZIO_SUPPORTED BIT_28
4004#define DT_OEM_001 BIT_29
4005#define DT_ISP2200A BIT_30
4006#define DT_EXTENDED_IDS BIT_31
4007
4008#define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
4009#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
4010#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
4011#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
4012#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
4013#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
4014#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
4015#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
4016#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
4017#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
4018#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
4019#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
4020#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4021#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
4022#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
4023#define IS_QLA81XX(ha) (IS_QLA8001(ha))
4024#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
4025#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
4026#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
4027#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
4028#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
4029#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
4030#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
4031#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
4032#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
4033#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
4034
4035#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
4036 IS_QLA6312(ha) || IS_QLA6322(ha))
4037#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
4038#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
4039#define IS_QLA25XX(ha) (IS_QLA2532(ha))
4040#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
4041#define IS_QLA84XX(ha) (IS_QLA8432(ha))
4042#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
4043#define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
4044#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4045 IS_QLA84XX(ha))
4046#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
4047 IS_QLA8031(ha) || IS_QLA8044(ha))
4048#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
4049#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
4050 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
4051 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
4052 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4053 IS_QLA28XX(ha))
4054#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4055 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4056#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4057#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4058 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4059#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4060 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4061#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
4062
4063#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
4064#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4065#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4066#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4067#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4068#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
4069#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
4070#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
4071 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4072#define IS_BIDI_CAPABLE(ha) \
4073 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4074
4075#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4076 ((ha)->fw_attributes_ext[0] & BIT_0))
4077#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4078#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4079#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
4080#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4081 IS_QLA28XX(ha))
4082#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4083 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4084#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4085 IS_QLA28XX(ha))
4086#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
4087#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4088#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4089 IS_QLA28XX(ha))
4090#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4091 IS_QLA28XX(ha))
4092#define IS_EXCHG_OFFLD_CAPABLE(ha) \
4093 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4094#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
4095 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4096 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4097#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
4098 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4099
4100
4101 uint8_t serial0;
4102 uint8_t serial1;
4103 uint8_t serial2;
4104
4105
4106#define MAX_NVRAM_SIZE 4096
4107#define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
4108 uint16_t nvram_size;
4109 uint16_t nvram_base;
4110 void *nvram;
4111 uint16_t vpd_size;
4112 uint16_t vpd_base;
4113 void *vpd;
4114
4115 uint16_t loop_reset_delay;
4116 uint8_t retry_count;
4117 uint8_t login_timeout;
4118 uint16_t r_a_tov;
4119 int port_down_retry_count;
4120 uint8_t mbx_count;
4121 uint8_t aen_mbx_count;
4122 atomic_t num_pend_mbx_stage1;
4123 atomic_t num_pend_mbx_stage2;
4124 atomic_t num_pend_mbx_stage3;
4125 uint16_t frame_payload_size;
4126
4127 uint32_t login_retry_count;
4128
4129 ms_iocb_entry_t *ms_iocb;
4130 dma_addr_t ms_iocb_dma;
4131 struct ct_sns_pkt *ct_sns;
4132 dma_addr_t ct_sns_dma;
4133
4134 struct sns_cmd_pkt *sns_cmd;
4135 dma_addr_t sns_cmd_dma;
4136
4137#define SFP_DEV_SIZE 512
4138#define SFP_BLOCK_SIZE 64
4139#define SFP_RTDI_LEN SFP_BLOCK_SIZE
4140
4141 void *sfp_data;
4142 dma_addr_t sfp_data_dma;
4143
4144 struct qla_flt_header *flt;
4145 dma_addr_t flt_dma;
4146
4147#define XGMAC_DATA_SIZE 4096
4148 void *xgmac_data;
4149 dma_addr_t xgmac_data_dma;
4150
4151#define DCBX_TLV_DATA_SIZE 4096
4152 void *dcbx_tlv;
4153 dma_addr_t dcbx_tlv_dma;
4154
4155 struct task_struct *dpc_thread;
4156 uint8_t dpc_active;
4157
4158 dma_addr_t gid_list_dma;
4159 struct gid_list_info *gid_list;
4160 int gid_list_info_size;
4161
4162
4163#define DMA_POOL_SIZE 256
4164 struct dma_pool *s_dma_pool;
4165
4166 dma_addr_t init_cb_dma;
4167 init_cb_t *init_cb;
4168 int init_cb_size;
4169 dma_addr_t ex_init_cb_dma;
4170 struct ex_init_cb_81xx *ex_init_cb;
4171
4172 void *async_pd;
4173 dma_addr_t async_pd_dma;
4174
4175#define ENABLE_EXTENDED_LOGIN BIT_7
4176
4177
4178 void *exlogin_buf;
4179 dma_addr_t exlogin_buf_dma;
4180 int exlogin_size;
4181
4182#define ENABLE_EXCHANGE_OFFLD BIT_2
4183
4184
4185 void *exchoffld_buf;
4186 dma_addr_t exchoffld_buf_dma;
4187 int exchoffld_size;
4188 int exchoffld_count;
4189
4190
4191 struct els_plogi_payload plogi_els_payld;
4192
4193 void *swl;
4194
4195
4196 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4197 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4198 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4199
4200 mbx_cmd_t *mcp;
4201 struct mbx_cmd_32 *mcp32;
4202
4203 unsigned long mbx_cmd_flags;
4204#define MBX_INTERRUPT 1
4205#define MBX_INTR_WAIT 2
4206#define MBX_UPDATE_FLASH_ACTIVE 3
4207
4208 struct mutex vport_lock;
4209 spinlock_t vport_slock;
4210 struct mutex mq_lock;
4211 struct completion mbx_cmd_comp;
4212 struct completion mbx_intr_comp;
4213 struct completion dcbx_comp;
4214 struct completion lb_portup_comp;
4215
4216#define DCBX_COMP_TIMEOUT 20
4217#define LB_PORTUP_COMP_TIMEOUT 10
4218
4219 int notify_dcbx_comp;
4220 int notify_lb_portup_comp;
4221 struct mutex selflogin_lock;
4222
4223
4224 uint16_t fw_major_version;
4225 uint16_t fw_minor_version;
4226 uint16_t fw_subminor_version;
4227 uint16_t fw_attributes;
4228 uint16_t fw_attributes_h;
4229#define FW_ATTR_H_NVME_FBURST BIT_1
4230#define FW_ATTR_H_NVME BIT_10
4231#define FW_ATTR_H_NVME_UPDATED BIT_14
4232
4233 uint16_t fw_attributes_ext[2];
4234 uint32_t fw_memory_size;
4235 uint32_t fw_transfer_size;
4236 uint32_t fw_srisc_address;
4237#define RISC_START_ADDRESS_2100 0x1000
4238#define RISC_START_ADDRESS_2300 0x800
4239#define RISC_START_ADDRESS_2400 0x100000
4240
4241 uint16_t orig_fw_tgt_xcb_count;
4242 uint16_t cur_fw_tgt_xcb_count;
4243 uint16_t orig_fw_xcb_count;
4244 uint16_t cur_fw_xcb_count;
4245 uint16_t orig_fw_iocb_count;
4246 uint16_t cur_fw_iocb_count;
4247 uint16_t fw_max_fcf_count;
4248
4249 uint32_t fw_shared_ram_start;
4250 uint32_t fw_shared_ram_end;
4251 uint32_t fw_ddr_ram_start;
4252 uint32_t fw_ddr_ram_end;
4253
4254 uint16_t fw_options[16];
4255 uint8_t fw_seriallink_options[4];
4256 __le16 fw_seriallink_options24[4];
4257
4258 uint8_t serdes_version[3];
4259 uint8_t mpi_version[3];
4260 uint32_t mpi_capabilities;
4261 uint8_t phy_version[3];
4262 uint8_t pep_version[3];
4263
4264
4265 struct fwdt {
4266 void *template;
4267 ulong length;
4268 ulong dump_size;
4269 } fwdt[2];
4270 struct qla2xxx_fw_dump *fw_dump;
4271 uint32_t fw_dump_len;
4272 u32 fw_dump_alloc_len;
4273 bool fw_dumped;
4274 unsigned long fw_dump_cap_flags;
4275#define RISC_PAUSE_CMPL 0
4276#define DMA_SHUTDOWN_CMPL 1
4277#define ISP_RESET_CMPL 2
4278#define RISC_RDY_AFT_RESET 3
4279#define RISC_SRAM_DUMP_CMPL 4
4280#define RISC_EXT_MEM_DUMP_CMPL 5
4281#define ISP_MBX_RDY 6
4282#define ISP_SOFT_RESET_CMPL 7
4283 int fw_dump_reading;
4284 void *mpi_fw_dump;
4285 u32 mpi_fw_dump_len;
4286 unsigned int mpi_fw_dump_reading:1;
4287 unsigned int mpi_fw_dumped:1;
4288 int prev_minidump_failed;
4289 dma_addr_t eft_dma;
4290 void *eft;
4291
4292#define MCTP_DUMP_SIZE 0x086064
4293 dma_addr_t mctp_dump_dma;
4294 void *mctp_dump;
4295 int mctp_dumped;
4296 int mctp_dump_reading;
4297 uint32_t chain_offset;
4298 struct dentry *dfs_dir;
4299 struct dentry *dfs_fce;
4300 struct dentry *dfs_tgt_counters;
4301 struct dentry *dfs_fw_resource_cnt;
4302
4303 dma_addr_t fce_dma;
4304 void *fce;
4305 uint32_t fce_bufs;
4306 uint16_t fce_mb[8];
4307 uint64_t fce_wr, fce_rd;
4308 struct mutex fce_mutex;
4309
4310 uint32_t pci_attr;
4311 uint16_t chip_revision;
4312
4313 uint16_t product_id[4];
4314
4315 uint8_t model_number[16+1];
4316 char model_desc[80];
4317 uint8_t adapter_id[16+1];
4318
4319
4320 char *optrom_buffer;
4321 uint32_t optrom_size;
4322 int optrom_state;
4323#define QLA_SWAITING 0
4324#define QLA_SREADING 1
4325#define QLA_SWRITING 2
4326 uint32_t optrom_region_start;
4327 uint32_t optrom_region_size;
4328 struct mutex optrom_mutex;
4329
4330
4331#define ROM_CODE_TYPE_BIOS 0
4332#define ROM_CODE_TYPE_FCODE 1
4333#define ROM_CODE_TYPE_EFI 3
4334 uint8_t bios_revision[2];
4335 uint8_t efi_revision[2];
4336 uint8_t fcode_revision[16];
4337 uint32_t fw_revision[4];
4338
4339 uint32_t gold_fw_version[4];
4340
4341
4342 uint32_t flash_conf_off;
4343 uint32_t flash_data_off;
4344 uint32_t nvram_conf_off;
4345 uint32_t nvram_data_off;
4346
4347 uint32_t fdt_wrt_disable;
4348 uint32_t fdt_wrt_enable;
4349 uint32_t fdt_erase_cmd;
4350 uint32_t fdt_block_size;
4351 uint32_t fdt_unprotect_sec_cmd;
4352 uint32_t fdt_protect_sec_cmd;
4353 uint32_t fdt_wrt_sts_reg_cmd;
4354
4355 struct {
4356 uint32_t flt_region_flt;
4357 uint32_t flt_region_fdt;
4358 uint32_t flt_region_boot;
4359 uint32_t flt_region_boot_sec;
4360 uint32_t flt_region_fw;
4361 uint32_t flt_region_fw_sec;
4362 uint32_t flt_region_vpd_nvram;
4363 uint32_t flt_region_vpd_nvram_sec;
4364 uint32_t flt_region_vpd;
4365 uint32_t flt_region_vpd_sec;
4366 uint32_t flt_region_nvram;
4367 uint32_t flt_region_nvram_sec;
4368 uint32_t flt_region_npiv_conf;
4369 uint32_t flt_region_gold_fw;
4370 uint32_t flt_region_fcp_prio;
4371 uint32_t flt_region_bootload;
4372 uint32_t flt_region_img_status_pri;
4373 uint32_t flt_region_img_status_sec;
4374 uint32_t flt_region_aux_img_status_pri;
4375 uint32_t flt_region_aux_img_status_sec;
4376 };
4377 uint8_t active_image;
4378
4379
4380 uint16_t beacon_blink_led;
4381 uint8_t beacon_color_state;
4382#define QLA_LED_GRN_ON 0x01
4383#define QLA_LED_YLW_ON 0x02
4384#define QLA_LED_ABR_ON 0x04
4385#define QLA_LED_ALL_ON 0x07
4386
4387 uint16_t zio_mode;
4388 uint16_t zio_timer;
4389
4390 struct qla_msix_entry *msix_entries;
4391
4392 struct list_head vp_list;
4393 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4394 sizeof(unsigned long)];
4395 uint16_t num_vhosts;
4396 uint16_t num_vsans;
4397 uint16_t max_npiv_vports;
4398 int cur_vport_count;
4399
4400 struct qla_chip_state_84xx *cs84xx;
4401 struct isp_operations *isp_ops;
4402 struct workqueue_struct *wq;
4403 struct qlfc_fw fw_buf;
4404
4405
4406 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4407
4408 struct dma_pool *dl_dma_pool;
4409#define DSD_LIST_DMA_POOL_SIZE 512
4410
4411 struct dma_pool *fcp_cmnd_dma_pool;
4412 mempool_t *ctx_mempool;
4413#define FCP_CMND_DMA_POOL_SIZE 512
4414
4415 void __iomem *nx_pcibase;
4416 void __iomem *nxdb_rd_ptr;
4417 void __iomem *nxdb_wr_ptr;
4418
4419 uint32_t crb_win;
4420 uint32_t curr_window;
4421 uint32_t ddr_mn_window;
4422 unsigned long mn_win_crb;
4423 unsigned long ms_win_crb;
4424 int qdr_sn_window;
4425 uint32_t fcoe_dev_init_timeout;
4426 uint32_t fcoe_reset_timeout;
4427 rwlock_t hw_lock;
4428 uint16_t portnum;
4429 int link_width;
4430 struct fw_blob *hablob;
4431 struct qla82xx_legacy_intr_set nx_legacy_intr;
4432
4433 uint16_t gbl_dsd_inuse;
4434 uint16_t gbl_dsd_avail;
4435 struct list_head gbl_dsd_list;
4436#define NUM_DSD_CHAIN 4096
4437
4438 uint8_t fw_type;
4439 uint32_t file_prd_off;
4440
4441 uint32_t md_template_size;
4442 void *md_tmplt_hdr;
4443 dma_addr_t md_tmplt_hdr_dma;
4444 void *md_dump;
4445 uint32_t md_dump_size;
4446
4447 void *loop_id_map;
4448
4449
4450 uint32_t idc_audit_ts;
4451 uint32_t idc_extend_tmo;
4452
4453
4454 struct workqueue_struct *dpc_lp_wq;
4455 struct work_struct idc_aen;
4456
4457 struct workqueue_struct *dpc_hp_wq;
4458 struct work_struct nic_core_reset;
4459 struct work_struct idc_state_handler;
4460 struct work_struct nic_core_unrecoverable;
4461 struct work_struct board_disable;
4462
4463 struct mr_data_fx00 mr;
4464 uint32_t chip_reset;
4465
4466 struct qlt_hw_data tgt;
4467 int allow_cna_fw_dump;
4468 uint32_t fw_ability_mask;
4469 uint16_t min_supported_speed;
4470 uint16_t max_supported_speed;
4471
4472
4473 struct dma_pool *dif_bundl_pool;
4474 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4475 struct {
4476 struct {
4477 struct list_head head;
4478 uint count;
4479 } good;
4480 struct {
4481 struct list_head head;
4482 uint count;
4483 } unusable;
4484 } pool;
4485
4486 unsigned long long dif_bundle_crossed_pages;
4487 unsigned long long dif_bundle_reads;
4488 unsigned long long dif_bundle_writes;
4489 unsigned long long dif_bundle_kallocs;
4490 unsigned long long dif_bundle_dma_allocs;
4491
4492 atomic_t nvme_active_aen_cnt;
4493 uint16_t nvme_last_rptd_aen;
4494
4495 uint8_t fc4_type_priority;
4496
4497 atomic_t zio_threshold;
4498 uint16_t last_zio_threshold;
4499
4500#define DEFAULT_ZIO_THRESHOLD 5
4501
4502 struct qla_hw_data_stat stat;
4503};
4504
4505struct active_regions {
4506 uint8_t global;
4507 struct {
4508 uint8_t board_config;
4509 uint8_t vpd_nvram;
4510 uint8_t npiv_config_0_1;
4511 uint8_t npiv_config_2_3;
4512 } aux;
4513};
4514
4515#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4516#define FW_ABILITY_MAX_SPEED_16G 0x0
4517#define FW_ABILITY_MAX_SPEED_32G 0x1
4518#define FW_ABILITY_MAX_SPEED(ha) \
4519 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4520
4521#define QLA_GET_DATA_RATE 0
4522#define QLA_SET_DATA_RATE_NOLR 1
4523#define QLA_SET_DATA_RATE_LR 2
4524
4525struct purex_item {
4526 struct list_head list;
4527 struct scsi_qla_host *vha;
4528 void (*process_item)(struct scsi_qla_host *vha, void *pkt);
4529 struct {
4530 uint8_t iocb[64];
4531 } iocb;
4532};
4533
4534
4535
4536
4537typedef struct scsi_qla_host {
4538 struct list_head list;
4539 struct list_head vp_fcports;
4540 struct list_head work_list;
4541 spinlock_t work_lock;
4542 struct work_struct iocb_work;
4543
4544
4545 struct Scsi_Host *host;
4546 unsigned long host_no;
4547 uint8_t host_str[16];
4548
4549 volatile struct {
4550 uint32_t init_done :1;
4551 uint32_t online :1;
4552 uint32_t reset_active :1;
4553
4554 uint32_t management_server_logged_in :1;
4555 uint32_t process_response_queue :1;
4556 uint32_t difdix_supported:1;
4557 uint32_t delete_progress:1;
4558
4559 uint32_t fw_tgt_reported:1;
4560 uint32_t bbcr_enable:1;
4561 uint32_t qpairs_available:1;
4562 uint32_t qpairs_req_created:1;
4563 uint32_t qpairs_rsp_created:1;
4564 uint32_t nvme_enabled:1;
4565 uint32_t nvme_first_burst:1;
4566 } flags;
4567
4568 atomic_t loop_state;
4569#define LOOP_TIMEOUT 1
4570#define LOOP_DOWN 2
4571#define LOOP_UP 3
4572#define LOOP_UPDATE 4
4573#define LOOP_READY 5
4574#define LOOP_DEAD 6
4575
4576 unsigned long relogin_jif;
4577 unsigned long dpc_flags;
4578#define RESET_MARKER_NEEDED 0
4579#define RESET_ACTIVE 1
4580#define ISP_ABORT_NEEDED 2
4581#define ABORT_ISP_ACTIVE 3
4582#define LOOP_RESYNC_NEEDED 4
4583#define LOOP_RESYNC_ACTIVE 5
4584#define LOCAL_LOOP_UPDATE 6
4585#define RSCN_UPDATE 7
4586#define RELOGIN_NEEDED 8
4587#define REGISTER_FC4_NEEDED 9
4588#define ISP_ABORT_RETRY 10
4589#define BEACON_BLINK_NEEDED 11
4590#define REGISTER_FDMI_NEEDED 12
4591#define FCPORT_UPDATE_NEEDED 13
4592#define VP_DPC_NEEDED 14
4593#define UNLOADING 15
4594#define NPIV_CONFIG_NEEDED 16
4595#define ISP_UNRECOVERABLE 17
4596#define FCOE_CTX_RESET_NEEDED 18
4597#define MPI_RESET_NEEDED 19
4598#define ISP_QUIESCE_NEEDED 20
4599#define N2N_LINK_RESET 21
4600#define PORT_UPDATE_NEEDED 22
4601#define FX00_RESET_RECOVERY 23
4602#define FX00_TARGET_SCAN 24
4603#define FX00_CRITEMP_RECOVERY 25
4604#define FX00_HOST_INFO_RESEND 26
4605#define QPAIR_ONLINE_CHECK_NEEDED 27
4606#define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4607#define DETECT_SFP_CHANGE 29
4608#define N2N_LOGIN_NEEDED 30
4609#define IOCB_WORK_ACTIVE 31
4610#define SET_ZIO_THRESHOLD_NEEDED 32
4611#define ISP_ABORT_TO_ROM 33
4612#define VPORT_DELETE 34
4613
4614#define PROCESS_PUREX_IOCB 63
4615
4616 unsigned long pci_flags;
4617#define PFLG_DISCONNECTED 0
4618#define PFLG_DRIVER_REMOVING 1
4619#define PFLG_DRIVER_PROBING 2
4620
4621 uint32_t device_flags;
4622#define SWITCH_FOUND BIT_0
4623#define DFLG_NO_CABLE BIT_1
4624#define DFLG_DEV_FAILED BIT_5
4625
4626
4627 uint16_t loop_id;
4628 uint16_t self_login_loop_id;
4629
4630
4631 fc_port_t bidir_fcport;
4632
4633
4634
4635
4636 port_id_t d_id;
4637 uint8_t marker_needed;
4638 uint16_t mgmt_svr_loop_id;
4639
4640
4641
4642
4643 uint8_t loop_down_abort_time;
4644 atomic_t loop_down_timer;
4645 uint8_t link_down_timeout;
4646
4647 uint32_t timer_active;
4648 struct timer_list timer;
4649
4650 uint8_t node_name[WWN_SIZE];
4651 uint8_t port_name[WWN_SIZE];
4652 uint8_t fabric_node_name[WWN_SIZE];
4653 uint8_t fabric_port_name[WWN_SIZE];
4654
4655 struct nvme_fc_local_port *nvme_local_port;
4656 struct completion nvme_del_done;
4657
4658 uint16_t fcoe_vlan_id;
4659 uint16_t fcoe_fcf_idx;
4660 uint8_t fcoe_vn_port_mac[6];
4661
4662
4663 struct list_head qla_cmd_list;
4664 struct list_head qla_sess_op_cmd_list;
4665 struct list_head unknown_atio_list;
4666 spinlock_t cmd_list_lock;
4667 struct delayed_work unknown_atio_work;
4668
4669
4670 atomic_t generation_tick;
4671
4672 int total_fcport_update_gen;
4673
4674 struct list_head logo_list;
4675
4676 struct list_head plogi_ack_list;
4677
4678 struct list_head qp_list;
4679
4680 uint32_t vp_abort_cnt;
4681
4682 struct fc_vport *fc_vport;
4683 uint16_t vp_idx;
4684 struct qla_qpair *qpair;
4685
4686 unsigned long vp_flags;
4687#define VP_IDX_ACQUIRED 0
4688#define VP_CREATE_NEEDED 1
4689#define VP_BIND_NEEDED 2
4690#define VP_DELETE_NEEDED 3
4691#define VP_SCR_NEEDED 4
4692#define VP_CONFIG_OK 5
4693 atomic_t vp_state;
4694#define VP_OFFLINE 0
4695#define VP_ACTIVE 1
4696#define VP_FAILED 2
4697
4698 uint16_t vp_err_state;
4699 uint16_t vp_prev_err_state;
4700#define VP_ERR_UNKWN 0
4701#define VP_ERR_PORTDWN 1
4702#define VP_ERR_FAB_UNSUPPORTED 2
4703#define VP_ERR_FAB_NORESOURCES 3
4704#define VP_ERR_FAB_LOGOUT 4
4705#define VP_ERR_ADAP_NORESOURCES 5
4706 struct qla_hw_data *hw;
4707 struct scsi_qlt_host vha_tgt;
4708 struct req_que *req;
4709 int fw_heartbeat_counter;
4710 int seconds_since_last_heartbeat;
4711 struct fc_host_statistics fc_host_stat;
4712 struct qla_statistics qla_stats;
4713 struct bidi_statistics bidi_stats;
4714 atomic_t vref_count;
4715 struct qla8044_reset_template reset_tmplt;
4716 uint16_t bbcr;
4717
4718 uint16_t u_ql2xexchoffld;
4719 uint16_t u_ql2xiniexchg;
4720 uint16_t qlini_mode;
4721 uint16_t ql2xexchoffld;
4722 uint16_t ql2xiniexchg;
4723
4724 struct purex_list {
4725 struct list_head head;
4726 spinlock_t lock;
4727 } purex_list;
4728
4729 struct name_list_extended gnl;
4730
4731 int fcport_count;
4732 wait_queue_head_t fcport_waitQ;
4733 wait_queue_head_t vref_waitq;
4734 uint8_t min_supported_speed;
4735 uint8_t n2n_node_name[WWN_SIZE];
4736 uint8_t n2n_port_name[WWN_SIZE];
4737 uint16_t n2n_id;
4738 __le16 dport_data[4];
4739 struct list_head gpnid_list;
4740 struct fab_scan scan;
4741
4742 unsigned int irq_offset;
4743} scsi_qla_host_t;
4744
4745struct qla27xx_image_status {
4746 uint8_t image_status_mask;
4747 __le16 generation;
4748 uint8_t ver_major;
4749 uint8_t ver_minor;
4750 uint8_t bitmap;
4751 uint8_t reserved[2];
4752 __le32 checksum;
4753 __le32 signature;
4754} __packed;
4755
4756
4757#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4758#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4759#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4760#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4761
4762#define SET_VP_IDX 1
4763#define SET_AL_PA 2
4764#define RESET_VP_IDX 3
4765#define RESET_AL_PA 4
4766struct qla_tgt_vp_map {
4767 uint8_t idx;
4768 scsi_qla_host_t *vha;
4769};
4770
4771struct qla2_sgx {
4772 dma_addr_t dma_addr;
4773 uint32_t dma_len;
4774
4775 uint32_t tot_bytes;
4776 struct scatterlist *cur_sg;
4777
4778
4779 uint32_t bytes_consumed;
4780 uint32_t num_bytes;
4781 uint32_t tot_partial;
4782
4783
4784 uint32_t num_sg;
4785 srb_t *sp;
4786};
4787
4788#define QLA_FW_STARTED(_ha) { \
4789 int i; \
4790 _ha->flags.fw_started = 1; \
4791 _ha->base_qpair->fw_started = 1; \
4792 for (i = 0; i < _ha->max_qpairs; i++) { \
4793 if (_ha->queue_pair_map[i]) \
4794 _ha->queue_pair_map[i]->fw_started = 1; \
4795 } \
4796}
4797
4798#define QLA_FW_STOPPED(_ha) { \
4799 int i; \
4800 _ha->flags.fw_started = 0; \
4801 _ha->base_qpair->fw_started = 0; \
4802 for (i = 0; i < _ha->max_qpairs; i++) { \
4803 if (_ha->queue_pair_map[i]) \
4804 _ha->queue_pair_map[i]->fw_started = 0; \
4805 } \
4806}
4807
4808
4809#define SFUB_CHECKSUM_SIZE 4
4810
4811struct secure_flash_update_block {
4812 uint32_t block_info;
4813 uint32_t signature_lo;
4814 uint32_t signature_hi;
4815 uint32_t signature_upper[0x3e];
4816};
4817
4818struct secure_flash_update_block_pk {
4819 uint32_t block_info;
4820 uint32_t signature_lo;
4821 uint32_t signature_hi;
4822 uint32_t signature_upper[0x3e];
4823 uint32_t public_key[0x41];
4824};
4825
4826
4827
4828
4829#define LOOP_TRANSITION(ha) \
4830 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4831 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4832 atomic_read(&ha->loop_state) == LOOP_DOWN)
4833
4834#define STATE_TRANSITION(ha) \
4835 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4836 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4837
4838#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4839 atomic_inc(&__vha->vref_count); \
4840 mb(); \
4841 if (__vha->flags.delete_progress) { \
4842 atomic_dec(&__vha->vref_count); \
4843 wake_up(&__vha->vref_waitq); \
4844 __bail = 1; \
4845 } else { \
4846 __bail = 0; \
4847 } \
4848} while (0)
4849
4850#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4851 atomic_dec(&__vha->vref_count); \
4852 wake_up(&__vha->vref_waitq); \
4853} while (0) \
4854
4855#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4856 atomic_inc(&__qpair->ref_count); \
4857 mb(); \
4858 if (__qpair->delete_in_progress) { \
4859 atomic_dec(&__qpair->ref_count); \
4860 __bail = 1; \
4861 } else { \
4862 __bail = 0; \
4863 } \
4864} while (0)
4865
4866#define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4867 atomic_dec(&__qpair->ref_count); \
4868
4869
4870#define QLA_ENA_CONF(_ha) {\
4871 int i;\
4872 _ha->base_qpair->enable_explicit_conf = 1; \
4873 for (i = 0; i < _ha->max_qpairs; i++) { \
4874 if (_ha->queue_pair_map[i]) \
4875 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4876 } \
4877}
4878
4879#define QLA_DIS_CONF(_ha) {\
4880 int i;\
4881 _ha->base_qpair->enable_explicit_conf = 0; \
4882 for (i = 0; i < _ha->max_qpairs; i++) { \
4883 if (_ha->queue_pair_map[i]) \
4884 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4885 } \
4886}
4887
4888
4889
4890
4891#define MBS_MASK 0x3fff
4892
4893#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4894#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4895#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4896#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4897#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4898#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4899#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4900#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4901#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4902#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4903
4904#define QLA_FUNCTION_TIMEOUT 0x100
4905#define QLA_FUNCTION_PARAMETER_ERROR 0x101
4906#define QLA_FUNCTION_FAILED 0x102
4907#define QLA_MEMORY_ALLOC_FAILED 0x103
4908#define QLA_LOCK_TIMEOUT 0x104
4909#define QLA_ABORTED 0x105
4910#define QLA_SUSPENDED 0x106
4911#define QLA_BUSY 0x107
4912#define QLA_ALREADY_REGISTERED 0x109
4913#define QLA_OS_TIMER_EXPIRED 0x10a
4914
4915#define NVRAM_DELAY() udelay(10)
4916
4917
4918
4919
4920#define OPTROM_SIZE_2300 0x20000
4921#define OPTROM_SIZE_2322 0x100000
4922#define OPTROM_SIZE_24XX 0x100000
4923#define OPTROM_SIZE_25XX 0x200000
4924#define OPTROM_SIZE_81XX 0x400000
4925#define OPTROM_SIZE_82XX 0x800000
4926#define OPTROM_SIZE_83XX 0x1000000
4927#define OPTROM_SIZE_28XX 0x2000000
4928
4929#define OPTROM_BURST_SIZE 0x1000
4930#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4931
4932#define QLA_DSDS_PER_IOCB 37
4933
4934#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4935
4936#define QLA_SG_ALL 1024
4937
4938enum nexus_wait_type {
4939 WAIT_HOST = 0,
4940 WAIT_TARGET,
4941 WAIT_LUN,
4942};
4943
4944
4945struct sff_8247_a0 {
4946 u8 txid;
4947 u8 ext_txid;
4948 u8 connector;
4949
4950 u8 eth_infi_cc3;
4951 u8 sonet_cc4[2];
4952 u8 eth_cc6;
4953
4954#define FC_LL_VL BIT_7
4955#define FC_LL_S BIT_6
4956#define FC_LL_I BIT_5
4957#define FC_LL_L BIT_4
4958#define FC_LL_M BIT_3
4959#define FC_LL_SA BIT_2
4960#define FC_LL_LC BIT_1
4961#define FC_LL_EL BIT_0
4962 u8 fc_ll_cc7;
4963
4964#define FC_TEC_EL BIT_7
4965#define FC_TEC_SN BIT_6
4966#define FC_TEC_SL BIT_5
4967#define FC_TEC_LL BIT_4
4968#define FC_TEC_ACT BIT_3
4969#define FC_TEC_PAS BIT_2
4970 u8 fc_tec_cc8;
4971
4972#define FC_MED_TW BIT_7
4973#define FC_MED_TP BIT_6
4974#define FC_MED_MI BIT_5
4975#define FC_MED_TV BIT_4
4976#define FC_MED_M6 BIT_3
4977#define FC_MED_M5 BIT_2
4978#define FC_MED_SM BIT_0
4979 u8 fc_med_cc9;
4980
4981#define FC_SP_12 BIT_7
4982#define FC_SP_8 BIT_6
4983#define FC_SP_16 BIT_5
4984#define FC_SP_4 BIT_4
4985#define FC_SP_32 BIT_3
4986#define FC_SP_2 BIT_2
4987#define FC_SP_1 BIT_0
4988 u8 fc_sp_cc10;
4989 u8 encode;
4990 u8 bitrate;
4991 u8 rate_id;
4992 u8 length_km;
4993 u8 length_100m;
4994 u8 length_50um_10m;
4995 u8 length_62um_10m;
4996 u8 length_om4_10m;
4997 u8 length_om3_10m;
4998#define SFF_VEN_NAME_LEN 16
4999 u8 vendor_name[SFF_VEN_NAME_LEN];
5000 u8 tx_compat;
5001 u8 vendor_oui[3];
5002#define SFF_PART_NAME_LEN 16
5003 u8 vendor_pn[SFF_PART_NAME_LEN];
5004 u8 vendor_rev[4];
5005 u8 wavelength[2];
5006 u8 resv;
5007 u8 cc_base;
5008 u8 options[2];
5009 u8 br_max;
5010 u8 br_min;
5011 u8 vendor_sn[16];
5012 u8 date_code[8];
5013 u8 diag;
5014 u8 enh_options;
5015 u8 sff_revision;
5016 u8 cc_ext;
5017 u8 vendor_specific[32];
5018 u8 resv2[128];
5019};
5020
5021
5022#define IS_BPM_CAPABLE(ha) \
5023 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
5024 IS_QLA27XX(ha) || IS_QLA28XX(ha))
5025#define IS_BPM_RANGE_CAPABLE(ha) \
5026 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5027#define IS_BPM_ENABLED(vha) \
5028 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
5029
5030#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
5031
5032#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
5033 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
5034
5035#define SAVE_TOPO(_ha) { \
5036 if (_ha->current_topology) \
5037 _ha->prev_topology = _ha->current_topology; \
5038}
5039
5040#define N2N_TOPO(ha) \
5041 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5042 ha->current_topology == ISP_CFG_N || \
5043 !ha->current_topology)
5044
5045#define NVME_TYPE(fcport) \
5046 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5047
5048#define FCP_TYPE(fcport) \
5049 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5050
5051#define NVME_ONLY_TARGET(fcport) \
5052 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5053
5054#define NVME_FCP_TARGET(fcport) \
5055 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5056
5057#define NVME_TARGET(ha, fcport) \
5058 ((NVME_FCP_TARGET(fcport) && \
5059 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \
5060 NVME_ONLY_TARGET(fcport)) \
5061
5062#define PRLI_PHASE(_cls) \
5063 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5064
5065#include "qla_target.h"
5066#include "qla_gbl.h"
5067#include "qla_dbg.h"
5068#include "qla_inline.h"
5069#endif
5070