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8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/i2c.h>
12#include <linux/slab.h>
13#include <linux/v4l2-mediabus.h>
14
15#include <media/soc_camera.h>
16#include <media/v4l2-clk.h>
17#include <media/v4l2-ctrls.h>
18
19#define to_ov9740(sd) container_of(sd, struct ov9740_priv, subdev)
20
21
22#define OV9740_MODEL_ID_HI 0x0000
23#define OV9740_MODEL_ID_LO 0x0001
24#define OV9740_REVISION_NUMBER 0x0002
25#define OV9740_MANUFACTURER_ID 0x0003
26#define OV9740_SMIA_VERSION 0x0004
27
28
29#define OV9740_MODE_SELECT 0x0100
30#define OV9740_IMAGE_ORT 0x0101
31#define OV9740_SOFTWARE_RESET 0x0103
32#define OV9740_GRP_PARAM_HOLD 0x0104
33#define OV9740_MSK_CORRUP_FM 0x0105
34
35
36#define OV9740_FRM_LENGTH_LN_HI 0x0340
37#define OV9740_FRM_LENGTH_LN_LO 0x0341
38#define OV9740_LN_LENGTH_PCK_HI 0x0342
39#define OV9740_LN_LENGTH_PCK_LO 0x0343
40#define OV9740_X_ADDR_START_HI 0x0344
41#define OV9740_X_ADDR_START_LO 0x0345
42#define OV9740_Y_ADDR_START_HI 0x0346
43#define OV9740_Y_ADDR_START_LO 0x0347
44#define OV9740_X_ADDR_END_HI 0x0348
45#define OV9740_X_ADDR_END_LO 0x0349
46#define OV9740_Y_ADDR_END_HI 0x034a
47#define OV9740_Y_ADDR_END_LO 0x034b
48#define OV9740_X_OUTPUT_SIZE_HI 0x034c
49#define OV9740_X_OUTPUT_SIZE_LO 0x034d
50#define OV9740_Y_OUTPUT_SIZE_HI 0x034e
51#define OV9740_Y_OUTPUT_SIZE_LO 0x034f
52
53
54#define OV9740_IO_CREL00 0x3002
55#define OV9740_IO_CREL01 0x3004
56#define OV9740_IO_CREL02 0x3005
57#define OV9740_IO_OUTPUT_SEL01 0x3026
58#define OV9740_IO_OUTPUT_SEL02 0x3027
59
60
61#define OV9740_AWB_MANUAL_CTRL 0x3406
62
63
64#define OV9740_ANALOG_CTRL01 0x3601
65#define OV9740_ANALOG_CTRL02 0x3602
66#define OV9740_ANALOG_CTRL03 0x3603
67#define OV9740_ANALOG_CTRL04 0x3604
68#define OV9740_ANALOG_CTRL10 0x3610
69#define OV9740_ANALOG_CTRL12 0x3612
70#define OV9740_ANALOG_CTRL15 0x3615
71#define OV9740_ANALOG_CTRL20 0x3620
72#define OV9740_ANALOG_CTRL21 0x3621
73#define OV9740_ANALOG_CTRL22 0x3622
74#define OV9740_ANALOG_CTRL30 0x3630
75#define OV9740_ANALOG_CTRL31 0x3631
76#define OV9740_ANALOG_CTRL32 0x3632
77#define OV9740_ANALOG_CTRL33 0x3633
78
79
80#define OV9740_SENSOR_CTRL03 0x3703
81#define OV9740_SENSOR_CTRL04 0x3704
82#define OV9740_SENSOR_CTRL05 0x3705
83#define OV9740_SENSOR_CTRL07 0x3707
84
85
86#define OV9740_TIMING_CTRL17 0x3817
87#define OV9740_TIMING_CTRL19 0x3819
88#define OV9740_TIMING_CTRL33 0x3833
89#define OV9740_TIMING_CTRL35 0x3835
90
91
92#define OV9740_AEC_MAXEXPO_60_H 0x3a02
93#define OV9740_AEC_MAXEXPO_60_L 0x3a03
94#define OV9740_AEC_B50_STEP_HI 0x3a08
95#define OV9740_AEC_B50_STEP_LO 0x3a09
96#define OV9740_AEC_B60_STEP_HI 0x3a0a
97#define OV9740_AEC_B60_STEP_LO 0x3a0b
98#define OV9740_AEC_CTRL0D 0x3a0d
99#define OV9740_AEC_CTRL0E 0x3a0e
100#define OV9740_AEC_MAXEXPO_50_H 0x3a14
101#define OV9740_AEC_MAXEXPO_50_L 0x3a15
102
103
104#define OV9740_AEC_ENABLE 0x3503
105#define OV9740_GAIN_CEILING_01 0x3a18
106#define OV9740_GAIN_CEILING_02 0x3a19
107#define OV9740_AEC_HI_THRESHOLD 0x3a11
108#define OV9740_AEC_3A1A 0x3a1a
109#define OV9740_AEC_CTRL1B_WPT2 0x3a1b
110#define OV9740_AEC_CTRL0F_WPT 0x3a0f
111#define OV9740_AEC_CTRL10_BPT 0x3a10
112#define OV9740_AEC_CTRL1E_BPT2 0x3a1e
113#define OV9740_AEC_LO_THRESHOLD 0x3a1f
114
115
116#define OV9740_BLC_AUTO_ENABLE 0x4002
117#define OV9740_BLC_MODE 0x4005
118
119
120#define OV9740_VFIFO_READ_START_HI 0x4608
121#define OV9740_VFIFO_READ_START_LO 0x4609
122
123
124#define OV9740_DVP_VSYNC_CTRL02 0x4702
125#define OV9740_DVP_VSYNC_MODE 0x4704
126#define OV9740_DVP_VSYNC_CTRL06 0x4706
127
128
129#define OV9740_PLL_MODE_CTRL01 0x3104
130#define OV9740_PRE_PLL_CLK_DIV 0x0305
131#define OV9740_PLL_MULTIPLIER 0x0307
132#define OV9740_VT_SYS_CLK_DIV 0x0303
133#define OV9740_VT_PIX_CLK_DIV 0x0301
134#define OV9740_PLL_CTRL3010 0x3010
135#define OV9740_VFIFO_CTRL00 0x460e
136
137
138#define OV9740_ISP_CTRL00 0x5000
139#define OV9740_ISP_CTRL01 0x5001
140#define OV9740_ISP_CTRL03 0x5003
141#define OV9740_ISP_CTRL05 0x5005
142#define OV9740_ISP_CTRL12 0x5012
143#define OV9740_ISP_CTRL19 0x5019
144#define OV9740_ISP_CTRL1A 0x501a
145#define OV9740_ISP_CTRL1E 0x501e
146#define OV9740_ISP_CTRL1F 0x501f
147#define OV9740_ISP_CTRL20 0x5020
148#define OV9740_ISP_CTRL21 0x5021
149
150
151#define OV9740_AWB_CTRL00 0x5180
152#define OV9740_AWB_CTRL01 0x5181
153#define OV9740_AWB_CTRL02 0x5182
154#define OV9740_AWB_CTRL03 0x5183
155#define OV9740_AWB_ADV_CTRL01 0x5184
156#define OV9740_AWB_ADV_CTRL02 0x5185
157#define OV9740_AWB_ADV_CTRL03 0x5186
158#define OV9740_AWB_ADV_CTRL04 0x5187
159#define OV9740_AWB_ADV_CTRL05 0x5188
160#define OV9740_AWB_ADV_CTRL06 0x5189
161#define OV9740_AWB_ADV_CTRL07 0x518a
162#define OV9740_AWB_ADV_CTRL08 0x518b
163#define OV9740_AWB_ADV_CTRL09 0x518c
164#define OV9740_AWB_ADV_CTRL10 0x518d
165#define OV9740_AWB_ADV_CTRL11 0x518e
166#define OV9740_AWB_CTRL0F 0x518f
167#define OV9740_AWB_CTRL10 0x5190
168#define OV9740_AWB_CTRL11 0x5191
169#define OV9740_AWB_CTRL12 0x5192
170#define OV9740_AWB_CTRL13 0x5193
171#define OV9740_AWB_CTRL14 0x5194
172
173
174#define OV9740_MIPI_CTRL00 0x4800
175#define OV9740_MIPI_3837 0x3837
176#define OV9740_MIPI_CTRL01 0x4801
177#define OV9740_MIPI_CTRL03 0x4803
178#define OV9740_MIPI_CTRL05 0x4805
179#define OV9740_VFIFO_RD_CTRL 0x4601
180#define OV9740_MIPI_CTRL_3012 0x3012
181#define OV9740_SC_CMMM_MIPI_CTR 0x3014
182
183#define OV9740_MAX_WIDTH 1280
184#define OV9740_MAX_HEIGHT 720
185
186
187struct ov9740_reg {
188 u16 reg;
189 u8 val;
190};
191
192struct ov9740_priv {
193 struct v4l2_subdev subdev;
194 struct v4l2_ctrl_handler hdl;
195 struct v4l2_clk *clk;
196
197 u16 model;
198 u8 revision;
199 u8 manid;
200 u8 smiaver;
201
202 bool flag_vflip;
203 bool flag_hflip;
204
205
206 struct v4l2_mbus_framefmt current_mf;
207 bool current_enable;
208};
209
210static const struct ov9740_reg ov9740_defaults[] = {
211
212 { OV9740_SOFTWARE_RESET, 0x01 },
213
214
215 { OV9740_AEC_B50_STEP_HI, 0x00 },
216 { OV9740_AEC_B50_STEP_LO, 0xe8 },
217 { OV9740_AEC_CTRL0E, 0x03 },
218 { OV9740_AEC_MAXEXPO_50_H, 0x15 },
219 { OV9740_AEC_MAXEXPO_50_L, 0xc6 },
220 { OV9740_AEC_B60_STEP_HI, 0x00 },
221 { OV9740_AEC_B60_STEP_LO, 0xc0 },
222 { OV9740_AEC_CTRL0D, 0x04 },
223 { OV9740_AEC_MAXEXPO_60_H, 0x18 },
224 { OV9740_AEC_MAXEXPO_60_L, 0x20 },
225
226
227 { 0x5842, 0x02 }, { 0x5843, 0x5e }, { 0x5844, 0x04 }, { 0x5845, 0x32 },
228 { 0x5846, 0x03 }, { 0x5847, 0x29 }, { 0x5848, 0x02 }, { 0x5849, 0xcc },
229
230
231 { 0x5800, 0x29 }, { 0x5801, 0x25 }, { 0x5802, 0x20 }, { 0x5803, 0x21 },
232 { 0x5804, 0x26 }, { 0x5805, 0x2e }, { 0x5806, 0x11 }, { 0x5807, 0x0c },
233 { 0x5808, 0x09 }, { 0x5809, 0x0a }, { 0x580a, 0x0e }, { 0x580b, 0x16 },
234 { 0x580c, 0x06 }, { 0x580d, 0x02 }, { 0x580e, 0x00 }, { 0x580f, 0x00 },
235 { 0x5810, 0x04 }, { 0x5811, 0x0a }, { 0x5812, 0x05 }, { 0x5813, 0x02 },
236 { 0x5814, 0x00 }, { 0x5815, 0x00 }, { 0x5816, 0x03 }, { 0x5817, 0x09 },
237 { 0x5818, 0x0f }, { 0x5819, 0x0a }, { 0x581a, 0x07 }, { 0x581b, 0x08 },
238 { 0x581c, 0x0b }, { 0x581d, 0x14 }, { 0x581e, 0x28 }, { 0x581f, 0x23 },
239 { 0x5820, 0x1d }, { 0x5821, 0x1e }, { 0x5822, 0x24 }, { 0x5823, 0x2a },
240 { 0x5824, 0x4f }, { 0x5825, 0x6f }, { 0x5826, 0x5f }, { 0x5827, 0x7f },
241 { 0x5828, 0x9f }, { 0x5829, 0x5f }, { 0x582a, 0x8f }, { 0x582b, 0x9e },
242 { 0x582c, 0x8f }, { 0x582d, 0x9f }, { 0x582e, 0x4f }, { 0x582f, 0x87 },
243 { 0x5830, 0x86 }, { 0x5831, 0x97 }, { 0x5832, 0xae }, { 0x5833, 0x3f },
244 { 0x5834, 0x8e }, { 0x5835, 0x7c }, { 0x5836, 0x7e }, { 0x5837, 0xaf },
245 { 0x5838, 0x8f }, { 0x5839, 0x8f }, { 0x583a, 0x9f }, { 0x583b, 0x7f },
246 { 0x583c, 0x5f },
247
248
249 { 0x5480, 0x07 }, { 0x5481, 0x18 }, { 0x5482, 0x2c }, { 0x5483, 0x4e },
250 { 0x5484, 0x5e }, { 0x5485, 0x6b }, { 0x5486, 0x77 }, { 0x5487, 0x82 },
251 { 0x5488, 0x8c }, { 0x5489, 0x95 }, { 0x548a, 0xa4 }, { 0x548b, 0xb1 },
252 { 0x548c, 0xc6 }, { 0x548d, 0xd8 }, { 0x548e, 0xe9 },
253
254
255 { 0x5490, 0x0f }, { 0x5491, 0xff }, { 0x5492, 0x0d }, { 0x5493, 0x05 },
256 { 0x5494, 0x07 }, { 0x5495, 0x1a }, { 0x5496, 0x04 }, { 0x5497, 0x01 },
257 { 0x5498, 0x03 }, { 0x5499, 0x53 }, { 0x549a, 0x02 }, { 0x549b, 0xeb },
258 { 0x549c, 0x02 }, { 0x549d, 0xa0 }, { 0x549e, 0x02 }, { 0x549f, 0x67 },
259 { 0x54a0, 0x02 }, { 0x54a1, 0x3b }, { 0x54a2, 0x02 }, { 0x54a3, 0x18 },
260 { 0x54a4, 0x01 }, { 0x54a5, 0xe7 }, { 0x54a6, 0x01 }, { 0x54a7, 0xc3 },
261 { 0x54a8, 0x01 }, { 0x54a9, 0x94 }, { 0x54aa, 0x01 }, { 0x54ab, 0x72 },
262 { 0x54ac, 0x01 }, { 0x54ad, 0x57 },
263
264
265 { OV9740_AWB_CTRL00, 0xf0 },
266 { OV9740_AWB_CTRL01, 0x00 },
267 { OV9740_AWB_CTRL02, 0x41 },
268 { OV9740_AWB_CTRL03, 0x42 },
269 { OV9740_AWB_ADV_CTRL01, 0x8a },
270 { OV9740_AWB_ADV_CTRL02, 0x61 },
271 { OV9740_AWB_ADV_CTRL03, 0xce },
272 { OV9740_AWB_ADV_CTRL04, 0xa8 },
273 { OV9740_AWB_ADV_CTRL05, 0x17 },
274 { OV9740_AWB_ADV_CTRL06, 0x1f },
275 { OV9740_AWB_ADV_CTRL07, 0x27 },
276 { OV9740_AWB_ADV_CTRL08, 0x41 },
277 { OV9740_AWB_ADV_CTRL09, 0x34 },
278 { OV9740_AWB_ADV_CTRL10, 0xf0 },
279 { OV9740_AWB_ADV_CTRL11, 0x10 },
280 { OV9740_AWB_CTRL0F, 0xff },
281 { OV9740_AWB_CTRL10, 0x00 },
282 { OV9740_AWB_CTRL11, 0xff },
283 { OV9740_AWB_CTRL12, 0x00 },
284 { OV9740_AWB_CTRL13, 0xff },
285 { OV9740_AWB_CTRL14, 0x00 },
286
287
288 { 0x530d, 0x12 },
289
290
291 { 0x5380, 0x01 }, { 0x5381, 0x00 }, { 0x5382, 0x00 }, { 0x5383, 0x17 },
292 { 0x5384, 0x00 }, { 0x5385, 0x01 }, { 0x5386, 0x00 }, { 0x5387, 0x00 },
293 { 0x5388, 0x00 }, { 0x5389, 0xe0 }, { 0x538a, 0x00 }, { 0x538b, 0x20 },
294 { 0x538c, 0x00 }, { 0x538d, 0x00 }, { 0x538e, 0x00 }, { 0x538f, 0x16 },
295 { 0x5390, 0x00 }, { 0x5391, 0x9c }, { 0x5392, 0x00 }, { 0x5393, 0xa0 },
296 { 0x5394, 0x18 },
297
298
299 { 0x3c0a, 0x9c }, { 0x3c0b, 0x3f },
300
301
302 { OV9740_IO_OUTPUT_SEL01, 0x00 },
303 { OV9740_IO_OUTPUT_SEL02, 0x00 },
304 { OV9740_IO_CREL00, 0x00 },
305 { OV9740_IO_CREL01, 0x00 },
306 { OV9740_IO_CREL02, 0x00 },
307
308
309 { OV9740_AWB_MANUAL_CTRL, 0x00 },
310
311
312 { OV9740_ANALOG_CTRL03, 0xaa },
313 { OV9740_ANALOG_CTRL32, 0x2f },
314 { OV9740_ANALOG_CTRL20, 0x66 },
315 { OV9740_ANALOG_CTRL21, 0xc0 },
316 { OV9740_ANALOG_CTRL31, 0x52 },
317 { OV9740_ANALOG_CTRL33, 0x50 },
318 { OV9740_ANALOG_CTRL30, 0xca },
319 { OV9740_ANALOG_CTRL04, 0x0c },
320 { OV9740_ANALOG_CTRL01, 0x40 },
321 { OV9740_ANALOG_CTRL02, 0x16 },
322 { OV9740_ANALOG_CTRL10, 0xa1 },
323 { OV9740_ANALOG_CTRL12, 0x24 },
324 { OV9740_ANALOG_CTRL22, 0x9f },
325 { OV9740_ANALOG_CTRL15, 0xf0 },
326
327
328 { OV9740_SENSOR_CTRL03, 0x42 },
329 { OV9740_SENSOR_CTRL04, 0x10 },
330 { OV9740_SENSOR_CTRL05, 0x45 },
331 { OV9740_SENSOR_CTRL07, 0x14 },
332
333
334 { OV9740_TIMING_CTRL33, 0x04 },
335 { OV9740_TIMING_CTRL35, 0x02 },
336 { OV9740_TIMING_CTRL19, 0x6e },
337 { OV9740_TIMING_CTRL17, 0x94 },
338
339
340 { OV9740_AEC_ENABLE, 0x10 },
341 { OV9740_GAIN_CEILING_01, 0x00 },
342 { OV9740_GAIN_CEILING_02, 0x7f },
343 { OV9740_AEC_HI_THRESHOLD, 0xa0 },
344 { OV9740_AEC_3A1A, 0x05 },
345 { OV9740_AEC_CTRL1B_WPT2, 0x50 },
346 { OV9740_AEC_CTRL0F_WPT, 0x50 },
347 { OV9740_AEC_CTRL10_BPT, 0x4c },
348 { OV9740_AEC_CTRL1E_BPT2, 0x4c },
349 { OV9740_AEC_LO_THRESHOLD, 0x26 },
350
351
352 { OV9740_BLC_AUTO_ENABLE, 0x45 },
353 { OV9740_BLC_MODE, 0x18 },
354
355
356 { OV9740_DVP_VSYNC_CTRL02, 0x04 },
357 { OV9740_DVP_VSYNC_MODE, 0x00 },
358 { OV9740_DVP_VSYNC_CTRL06, 0x08 },
359
360
361 { OV9740_PLL_MODE_CTRL01, 0x20 },
362 { OV9740_PRE_PLL_CLK_DIV, 0x03 },
363 { OV9740_PLL_MULTIPLIER, 0x4c },
364 { OV9740_VT_SYS_CLK_DIV, 0x01 },
365 { OV9740_VT_PIX_CLK_DIV, 0x08 },
366 { OV9740_PLL_CTRL3010, 0x01 },
367 { OV9740_VFIFO_CTRL00, 0x82 },
368
369
370
371 { OV9740_FRM_LENGTH_LN_HI, 0x03 },
372 { OV9740_FRM_LENGTH_LN_LO, 0x07 },
373
374 { OV9740_LN_LENGTH_PCK_HI, 0x06 },
375 { OV9740_LN_LENGTH_PCK_LO, 0x62 },
376
377
378 { OV9740_MIPI_CTRL00, 0x44 },
379 { OV9740_MIPI_3837, 0x01 },
380 { OV9740_MIPI_CTRL01, 0x0f },
381 { OV9740_MIPI_CTRL03, 0x05 },
382 { OV9740_MIPI_CTRL05, 0x10 },
383 { OV9740_VFIFO_RD_CTRL, 0x16 },
384 { OV9740_MIPI_CTRL_3012, 0x70 },
385 { OV9740_SC_CMMM_MIPI_CTR, 0x01 },
386
387
388 { OV9740_ISP_CTRL19, 0x02 },
389};
390
391static u32 ov9740_codes[] = {
392 MEDIA_BUS_FMT_YUYV8_2X8,
393};
394
395
396static int ov9740_reg_read(struct i2c_client *client, u16 reg, u8 *val)
397{
398 int ret;
399 struct i2c_msg msg[] = {
400 {
401 .addr = client->addr,
402 .flags = 0,
403 .len = 2,
404 .buf = (u8 *)®,
405 },
406 {
407 .addr = client->addr,
408 .flags = I2C_M_RD,
409 .len = 1,
410 .buf = val,
411 },
412 };
413
414 reg = swab16(reg);
415
416 ret = i2c_transfer(client->adapter, msg, 2);
417 if (ret < 0) {
418 dev_err(&client->dev, "Failed reading register 0x%04x!\n", reg);
419 return ret;
420 }
421
422 return 0;
423}
424
425
426static int ov9740_reg_write(struct i2c_client *client, u16 reg, u8 val)
427{
428 struct i2c_msg msg;
429 struct {
430 u16 reg;
431 u8 val;
432 } __packed buf;
433 int ret;
434
435 reg = swab16(reg);
436
437 buf.reg = reg;
438 buf.val = val;
439
440 msg.addr = client->addr;
441 msg.flags = 0;
442 msg.len = 3;
443 msg.buf = (u8 *)&buf;
444
445 ret = i2c_transfer(client->adapter, &msg, 1);
446 if (ret < 0) {
447 dev_err(&client->dev, "Failed writing register 0x%04x!\n", reg);
448 return ret;
449 }
450
451 return 0;
452}
453
454
455
456static int ov9740_reg_rmw(struct i2c_client *client, u16 reg, u8 set, u8 unset)
457{
458 u8 val;
459 int ret;
460
461 ret = ov9740_reg_read(client, reg, &val);
462 if (ret < 0) {
463 dev_err(&client->dev,
464 "[Read]-Modify-Write of register 0x%04x failed!\n",
465 reg);
466 return ret;
467 }
468
469 val |= set;
470 val &= ~unset;
471
472 ret = ov9740_reg_write(client, reg, val);
473 if (ret < 0) {
474 dev_err(&client->dev,
475 "Read-Modify-[Write] of register 0x%04x failed!\n",
476 reg);
477 return ret;
478 }
479
480 return 0;
481}
482
483static int ov9740_reg_write_array(struct i2c_client *client,
484 const struct ov9740_reg *regarray,
485 int regarraylen)
486{
487 int i;
488 int ret;
489
490 for (i = 0; i < regarraylen; i++) {
491 ret = ov9740_reg_write(client,
492 regarray[i].reg, regarray[i].val);
493 if (ret < 0)
494 return ret;
495 }
496
497 return 0;
498}
499
500
501static int ov9740_s_stream(struct v4l2_subdev *sd, int enable)
502{
503 struct i2c_client *client = v4l2_get_subdevdata(sd);
504 struct ov9740_priv *priv = to_ov9740(sd);
505 int ret;
506
507
508 if (priv->flag_vflip)
509 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x2, 0);
510 else
511 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x2);
512 if (ret < 0)
513 return ret;
514
515 if (priv->flag_hflip)
516 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x1, 0);
517 else
518 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x1);
519 if (ret < 0)
520 return ret;
521
522 if (enable) {
523 dev_dbg(&client->dev, "Enabling Streaming\n");
524
525 ret = ov9740_reg_write(client, OV9740_MODE_SELECT, 0x01);
526
527 } else {
528 dev_dbg(&client->dev, "Disabling Streaming\n");
529
530 ret = ov9740_reg_write(client, OV9740_SOFTWARE_RESET, 0x01);
531 if (!ret)
532
533 ret = ov9740_reg_write(client, OV9740_MODE_SELECT,
534 0x00);
535 }
536
537 priv->current_enable = enable;
538
539 return ret;
540}
541
542
543static void ov9740_res_roundup(u32 *width, u32 *height)
544{
545
546 *width = ALIGN(*width, 4);
547
548
549 if (*width > OV9740_MAX_WIDTH)
550 *width = OV9740_MAX_WIDTH;
551
552 if (*height > OV9740_MAX_HEIGHT)
553 *height = OV9740_MAX_HEIGHT;
554}
555
556
557static int ov9740_set_res(struct i2c_client *client, u32 width, u32 height)
558{
559 u32 x_start;
560 u32 y_start;
561 u32 x_end;
562 u32 y_end;
563 bool scaling = false;
564 u32 scale_input_x;
565 u32 scale_input_y;
566 int ret;
567
568 if ((width != OV9740_MAX_WIDTH) || (height != OV9740_MAX_HEIGHT))
569 scaling = true;
570
571
572
573
574
575
576
577
578 if ((OV9740_MAX_WIDTH * height) > (OV9740_MAX_HEIGHT * width)) {
579 scale_input_x = (OV9740_MAX_HEIGHT * width) / height;
580 scale_input_y = OV9740_MAX_HEIGHT;
581 } else {
582 scale_input_x = OV9740_MAX_WIDTH;
583 scale_input_y = (OV9740_MAX_WIDTH * height) / width;
584 }
585
586
587 x_start = (OV9740_MAX_WIDTH - scale_input_x) / 2;
588 y_start = (OV9740_MAX_HEIGHT - scale_input_y) / 2;
589 x_end = x_start + scale_input_x - 1;
590 y_end = y_start + scale_input_y - 1;
591
592 ret = ov9740_reg_write(client, OV9740_X_ADDR_START_HI, x_start >> 8);
593 if (ret)
594 goto done;
595 ret = ov9740_reg_write(client, OV9740_X_ADDR_START_LO, x_start & 0xff);
596 if (ret)
597 goto done;
598 ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_HI, y_start >> 8);
599 if (ret)
600 goto done;
601 ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_LO, y_start & 0xff);
602 if (ret)
603 goto done;
604
605 ret = ov9740_reg_write(client, OV9740_X_ADDR_END_HI, x_end >> 8);
606 if (ret)
607 goto done;
608 ret = ov9740_reg_write(client, OV9740_X_ADDR_END_LO, x_end & 0xff);
609 if (ret)
610 goto done;
611 ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_HI, y_end >> 8);
612 if (ret)
613 goto done;
614 ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_LO, y_end & 0xff);
615 if (ret)
616 goto done;
617
618 ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_HI, width >> 8);
619 if (ret)
620 goto done;
621 ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_LO, width & 0xff);
622 if (ret)
623 goto done;
624 ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_HI, height >> 8);
625 if (ret)
626 goto done;
627 ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_LO, height & 0xff);
628 if (ret)
629 goto done;
630
631 ret = ov9740_reg_write(client, OV9740_ISP_CTRL1E, scale_input_x >> 8);
632 if (ret)
633 goto done;
634 ret = ov9740_reg_write(client, OV9740_ISP_CTRL1F, scale_input_x & 0xff);
635 if (ret)
636 goto done;
637 ret = ov9740_reg_write(client, OV9740_ISP_CTRL20, scale_input_y >> 8);
638 if (ret)
639 goto done;
640 ret = ov9740_reg_write(client, OV9740_ISP_CTRL21, scale_input_y & 0xff);
641 if (ret)
642 goto done;
643
644 ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_HI,
645 (scale_input_x - width) >> 8);
646 if (ret)
647 goto done;
648 ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_LO,
649 (scale_input_x - width) & 0xff);
650 if (ret)
651 goto done;
652
653 ret = ov9740_reg_write(client, OV9740_ISP_CTRL00, 0xff);
654 if (ret)
655 goto done;
656 ret = ov9740_reg_write(client, OV9740_ISP_CTRL01, 0xef |
657 (scaling << 4));
658 if (ret)
659 goto done;
660 ret = ov9740_reg_write(client, OV9740_ISP_CTRL03, 0xff);
661
662done:
663 return ret;
664}
665
666
667static int ov9740_s_fmt(struct v4l2_subdev *sd,
668 struct v4l2_mbus_framefmt *mf)
669{
670 struct i2c_client *client = v4l2_get_subdevdata(sd);
671 struct ov9740_priv *priv = to_ov9740(sd);
672 int ret;
673
674 ret = ov9740_reg_write_array(client, ov9740_defaults,
675 ARRAY_SIZE(ov9740_defaults));
676 if (ret < 0)
677 return ret;
678
679 ret = ov9740_set_res(client, mf->width, mf->height);
680 if (ret < 0)
681 return ret;
682
683 priv->current_mf = *mf;
684 return ret;
685}
686
687static int ov9740_set_fmt(struct v4l2_subdev *sd,
688 struct v4l2_subdev_pad_config *cfg,
689 struct v4l2_subdev_format *format)
690{
691 struct v4l2_mbus_framefmt *mf = &format->format;
692
693 if (format->pad)
694 return -EINVAL;
695
696 ov9740_res_roundup(&mf->width, &mf->height);
697
698 mf->field = V4L2_FIELD_NONE;
699 mf->code = MEDIA_BUS_FMT_YUYV8_2X8;
700 mf->colorspace = V4L2_COLORSPACE_SRGB;
701
702 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
703 return ov9740_s_fmt(sd, mf);
704 cfg->try_fmt = *mf;
705 return 0;
706}
707
708static int ov9740_enum_mbus_code(struct v4l2_subdev *sd,
709 struct v4l2_subdev_pad_config *cfg,
710 struct v4l2_subdev_mbus_code_enum *code)
711{
712 if (code->pad || code->index >= ARRAY_SIZE(ov9740_codes))
713 return -EINVAL;
714
715 code->code = ov9740_codes[code->index];
716
717 return 0;
718}
719
720static int ov9740_get_selection(struct v4l2_subdev *sd,
721 struct v4l2_subdev_pad_config *cfg,
722 struct v4l2_subdev_selection *sel)
723{
724 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
725 return -EINVAL;
726
727 switch (sel->target) {
728 case V4L2_SEL_TGT_CROP_BOUNDS:
729 case V4L2_SEL_TGT_CROP:
730 sel->r.left = 0;
731 sel->r.top = 0;
732 sel->r.width = OV9740_MAX_WIDTH;
733 sel->r.height = OV9740_MAX_HEIGHT;
734 return 0;
735 default:
736 return -EINVAL;
737 }
738}
739
740
741static int ov9740_s_ctrl(struct v4l2_ctrl *ctrl)
742{
743 struct ov9740_priv *priv =
744 container_of(ctrl->handler, struct ov9740_priv, hdl);
745
746 switch (ctrl->id) {
747 case V4L2_CID_VFLIP:
748 priv->flag_vflip = ctrl->val;
749 break;
750 case V4L2_CID_HFLIP:
751 priv->flag_hflip = ctrl->val;
752 break;
753 default:
754 return -EINVAL;
755 }
756
757 return 0;
758}
759
760static int ov9740_s_power(struct v4l2_subdev *sd, int on)
761{
762 struct i2c_client *client = v4l2_get_subdevdata(sd);
763 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
764 struct ov9740_priv *priv = to_ov9740(sd);
765 int ret;
766
767 if (on) {
768 ret = soc_camera_power_on(&client->dev, ssdd, priv->clk);
769 if (ret < 0)
770 return ret;
771
772 if (priv->current_enable) {
773 ov9740_s_fmt(sd, &priv->current_mf);
774 ov9740_s_stream(sd, 1);
775 }
776 } else {
777 if (priv->current_enable) {
778 ov9740_s_stream(sd, 0);
779 priv->current_enable = true;
780 }
781
782 soc_camera_power_off(&client->dev, ssdd, priv->clk);
783 }
784
785 return 0;
786}
787
788#ifdef CONFIG_VIDEO_ADV_DEBUG
789static int ov9740_get_register(struct v4l2_subdev *sd,
790 struct v4l2_dbg_register *reg)
791{
792 struct i2c_client *client = v4l2_get_subdevdata(sd);
793 int ret;
794 u8 val;
795
796 if (reg->reg & ~0xffff)
797 return -EINVAL;
798
799 reg->size = 2;
800
801 ret = ov9740_reg_read(client, reg->reg, &val);
802 if (ret)
803 return ret;
804
805 reg->val = (__u64)val;
806
807 return ret;
808}
809
810static int ov9740_set_register(struct v4l2_subdev *sd,
811 const struct v4l2_dbg_register *reg)
812{
813 struct i2c_client *client = v4l2_get_subdevdata(sd);
814
815 if (reg->reg & ~0xffff || reg->val & ~0xff)
816 return -EINVAL;
817
818 return ov9740_reg_write(client, reg->reg, reg->val);
819}
820#endif
821
822static int ov9740_video_probe(struct i2c_client *client)
823{
824 struct v4l2_subdev *sd = i2c_get_clientdata(client);
825 struct ov9740_priv *priv = to_ov9740(sd);
826 u8 modelhi, modello;
827 int ret;
828
829 ret = ov9740_s_power(&priv->subdev, 1);
830 if (ret < 0)
831 return ret;
832
833
834
835
836 ret = ov9740_reg_read(client, OV9740_MODEL_ID_HI, &modelhi);
837 if (ret < 0)
838 goto done;
839
840 ret = ov9740_reg_read(client, OV9740_MODEL_ID_LO, &modello);
841 if (ret < 0)
842 goto done;
843
844 priv->model = (modelhi << 8) | modello;
845
846 ret = ov9740_reg_read(client, OV9740_REVISION_NUMBER, &priv->revision);
847 if (ret < 0)
848 goto done;
849
850 ret = ov9740_reg_read(client, OV9740_MANUFACTURER_ID, &priv->manid);
851 if (ret < 0)
852 goto done;
853
854 ret = ov9740_reg_read(client, OV9740_SMIA_VERSION, &priv->smiaver);
855 if (ret < 0)
856 goto done;
857
858 if (priv->model != 0x9740) {
859 ret = -ENODEV;
860 goto done;
861 }
862
863 dev_info(&client->dev, "ov9740 Model ID 0x%04x, Revision 0x%02x, Manufacturer 0x%02x, SMIA Version 0x%02x\n",
864 priv->model, priv->revision, priv->manid, priv->smiaver);
865
866 ret = v4l2_ctrl_handler_setup(&priv->hdl);
867
868done:
869 ov9740_s_power(&priv->subdev, 0);
870 return ret;
871}
872
873
874static int ov9740_g_mbus_config(struct v4l2_subdev *sd,
875 struct v4l2_mbus_config *cfg)
876{
877 struct i2c_client *client = v4l2_get_subdevdata(sd);
878 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
879
880 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
881 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
882 V4L2_MBUS_DATA_ACTIVE_HIGH;
883 cfg->type = V4L2_MBUS_PARALLEL;
884 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
885
886 return 0;
887}
888
889static const struct v4l2_subdev_video_ops ov9740_video_ops = {
890 .s_stream = ov9740_s_stream,
891 .g_mbus_config = ov9740_g_mbus_config,
892};
893
894static const struct v4l2_subdev_core_ops ov9740_core_ops = {
895 .s_power = ov9740_s_power,
896#ifdef CONFIG_VIDEO_ADV_DEBUG
897 .g_register = ov9740_get_register,
898 .s_register = ov9740_set_register,
899#endif
900};
901
902static const struct v4l2_subdev_pad_ops ov9740_pad_ops = {
903 .enum_mbus_code = ov9740_enum_mbus_code,
904 .get_selection = ov9740_get_selection,
905 .set_fmt = ov9740_set_fmt,
906};
907
908static const struct v4l2_subdev_ops ov9740_subdev_ops = {
909 .core = &ov9740_core_ops,
910 .video = &ov9740_video_ops,
911 .pad = &ov9740_pad_ops,
912};
913
914static const struct v4l2_ctrl_ops ov9740_ctrl_ops = {
915 .s_ctrl = ov9740_s_ctrl,
916};
917
918
919
920
921static int ov9740_probe(struct i2c_client *client,
922 const struct i2c_device_id *did)
923{
924 struct ov9740_priv *priv;
925 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
926 int ret;
927
928 if (!ssdd) {
929 dev_err(&client->dev, "Missing platform_data for driver\n");
930 return -EINVAL;
931 }
932
933 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
934 if (!priv)
935 return -ENOMEM;
936
937 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9740_subdev_ops);
938 v4l2_ctrl_handler_init(&priv->hdl, 13);
939 v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
940 V4L2_CID_VFLIP, 0, 1, 1, 0);
941 v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
942 V4L2_CID_HFLIP, 0, 1, 1, 0);
943 priv->subdev.ctrl_handler = &priv->hdl;
944 if (priv->hdl.error)
945 return priv->hdl.error;
946
947 priv->clk = v4l2_clk_get(&client->dev, "mclk");
948 if (IS_ERR(priv->clk)) {
949 ret = PTR_ERR(priv->clk);
950 goto eclkget;
951 }
952
953 ret = ov9740_video_probe(client);
954 if (ret < 0) {
955 v4l2_clk_put(priv->clk);
956eclkget:
957 v4l2_ctrl_handler_free(&priv->hdl);
958 }
959
960 return ret;
961}
962
963static int ov9740_remove(struct i2c_client *client)
964{
965 struct ov9740_priv *priv = i2c_get_clientdata(client);
966
967 v4l2_clk_put(priv->clk);
968 v4l2_device_unregister_subdev(&priv->subdev);
969 v4l2_ctrl_handler_free(&priv->hdl);
970 return 0;
971}
972
973static const struct i2c_device_id ov9740_id[] = {
974 { "ov9740", 0 },
975 { }
976};
977MODULE_DEVICE_TABLE(i2c, ov9740_id);
978
979static struct i2c_driver ov9740_i2c_driver = {
980 .driver = {
981 .name = "ov9740",
982 },
983 .probe = ov9740_probe,
984 .remove = ov9740_remove,
985 .id_table = ov9740_id,
986};
987
988module_i2c_driver(ov9740_i2c_driver);
989
990MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV9740");
991MODULE_AUTHOR("Andrew Chew <achew@nvidia.com>");
992MODULE_LICENSE("GPL v2");
993
