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5
6
7#ifndef _QLGE_H_
8#define _QLGE_H_
9
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/netdevice.h>
13#include <linux/rtnetlink.h>
14#include <linux/if_vlan.h>
15
16
17
18
19#define DRV_NAME "qlge"
20#define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
21#define DRV_VERSION "1.00.00.35"
22
23#define WQ_ADDR_ALIGN 0x3
24
25#define QLGE_VENDOR_ID 0x1077
26#define QLGE_DEVICE_ID_8012 0x8012
27#define QLGE_DEVICE_ID_8000 0x8000
28#define QLGE_MEZZ_SSYS_ID_068 0x0068
29#define QLGE_MEZZ_SSYS_ID_180 0x0180
30#define MAX_CPUS 8
31#define MAX_TX_RINGS MAX_CPUS
32#define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
33
34#define NUM_TX_RING_ENTRIES 256
35#define NUM_RX_RING_ENTRIES 256
36
37
38
39
40#define QLGE_BQ_SHIFT 9
41#define QLGE_BQ_LEN BIT(QLGE_BQ_SHIFT)
42#define QLGE_BQ_SIZE (QLGE_BQ_LEN * sizeof(__le64))
43
44#define DB_PAGE_SIZE 4096
45
46
47
48
49#define MAX_DB_PAGES_PER_BQ(x) \
50 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
51 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
52
53#define RX_RING_SHADOW_SPACE (sizeof(u64) + \
54 MAX_DB_PAGES_PER_BQ(QLGE_BQ_LEN) * sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(QLGE_BQ_LEN) * sizeof(u64))
56#define LARGE_BUFFER_MAX_SIZE 8192
57#define LARGE_BUFFER_MIN_SIZE 2048
58
59#define MAX_CQ 128
60#define DFLT_COALESCE_WAIT 100
61#define MAX_INTER_FRAME_WAIT 10
62#define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT / 2)
63#define UDELAY_COUNT 3
64#define UDELAY_DELAY 100
65
66#define TX_DESC_PER_IOCB 8
67
68#if ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2) > 0
69#define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
70#else
71#define TX_DESC_PER_OAL 0
72#endif
73
74
75
76
77
78
79#define LSW(x) ((u16)(x))
80#define MSW(x) ((u16)((u32)(x) >> 16))
81#define LSD(x) ((u32)((u64)(x)))
82#define MSD(x) ((u32)((((u64)(x)) >> 32)))
83
84
85
86
87#define QLGE_FIT16(value) ((u16)(value))
88
89
90
91
92
93enum {
94 MPI_TEST_FUNC_PORT_CFG = 0x1002,
95 MPI_TEST_FUNC_PRB_CTL = 0x100e,
96 MPI_TEST_FUNC_PRB_EN = 0x18a20000,
97 MPI_TEST_FUNC_RST_STS = 0x100a,
98 MPI_TEST_FUNC_RST_FRC = 0x00000003,
99 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
100 MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0),
101 MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e,
102 MPI_TEST_NIC1_FUNC_SHIFT = 1,
103 MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4),
104 MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0,
105 MPI_TEST_NIC2_FUNC_SHIFT = 5,
106 MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8),
107 MPI_TEST_FC1_FUNCTION_MASK = 0x00000e00,
108 MPI_TEST_FC1_FUNCTION_SHIFT = 9,
109 MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12),
110 MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000,
111 MPI_TEST_FC2_FUNCTION_SHIFT = 13,
112
113 MPI_NIC_READ = 0x00000000,
114 MPI_NIC_REG_BLOCK = 0x00020000,
115 MPI_NIC_FUNCTION_SHIFT = 6,
116};
117
118
119
120
121enum {
122
123 MAILBOX_COUNT = 16,
124 MAILBOX_TIMEOUT = 5,
125
126 PROC_ADDR_RDY = (1 << 31),
127 PROC_ADDR_R = (1 << 30),
128 PROC_ADDR_ERR = (1 << 29),
129 PROC_ADDR_DA = (1 << 28),
130 PROC_ADDR_FUNC0_MBI = 0x00001180,
131 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
132 PROC_ADDR_FUNC0_CTL = 0x000011a1,
133 PROC_ADDR_FUNC2_MBI = 0x00001280,
134 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
135 PROC_ADDR_FUNC2_CTL = 0x000012a1,
136 PROC_ADDR_MPI_RISC = 0x00000000,
137 PROC_ADDR_MDE = 0x00010000,
138 PROC_ADDR_REGBLOCK = 0x00020000,
139 PROC_ADDR_RISC_REG = 0x00030000,
140};
141
142
143
144
145enum {
146 SYS_EFE = (1 << 0),
147 SYS_FAE = (1 << 1),
148 SYS_MDC = (1 << 2),
149 SYS_DST = (1 << 3),
150 SYS_DWC = (1 << 4),
151 SYS_EVW = (1 << 5),
152 SYS_OMP_DLY_MASK = 0x3f000000,
153
154
155
156 SYS_ODI = (1 << 14),
157};
158
159
160
161
162enum {
163 RST_FO_TFO = (1 << 0),
164 RST_FO_RR_MASK = 0x00060000,
165 RST_FO_RR_CQ_CAM = 0x00000000,
166 RST_FO_RR_DROP = 0x00000002,
167 RST_FO_RR_DQ = 0x00000004,
168 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
169 RST_FO_FRB = (1 << 12),
170 RST_FO_MOP = (1 << 13),
171 RST_FO_REG = (1 << 14),
172 RST_FO_FR = (1 << 15),
173};
174
175
176
177
178enum {
179 FSC_DBRST_MASK = 0x00070000,
180 FSC_DBRST_256 = 0x00000000,
181 FSC_DBRST_512 = 0x00000001,
182 FSC_DBRST_768 = 0x00000002,
183 FSC_DBRST_1024 = 0x00000003,
184 FSC_DBL_MASK = 0x00180000,
185 FSC_DBL_DBRST = 0x00000000,
186 FSC_DBL_MAX_PLD = 0x00000008,
187 FSC_DBL_MAX_BRST = 0x00000010,
188 FSC_DBL_128_BYTES = 0x00000018,
189 FSC_EC = (1 << 5),
190 FSC_EPC_MASK = 0x00c00000,
191 FSC_EPC_INBOUND = (1 << 6),
192 FSC_EPC_OUTBOUND = (1 << 7),
193 FSC_VM_PAGESIZE_MASK = 0x07000000,
194 FSC_VM_PAGE_2K = 0x00000100,
195 FSC_VM_PAGE_4K = 0x00000200,
196 FSC_VM_PAGE_8K = 0x00000300,
197 FSC_VM_PAGE_64K = 0x00000600,
198 FSC_SH = (1 << 11),
199 FSC_DSB = (1 << 12),
200 FSC_STE = (1 << 13),
201 FSC_FE = (1 << 15),
202};
203
204
205
206
207enum {
208 CSR_ERR_STS_MASK = 0x0000003f,
209
210
211
212 CSR_RR = (1 << 8),
213 CSR_HRI = (1 << 9),
214 CSR_RP = (1 << 10),
215 CSR_CMD_PARM_SHIFT = 22,
216 CSR_CMD_NOP = 0x00000000,
217 CSR_CMD_SET_RST = 0x10000000,
218 CSR_CMD_CLR_RST = 0x20000000,
219 CSR_CMD_SET_PAUSE = 0x30000000,
220 CSR_CMD_CLR_PAUSE = 0x40000000,
221 CSR_CMD_SET_H2R_INT = 0x50000000,
222 CSR_CMD_CLR_H2R_INT = 0x60000000,
223 CSR_CMD_PAR_EN = 0x70000000,
224 CSR_CMD_SET_BAD_PAR = 0x80000000,
225 CSR_CMD_CLR_BAD_PAR = 0x90000000,
226 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
227};
228
229
230
231
232enum {
233 CFG_LRQ = (1 << 0),
234 CFG_DRQ = (1 << 1),
235 CFG_LR = (1 << 2),
236 CFG_DR = (1 << 3),
237 CFG_LE = (1 << 5),
238 CFG_LCQ = (1 << 6),
239 CFG_DCQ = (1 << 7),
240 CFG_Q_SHIFT = 8,
241 CFG_Q_MASK = 0x7f000000,
242};
243
244
245
246
247enum {
248 STS_FE = (1 << 0),
249 STS_PI = (1 << 1),
250 STS_PL0 = (1 << 2),
251 STS_PL1 = (1 << 3),
252 STS_PI0 = (1 << 4),
253 STS_PI1 = (1 << 5),
254 STS_FUNC_ID_MASK = 0x000000c0,
255 STS_FUNC_ID_SHIFT = 6,
256 STS_F0E = (1 << 8),
257 STS_F1E = (1 << 9),
258 STS_F2E = (1 << 10),
259 STS_F3E = (1 << 11),
260 STS_NFE = (1 << 12),
261};
262
263
264
265
266enum {
267 INTR_EN_INTR_MASK = 0x007f0000,
268 INTR_EN_TYPE_MASK = 0x03000000,
269 INTR_EN_TYPE_ENABLE = 0x00000100,
270 INTR_EN_TYPE_DISABLE = 0x00000200,
271 INTR_EN_TYPE_READ = 0x00000300,
272 INTR_EN_IHD = (1 << 13),
273 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
274 INTR_EN_EI = (1 << 14),
275 INTR_EN_EN = (1 << 15),
276};
277
278
279
280
281enum {
282 INTR_MASK_PI = (1 << 0),
283 INTR_MASK_HL0 = (1 << 1),
284 INTR_MASK_LH0 = (1 << 2),
285 INTR_MASK_HL1 = (1 << 3),
286 INTR_MASK_LH1 = (1 << 4),
287 INTR_MASK_SE = (1 << 5),
288 INTR_MASK_LSC = (1 << 6),
289 INTR_MASK_MC = (1 << 7),
290 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
291};
292
293
294
295
296enum {
297 REV_ID_MASK = 0x0000000f,
298 REV_ID_NICROLL_SHIFT = 0,
299 REV_ID_NICREV_SHIFT = 4,
300 REV_ID_XGROLL_SHIFT = 8,
301 REV_ID_XGREV_SHIFT = 12,
302 REV_ID_CHIPREV_SHIFT = 28,
303};
304
305
306
307
308enum {
309 FRC_ECC_ERR_VW = (1 << 12),
310 FRC_ECC_ERR_VB = (1 << 13),
311 FRC_ECC_ERR_NI = (1 << 14),
312 FRC_ECC_ERR_NO = (1 << 15),
313 FRC_ECC_PFE_SHIFT = 16,
314 FRC_ECC_ERR_DO = (1 << 18),
315 FRC_ECC_P14 = (1 << 19),
316};
317
318
319
320
321enum {
322 ERR_STS_NOF = (1 << 0),
323 ERR_STS_NIF = (1 << 1),
324 ERR_STS_DRP = (1 << 2),
325 ERR_STS_XGP = (1 << 3),
326 ERR_STS_FOU = (1 << 4),
327 ERR_STS_FOC = (1 << 5),
328 ERR_STS_FOF = (1 << 6),
329 ERR_STS_FIU = (1 << 7),
330 ERR_STS_FIC = (1 << 8),
331 ERR_STS_FIF = (1 << 9),
332 ERR_STS_MOF = (1 << 10),
333 ERR_STS_TA = (1 << 11),
334 ERR_STS_MA = (1 << 12),
335 ERR_STS_MPE = (1 << 13),
336 ERR_STS_SCE = (1 << 14),
337 ERR_STS_STE = (1 << 15),
338 ERR_STS_FOW = (1 << 16),
339 ERR_STS_UE = (1 << 17),
340 ERR_STS_MCH = (1 << 26),
341 ERR_STS_LOC_SHIFT = 27,
342};
343
344
345
346
347enum {
348 RAM_DBG_ADDR_FW = (1 << 30),
349 RAM_DBG_ADDR_FR = (1 << 31),
350};
351
352
353
354
355enum {
356
357
358
359
360 SEM_CLEAR = 0,
361 SEM_SET = 1,
362 SEM_FORCE = 3,
363 SEM_XGMAC0_SHIFT = 0,
364 SEM_XGMAC1_SHIFT = 2,
365 SEM_ICB_SHIFT = 4,
366 SEM_MAC_ADDR_SHIFT = 6,
367 SEM_FLASH_SHIFT = 8,
368 SEM_PROBE_SHIFT = 10,
369 SEM_RT_IDX_SHIFT = 12,
370 SEM_PROC_REG_SHIFT = 14,
371 SEM_XGMAC0_MASK = 0x00030000,
372 SEM_XGMAC1_MASK = 0x000c0000,
373 SEM_ICB_MASK = 0x00300000,
374 SEM_MAC_ADDR_MASK = 0x00c00000,
375 SEM_FLASH_MASK = 0x03000000,
376 SEM_PROBE_MASK = 0x0c000000,
377 SEM_RT_IDX_MASK = 0x30000000,
378 SEM_PROC_REG_MASK = 0xc0000000,
379};
380
381
382
383
384enum {
385 XGMAC_ADDR_RDY = (1 << 31),
386 XGMAC_ADDR_R = (1 << 30),
387 XGMAC_ADDR_XME = (1 << 29),
388
389
390 PAUSE_SRC_LO = 0x00000100,
391 PAUSE_SRC_HI = 0x00000104,
392 GLOBAL_CFG = 0x00000108,
393 GLOBAL_CFG_RESET = (1 << 0),
394 GLOBAL_CFG_JUMBO = (1 << 6),
395 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
396 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
397 TX_CFG = 0x0000010c,
398 TX_CFG_RESET = (1 << 0),
399 TX_CFG_EN = (1 << 1),
400 TX_CFG_PREAM = (1 << 2),
401 RX_CFG = 0x00000110,
402 RX_CFG_RESET = (1 << 0),
403 RX_CFG_EN = (1 << 1),
404 RX_CFG_PREAM = (1 << 2),
405 FLOW_CTL = 0x0000011c,
406 PAUSE_OPCODE = 0x00000120,
407 PAUSE_TIMER = 0x00000124,
408 PAUSE_FRM_DEST_LO = 0x00000128,
409 PAUSE_FRM_DEST_HI = 0x0000012c,
410 MAC_TX_PARAMS = 0x00000134,
411 MAC_TX_PARAMS_JUMBO = (1 << 31),
412 MAC_TX_PARAMS_SIZE_SHIFT = 16,
413 MAC_RX_PARAMS = 0x00000138,
414 MAC_SYS_INT = 0x00000144,
415 MAC_SYS_INT_MASK = 0x00000148,
416 MAC_MGMT_INT = 0x0000014c,
417 MAC_MGMT_IN_MASK = 0x00000150,
418 EXT_ARB_MODE = 0x000001fc,
419
420
421 TX_PKTS = 0x00000200,
422 TX_BYTES = 0x00000208,
423 TX_MCAST_PKTS = 0x00000210,
424 TX_BCAST_PKTS = 0x00000218,
425 TX_UCAST_PKTS = 0x00000220,
426 TX_CTL_PKTS = 0x00000228,
427 TX_PAUSE_PKTS = 0x00000230,
428 TX_64_PKT = 0x00000238,
429 TX_65_TO_127_PKT = 0x00000240,
430 TX_128_TO_255_PKT = 0x00000248,
431 TX_256_511_PKT = 0x00000250,
432 TX_512_TO_1023_PKT = 0x00000258,
433 TX_1024_TO_1518_PKT = 0x00000260,
434 TX_1519_TO_MAX_PKT = 0x00000268,
435 TX_UNDERSIZE_PKT = 0x00000270,
436 TX_OVERSIZE_PKT = 0x00000278,
437
438
439 RX_HALF_FULL_DET = 0x000002a0,
440 TX_HALF_FULL_DET = 0x000002a4,
441 RX_OVERFLOW_DET = 0x000002a8,
442 TX_OVERFLOW_DET = 0x000002ac,
443 RX_HALF_FULL_MASK = 0x000002b0,
444 TX_HALF_FULL_MASK = 0x000002b4,
445 RX_OVERFLOW_MASK = 0x000002b8,
446 TX_OVERFLOW_MASK = 0x000002bc,
447 STAT_CNT_CTL = 0x000002c0,
448 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
449 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
450 AUX_RX_HALF_FULL_DET = 0x000002d0,
451 AUX_TX_HALF_FULL_DET = 0x000002d4,
452 AUX_RX_OVERFLOW_DET = 0x000002d8,
453 AUX_TX_OVERFLOW_DET = 0x000002dc,
454 AUX_RX_HALF_FULL_MASK = 0x000002f0,
455 AUX_TX_HALF_FULL_MASK = 0x000002f4,
456 AUX_RX_OVERFLOW_MASK = 0x000002f8,
457 AUX_TX_OVERFLOW_MASK = 0x000002fc,
458
459
460 RX_BYTES = 0x00000300,
461 RX_BYTES_OK = 0x00000308,
462 RX_PKTS = 0x00000310,
463 RX_PKTS_OK = 0x00000318,
464 RX_BCAST_PKTS = 0x00000320,
465 RX_MCAST_PKTS = 0x00000328,
466 RX_UCAST_PKTS = 0x00000330,
467 RX_UNDERSIZE_PKTS = 0x00000338,
468 RX_OVERSIZE_PKTS = 0x00000340,
469 RX_JABBER_PKTS = 0x00000348,
470 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
471 RX_DROP_EVENTS = 0x00000358,
472 RX_FCERR_PKTS = 0x00000360,
473 RX_ALIGN_ERR = 0x00000368,
474 RX_SYMBOL_ERR = 0x00000370,
475 RX_MAC_ERR = 0x00000378,
476 RX_CTL_PKTS = 0x00000380,
477 RX_PAUSE_PKTS = 0x00000388,
478 RX_64_PKTS = 0x00000390,
479 RX_65_TO_127_PKTS = 0x00000398,
480 RX_128_255_PKTS = 0x000003a0,
481 RX_256_511_PKTS = 0x000003a8,
482 RX_512_TO_1023_PKTS = 0x000003b0,
483 RX_1024_TO_1518_PKTS = 0x000003b8,
484 RX_1519_TO_MAX_PKTS = 0x000003c0,
485 RX_LEN_ERR_PKTS = 0x000003c8,
486
487
488 MDIO_TX_DATA = 0x00000400,
489 MDIO_RX_DATA = 0x00000410,
490 MDIO_CMD = 0x00000420,
491 MDIO_PHY_ADDR = 0x00000430,
492 MDIO_PORT = 0x00000440,
493 MDIO_STATUS = 0x00000450,
494
495 XGMAC_REGISTER_END = 0x00000740,
496};
497
498
499
500
501enum {
502 ETS_QUEUE_SHIFT = 29,
503 ETS_REF = (1 << 26),
504 ETS_RS = (1 << 27),
505 ETS_P = (1 << 28),
506 ETS_FC_COS_SHIFT = 23,
507};
508
509
510
511
512enum {
513 FLASH_ADDR_RDY = (1 << 31),
514 FLASH_ADDR_R = (1 << 30),
515 FLASH_ADDR_ERR = (1 << 29),
516};
517
518
519
520
521enum {
522 CQ_STOP_QUEUE_MASK = (0x007f0000),
523 CQ_STOP_TYPE_MASK = (0x03000000),
524 CQ_STOP_TYPE_START = 0x00000100,
525 CQ_STOP_TYPE_STOP = 0x00000200,
526 CQ_STOP_TYPE_READ = 0x00000300,
527 CQ_STOP_EN = (1 << 15),
528};
529
530
531
532
533enum {
534 MAC_ADDR_IDX_SHIFT = 4,
535 MAC_ADDR_TYPE_SHIFT = 16,
536 MAC_ADDR_TYPE_COUNT = 10,
537 MAC_ADDR_TYPE_MASK = 0x000f0000,
538 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
539 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
540 MAC_ADDR_TYPE_VLAN = 0x00020000,
541 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
542 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
543 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
544 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
545 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
546 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
547 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
548 MAC_ADDR_ADR = (1 << 25),
549 MAC_ADDR_RS = (1 << 26),
550 MAC_ADDR_E = (1 << 27),
551 MAC_ADDR_MR = (1 << 30),
552 MAC_ADDR_MW = (1 << 31),
553 MAX_MULTICAST_ENTRIES = 32,
554
555
556
557
558 MAC_ADDR_MAX_CAM_ENTRIES = 512,
559 MAC_ADDR_MAX_CAM_WCOUNT = 3,
560 MAC_ADDR_MAX_MULTICAST_ENTRIES = 32,
561 MAC_ADDR_MAX_MULTICAST_WCOUNT = 2,
562 MAC_ADDR_MAX_VLAN_ENTRIES = 4096,
563 MAC_ADDR_MAX_VLAN_WCOUNT = 1,
564 MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096,
565 MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1,
566 MAC_ADDR_MAX_FC_MAC_ENTRIES = 4,
567 MAC_ADDR_MAX_FC_MAC_WCOUNT = 2,
568 MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8,
569 MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2,
570 MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16,
571 MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1,
572 MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4,
573 MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1,
574 MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4,
575 MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4,
576 MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4,
577 MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1,
578};
579
580
581
582
583enum {
584 SPLT_HDR_EP = (1 << 31),
585};
586
587
588
589
590enum {
591 FC_RCV_CFG_ECT = (1 << 15),
592 FC_RCV_CFG_DFH = (1 << 20),
593 FC_RCV_CFG_DVF = (1 << 21),
594 FC_RCV_CFG_RCE = (1 << 27),
595 FC_RCV_CFG_RFE = (1 << 28),
596 FC_RCV_CFG_TEE = (1 << 29),
597 FC_RCV_CFG_TCE = (1 << 30),
598 FC_RCV_CFG_TFE = (1 << 31),
599};
600
601
602
603
604enum {
605 NIC_RCV_CFG_PPE = (1 << 0),
606 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
607 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
608 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
609 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
610 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
611 NIC_RCV_CFG_RV = (1 << 3),
612 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
613 NIC_RCV_CFG_DFQ_SHIFT = 8,
614 NIC_RCV_CFG_DFQ = 0,
615};
616
617
618
619
620enum {
621 MGMT_RCV_CFG_ARP = (1 << 0),
622 MGMT_RCV_CFG_DHC = (1 << 1),
623 MGMT_RCV_CFG_DHS = (1 << 2),
624 MGMT_RCV_CFG_NP = (1 << 3),
625 MGMT_RCV_CFG_I6N = (1 << 4),
626 MGMT_RCV_CFG_I6R = (1 << 5),
627 MGMT_RCV_CFG_DH6 = (1 << 6),
628 MGMT_RCV_CFG_UD1 = (1 << 7),
629 MGMT_RCV_CFG_UD0 = (1 << 8),
630 MGMT_RCV_CFG_BCT = (1 << 9),
631 MGMT_RCV_CFG_MCT = (1 << 10),
632 MGMT_RCV_CFG_DM = (1 << 11),
633 MGMT_RCV_CFG_RM = (1 << 12),
634 MGMT_RCV_CFG_STL = (1 << 13),
635 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
636 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
637 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
638 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
639 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
640};
641
642
643
644
645enum {
646 RT_IDX_IDX_SHIFT = 8,
647 RT_IDX_TYPE_MASK = 0x000f0000,
648 RT_IDX_TYPE_SHIFT = 16,
649 RT_IDX_TYPE_RT = 0x00000000,
650 RT_IDX_TYPE_RT_INV = 0x00010000,
651 RT_IDX_TYPE_NICQ = 0x00020000,
652 RT_IDX_TYPE_NICQ_INV = 0x00030000,
653 RT_IDX_DST_MASK = 0x00700000,
654 RT_IDX_DST_RSS = 0x00000000,
655 RT_IDX_DST_CAM_Q = 0x00100000,
656 RT_IDX_DST_COS_Q = 0x00200000,
657 RT_IDX_DST_DFLT_Q = 0x00300000,
658 RT_IDX_DST_DEST_Q = 0x00400000,
659 RT_IDX_RS = (1 << 26),
660 RT_IDX_E = (1 << 27),
661 RT_IDX_MR = (1 << 30),
662 RT_IDX_MW = (1 << 31),
663
664
665 RT_IDX_BCAST = (1 << 0),
666 RT_IDX_MCAST = (1 << 1),
667 RT_IDX_MCAST_MATCH = (1 << 2),
668 RT_IDX_MCAST_REG_MATCH = (1 << 3),
669 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
670 RT_IDX_FC_MACH = (1 << 5),
671 RT_IDX_ETH_FCOE = (1 << 6),
672 RT_IDX_CAM_HIT = (1 << 7),
673 RT_IDX_CAM_BIT0 = (1 << 8),
674 RT_IDX_CAM_BIT1 = (1 << 9),
675 RT_IDX_VLAN_TAG = (1 << 10),
676 RT_IDX_VLAN_MATCH = (1 << 11),
677 RT_IDX_VLAN_FILTER = (1 << 12),
678 RT_IDX_ETH_SKIP1 = (1 << 13),
679 RT_IDX_ETH_SKIP2 = (1 << 14),
680 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
681 RT_IDX_802_3 = (1 << 16),
682 RT_IDX_LLDP = (1 << 17),
683 RT_IDX_UNUSED018 = (1 << 18),
684 RT_IDX_UNUSED019 = (1 << 19),
685 RT_IDX_UNUSED20 = (1 << 20),
686 RT_IDX_UNUSED21 = (1 << 21),
687 RT_IDX_ERR = (1 << 22),
688 RT_IDX_VALID = (1 << 23),
689 RT_IDX_TU_CSUM_ERR = (1 << 24),
690 RT_IDX_IP_CSUM_ERR = (1 << 25),
691 RT_IDX_MAC_ERR = (1 << 26),
692 RT_IDX_RSS_TCP6 = (1 << 27),
693 RT_IDX_RSS_TCP4 = (1 << 28),
694 RT_IDX_RSS_IPV6 = (1 << 29),
695 RT_IDX_RSS_IPV4 = (1 << 30),
696 RT_IDX_RSS_MATCH = (1 << 31),
697
698
699 RT_IDX_ALL_ERR_SLOT = 0,
700 RT_IDX_MAC_ERR_SLOT = 0,
701 RT_IDX_IP_CSUM_ERR_SLOT = 1,
702 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
703 RT_IDX_BCAST_SLOT = 3,
704 RT_IDX_MCAST_MATCH_SLOT = 4,
705 RT_IDX_ALLMULTI_SLOT = 5,
706 RT_IDX_UNUSED6_SLOT = 6,
707 RT_IDX_UNUSED7_SLOT = 7,
708 RT_IDX_RSS_MATCH_SLOT = 8,
709 RT_IDX_RSS_IPV4_SLOT = 8,
710 RT_IDX_RSS_IPV6_SLOT = 9,
711 RT_IDX_RSS_TCP4_SLOT = 10,
712 RT_IDX_RSS_TCP6_SLOT = 11,
713 RT_IDX_CAM_HIT_SLOT = 12,
714 RT_IDX_UNUSED013 = 13,
715 RT_IDX_UNUSED014 = 14,
716 RT_IDX_PROMISCUOUS_SLOT = 15,
717 RT_IDX_MAX_RT_SLOTS = 8,
718 RT_IDX_MAX_NIC_SLOTS = 16,
719};
720
721
722
723
724enum {
725 XG_SERDES_ADDR_RDY = (1 << 31),
726 XG_SERDES_ADDR_R = (1 << 30),
727
728 XG_SERDES_ADDR_STS = 0x00001E06,
729 XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005,
730 XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a,
731 XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001,
732
733
734 XG_SERDES_XAUI_AN_START = 0x00000000,
735 XG_SERDES_XAUI_AN_END = 0x00000034,
736 XG_SERDES_XAUI_HSS_PCS_START = 0x00000800,
737 XG_SERDES_XAUI_HSS_PCS_END = 0x0000880,
738 XG_SERDES_XFI_AN_START = 0x00001000,
739 XG_SERDES_XFI_AN_END = 0x00001034,
740 XG_SERDES_XFI_TRAIN_START = 0x10001050,
741 XG_SERDES_XFI_TRAIN_END = 0x1000107C,
742 XG_SERDES_XFI_HSS_PCS_START = 0x00001800,
743 XG_SERDES_XFI_HSS_PCS_END = 0x00001838,
744 XG_SERDES_XFI_HSS_TX_START = 0x00001c00,
745 XG_SERDES_XFI_HSS_TX_END = 0x00001c1f,
746 XG_SERDES_XFI_HSS_RX_START = 0x00001c40,
747 XG_SERDES_XFI_HSS_RX_END = 0x00001c5f,
748 XG_SERDES_XFI_HSS_PLL_START = 0x00001e00,
749 XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f,
750};
751
752
753
754
755enum {
756 PRB_MX_ADDR_ARE = (1 << 16),
757 PRB_MX_ADDR_UP = (1 << 15),
758 PRB_MX_ADDR_SWP = (1 << 14),
759
760
761 PRB_MX_ADDR_MAX_MODS = 21,
762 PRB_MX_ADDR_MOD_SEL_SHIFT = 9,
763 PRB_MX_ADDR_MOD_SEL_TBD = 0,
764 PRB_MX_ADDR_MOD_SEL_IDE1 = 1,
765 PRB_MX_ADDR_MOD_SEL_IDE2 = 2,
766 PRB_MX_ADDR_MOD_SEL_FRB = 3,
767 PRB_MX_ADDR_MOD_SEL_ODE1 = 4,
768 PRB_MX_ADDR_MOD_SEL_ODE2 = 5,
769 PRB_MX_ADDR_MOD_SEL_DA1 = 6,
770 PRB_MX_ADDR_MOD_SEL_DA2 = 7,
771 PRB_MX_ADDR_MOD_SEL_IMP1 = 8,
772 PRB_MX_ADDR_MOD_SEL_IMP2 = 9,
773 PRB_MX_ADDR_MOD_SEL_OMP1 = 10,
774 PRB_MX_ADDR_MOD_SEL_OMP2 = 11,
775 PRB_MX_ADDR_MOD_SEL_ORS1 = 12,
776 PRB_MX_ADDR_MOD_SEL_ORS2 = 13,
777 PRB_MX_ADDR_MOD_SEL_REG = 14,
778 PRB_MX_ADDR_MOD_SEL_MAC1 = 16,
779 PRB_MX_ADDR_MOD_SEL_MAC2 = 17,
780 PRB_MX_ADDR_MOD_SEL_VQM1 = 18,
781 PRB_MX_ADDR_MOD_SEL_VQM2 = 19,
782 PRB_MX_ADDR_MOD_SEL_MOP = 20,
783
784
785
786 PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7,
787 PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1,
788 PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309,
789 PRB_MX_ADDR_VALID_FC_MOD = 0x00003001,
790 PRB_MX_ADDR_VALID_TOTAL = 34,
791
792
793 PRB_MX_ADDR_CLOCK_SHIFT = 6,
794 PRB_MX_ADDR_SYS_CLOCK = 0,
795 PRB_MX_ADDR_PCI_CLOCK = 2,
796 PRB_MX_ADDR_FC_CLOCK = 5,
797 PRB_MX_ADDR_XGM_CLOCK = 6,
798
799 PRB_MX_ADDR_MAX_MUX = 64,
800};
801
802
803
804
805enum {
806 PROC_ADDR = 0,
807 PROC_DATA = 0x04,
808 SYS = 0x08,
809 RST_FO = 0x0c,
810 FSC = 0x10,
811 CSR = 0x14,
812 LED = 0x18,
813 ICB_RID = 0x1c,
814 ICB_L = 0x20,
815 ICB_H = 0x24,
816 CFG = 0x28,
817 BIOS_ADDR = 0x2c,
818 STS = 0x30,
819 INTR_EN = 0x34,
820 INTR_MASK = 0x38,
821 ISR1 = 0x3c,
822 ISR2 = 0x40,
823 ISR3 = 0x44,
824 ISR4 = 0x48,
825 REV_ID = 0x4c,
826 FRC_ECC_ERR = 0x50,
827 ERR_STS = 0x54,
828 RAM_DBG_ADDR = 0x58,
829 RAM_DBG_DATA = 0x5c,
830 ECC_ERR_CNT = 0x60,
831 SEM = 0x64,
832 GPIO_1 = 0x68,
833 GPIO_2 = 0x6c,
834 GPIO_3 = 0x70,
835 RSVD2 = 0x74,
836 XGMAC_ADDR = 0x78,
837 XGMAC_DATA = 0x7c,
838 NIC_ETS = 0x80,
839 CNA_ETS = 0x84,
840 FLASH_ADDR = 0x88,
841 FLASH_DATA = 0x8c,
842 CQ_STOP = 0x90,
843 PAGE_TBL_RID = 0x94,
844 WQ_PAGE_TBL_LO = 0x98,
845 WQ_PAGE_TBL_HI = 0x9c,
846 CQ_PAGE_TBL_LO = 0xa0,
847 CQ_PAGE_TBL_HI = 0xa4,
848 MAC_ADDR_IDX = 0xa8,
849 MAC_ADDR_DATA = 0xac,
850 COS_DFLT_CQ1 = 0xb0,
851 COS_DFLT_CQ2 = 0xb4,
852 ETYPE_SKIP1 = 0xb8,
853 ETYPE_SKIP2 = 0xbc,
854 SPLT_HDR = 0xc0,
855 FC_PAUSE_THRES = 0xc4,
856 NIC_PAUSE_THRES = 0xc8,
857 FC_ETHERTYPE = 0xcc,
858 FC_RCV_CFG = 0xd0,
859 NIC_RCV_CFG = 0xd4,
860 FC_COS_TAGS = 0xd8,
861 NIC_COS_TAGS = 0xdc,
862 MGMT_RCV_CFG = 0xe0,
863 RT_IDX = 0xe4,
864 RT_DATA = 0xe8,
865 RSVD7 = 0xec,
866 XG_SERDES_ADDR = 0xf0,
867 XG_SERDES_DATA = 0xf4,
868 PRB_MX_ADDR = 0xf8,
869 PRB_MX_DATA = 0xfc,
870};
871
872#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
873#define SMALL_BUFFER_SIZE 256
874#define SMALL_BUF_MAP_SIZE SMALL_BUFFER_SIZE
875#define SPLT_SETTING FSC_DBRST_1024
876#define SPLT_LEN 0
877#define QLGE_SB_PAD 0
878#else
879#define SMALL_BUFFER_SIZE 512
880#define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
881#define SPLT_SETTING FSC_SH
882#define SPLT_LEN (SPLT_HDR_EP | \
883 min(SMALL_BUF_MAP_SIZE, 1023))
884#define QLGE_SB_PAD 32
885#endif
886
887
888
889
890enum {
891 CAM_OUT_ROUTE_FC = 0,
892 CAM_OUT_ROUTE_NIC = 1,
893 CAM_OUT_FUNC_SHIFT = 2,
894 CAM_OUT_RV = (1 << 4),
895 CAM_OUT_SH = (1 << 15),
896 CAM_OUT_CQ_ID_SHIFT = 5,
897};
898
899
900
901
902enum {
903
904 AEN_SYS_ERR = 0x00008002,
905 AEN_LINK_UP = 0x00008011,
906 AEN_LINK_DOWN = 0x00008012,
907 AEN_IDC_CMPLT = 0x00008100,
908 AEN_IDC_REQ = 0x00008101,
909 AEN_IDC_EXT = 0x00008102,
910 AEN_DCBX_CHG = 0x00008110,
911 AEN_AEN_LOST = 0x00008120,
912 AEN_AEN_SFP_IN = 0x00008130,
913 AEN_AEN_SFP_OUT = 0x00008131,
914 AEN_FW_INIT_DONE = 0x00008400,
915 AEN_FW_INIT_FAIL = 0x00008401,
916
917
918 MB_CMD_NOP = 0x00000000,
919 MB_CMD_EX_FW = 0x00000002,
920 MB_CMD_MB_TEST = 0x00000006,
921 MB_CMD_CSUM_TEST = 0x00000007,
922 MB_CMD_ABOUT_FW = 0x00000008,
923 MB_CMD_COPY_RISC_RAM = 0x0000000a,
924 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
925 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
926 MB_CMD_WRITE_RAM = 0x0000000d,
927 MB_CMD_INIT_RISC_RAM = 0x0000000e,
928 MB_CMD_READ_RAM = 0x0000000f,
929 MB_CMD_STOP_FW = 0x00000014,
930 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
931 MB_CMD_WRITE_SFP = 0x00000030,
932 MB_CMD_READ_SFP = 0x00000031,
933 MB_CMD_INIT_FW = 0x00000060,
934 MB_CMD_GET_IFCB = 0x00000061,
935 MB_CMD_GET_FW_STATE = 0x00000069,
936 MB_CMD_IDC_REQ = 0x00000100,
937 MB_CMD_IDC_ACK = 0x00000101,
938 MB_CMD_SET_WOL_MODE = 0x00000110,
939 MB_WOL_DISABLE = 0,
940 MB_WOL_MAGIC_PKT = (1 << 1),
941 MB_WOL_FLTR = (1 << 2),
942 MB_WOL_UCAST = (1 << 3),
943 MB_WOL_MCAST = (1 << 4),
944 MB_WOL_BCAST = (1 << 5),
945 MB_WOL_LINK_UP = (1 << 6),
946 MB_WOL_LINK_DOWN = (1 << 7),
947 MB_WOL_MODE_ON = (1 << 16),
948 MB_CMD_SET_WOL_FLTR = 0x00000111,
949 MB_CMD_CLEAR_WOL_FLTR = 0x00000112,
950 MB_CMD_SET_WOL_MAGIC = 0x00000113,
951 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,
952 MB_CMD_SET_WOL_IMMED = 0x00000115,
953 MB_CMD_PORT_RESET = 0x00000120,
954 MB_CMD_SET_PORT_CFG = 0x00000122,
955 MB_CMD_GET_PORT_CFG = 0x00000123,
956 MB_CMD_GET_LINK_STS = 0x00000124,
957 MB_CMD_SET_LED_CFG = 0x00000125,
958 QL_LED_BLINK = 0x03e803e8,
959 MB_CMD_GET_LED_CFG = 0x00000126,
960 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160,
961 MB_SET_MPI_TFK_STOP = (1 << 0),
962 MB_SET_MPI_TFK_RESUME = (1 << 1),
963 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161,
964 MB_GET_MPI_TFK_STOPPED = (1 << 0),
965 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
966
967
968
969
970 MB_CMD_IOP_NONE = 0x0000,
971 MB_CMD_IOP_PREP_UPDATE_MPI = 0x0001,
972 MB_CMD_IOP_COMP_UPDATE_MPI = 0x0002,
973 MB_CMD_IOP_PREP_LINK_DOWN = 0x0010,
974 MB_CMD_IOP_DVR_START = 0x0100,
975 MB_CMD_IOP_FLASH_ACC = 0x0101,
976 MB_CMD_IOP_RESTART_MPI = 0x0102,
977 MB_CMD_IOP_CORE_DUMP_MPI = 0x0103,
978
979
980 MB_CMD_STS_GOOD = 0x00004000,
981 MB_CMD_STS_INTRMDT = 0x00001000,
982 MB_CMD_STS_INVLD_CMD = 0x00004001,
983 MB_CMD_STS_XFC_ERR = 0x00004002,
984 MB_CMD_STS_CSUM_ERR = 0x00004003,
985 MB_CMD_STS_ERR = 0x00004005,
986 MB_CMD_STS_PARAM_ERR = 0x00004006,
987};
988
989struct mbox_params {
990 u32 mbox_in[MAILBOX_COUNT];
991 u32 mbox_out[MAILBOX_COUNT];
992 int in_count;
993 int out_count;
994};
995
996struct flash_params_8012 {
997 u8 dev_id_str[4];
998 __le16 size;
999 __le16 csum;
1000 __le16 ver;
1001 __le16 sub_dev_id;
1002 u8 mac_addr[6];
1003 __le16 res;
1004};
1005
1006
1007
1008
1009#define FUNC0_FLASH_OFFSET 0x140200
1010#define FUNC1_FLASH_OFFSET 0x140600
1011
1012
1013struct flash_params_8000 {
1014 u8 dev_id_str[4];
1015 __le16 ver;
1016 __le16 size;
1017 __le16 csum;
1018 __le16 reserved0;
1019 __le16 total_size;
1020 __le16 entry_count;
1021 u8 data_type0;
1022 u8 data_size0;
1023 u8 mac_addr[6];
1024 u8 data_type1;
1025 u8 data_size1;
1026 u8 mac_addr1[6];
1027 u8 data_type2;
1028 u8 data_size2;
1029 __le16 vlan_id;
1030 u8 data_type3;
1031 u8 data_size3;
1032 __le16 last;
1033 u8 reserved1[464];
1034 __le16 subsys_ven_id;
1035 __le16 subsys_dev_id;
1036 u8 reserved2[4];
1037};
1038
1039union flash_params {
1040 struct flash_params_8012 flash_params_8012;
1041 struct flash_params_8000 flash_params_8000;
1042};
1043
1044
1045
1046
1047struct rx_doorbell_context {
1048 u32 cnsmr_idx;
1049 u32 valid;
1050 u32 reserved[4];
1051 u32 lbq_prod_idx;
1052 u32 sbq_prod_idx;
1053};
1054
1055
1056
1057
1058struct tx_doorbell_context {
1059 u32 prod_idx;
1060 u32 valid;
1061 u32 reserved[4];
1062 u32 lbq_prod_idx;
1063 u32 sbq_prod_idx;
1064};
1065
1066
1067struct tx_buf_desc {
1068 __le64 addr;
1069 __le32 len;
1070#define TX_DESC_LEN_MASK 0x000fffff
1071#define TX_DESC_C 0x40000000
1072#define TX_DESC_E 0x80000000
1073} __packed;
1074
1075
1076
1077
1078
1079#define OPCODE_OB_MAC_IOCB 0x01
1080#define OPCODE_OB_MAC_TSO_IOCB 0x02
1081#define OPCODE_IB_MAC_IOCB 0x20
1082#define OPCODE_IB_MPI_IOCB 0x21
1083#define OPCODE_IB_AE_IOCB 0x3f
1084
1085struct ob_mac_iocb_req {
1086 u8 opcode;
1087 u8 flags1;
1088#define OB_MAC_IOCB_REQ_OI 0x01
1089#define OB_MAC_IOCB_REQ_I 0x02
1090#define OB_MAC_IOCB_REQ_D 0x08
1091#define OB_MAC_IOCB_REQ_F 0x10
1092 u8 flags2;
1093 u8 flags3;
1094#define OB_MAC_IOCB_DFP 0x02
1095#define OB_MAC_IOCB_V 0x04
1096 __le32 reserved1[2];
1097 __le16 frame_len;
1098#define OB_MAC_IOCB_LEN_MASK 0x3ffff
1099 __le16 reserved2;
1100 u32 tid;
1101 u32 txq_idx;
1102 __le32 reserved3;
1103 __le16 vlan_tci;
1104 __le16 reserved4;
1105 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1106} __packed;
1107
1108struct ob_mac_iocb_rsp {
1109 u8 opcode;
1110 u8 flags1;
1111#define OB_MAC_IOCB_RSP_OI 0x01
1112#define OB_MAC_IOCB_RSP_I 0x02
1113#define OB_MAC_IOCB_RSP_E 0x08
1114#define OB_MAC_IOCB_RSP_S 0x10
1115#define OB_MAC_IOCB_RSP_L 0x20
1116#define OB_MAC_IOCB_RSP_P 0x40
1117 u8 flags2;
1118 u8 flags3;
1119#define OB_MAC_IOCB_RSP_B 0x80
1120 u32 tid;
1121 u32 txq_idx;
1122 __le32 reserved[13];
1123} __packed;
1124
1125struct ob_mac_tso_iocb_req {
1126 u8 opcode;
1127 u8 flags1;
1128#define OB_MAC_TSO_IOCB_OI 0x01
1129#define OB_MAC_TSO_IOCB_I 0x02
1130#define OB_MAC_TSO_IOCB_D 0x08
1131#define OB_MAC_TSO_IOCB_IP4 0x40
1132#define OB_MAC_TSO_IOCB_IP6 0x80
1133 u8 flags2;
1134#define OB_MAC_TSO_IOCB_LSO 0x20
1135#define OB_MAC_TSO_IOCB_UC 0x40
1136#define OB_MAC_TSO_IOCB_TC 0x80
1137 u8 flags3;
1138#define OB_MAC_TSO_IOCB_IC 0x01
1139#define OB_MAC_TSO_IOCB_DFP 0x02
1140#define OB_MAC_TSO_IOCB_V 0x04
1141 __le32 reserved1[2];
1142 __le32 frame_len;
1143 u32 tid;
1144 u32 txq_idx;
1145 __le16 total_hdrs_len;
1146 __le16 net_trans_offset;
1147#define OB_MAC_TRANSPORT_HDR_SHIFT 6
1148 __le16 vlan_tci;
1149 __le16 mss;
1150 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1151} __packed;
1152
1153struct ob_mac_tso_iocb_rsp {
1154 u8 opcode;
1155 u8 flags1;
1156#define OB_MAC_TSO_IOCB_RSP_OI 0x01
1157#define OB_MAC_TSO_IOCB_RSP_I 0x02
1158#define OB_MAC_TSO_IOCB_RSP_E 0x08
1159#define OB_MAC_TSO_IOCB_RSP_S 0x10
1160#define OB_MAC_TSO_IOCB_RSP_L 0x20
1161#define OB_MAC_TSO_IOCB_RSP_P 0x40
1162 u8 flags2;
1163 u8 flags3;
1164#define OB_MAC_TSO_IOCB_RSP_B 0x8000
1165 u32 tid;
1166 u32 txq_idx;
1167 __le32 reserved2[13];
1168} __packed;
1169
1170struct ib_mac_iocb_rsp {
1171 u8 opcode;
1172 u8 flags1;
1173#define IB_MAC_IOCB_RSP_OI 0x01
1174#define IB_MAC_IOCB_RSP_I 0x02
1175#define IB_MAC_CSUM_ERR_MASK 0x1c
1176#define IB_MAC_IOCB_RSP_TE 0x04
1177#define IB_MAC_IOCB_RSP_NU 0x08
1178#define IB_MAC_IOCB_RSP_IE 0x10
1179#define IB_MAC_IOCB_RSP_M_MASK 0x60
1180#define IB_MAC_IOCB_RSP_M_NONE 0x00
1181#define IB_MAC_IOCB_RSP_M_HASH 0x20
1182#define IB_MAC_IOCB_RSP_M_REG 0x40
1183#define IB_MAC_IOCB_RSP_M_PROM 0x60
1184#define IB_MAC_IOCB_RSP_B 0x80
1185 u8 flags2;
1186#define IB_MAC_IOCB_RSP_P 0x01
1187#define IB_MAC_IOCB_RSP_V 0x02
1188#define IB_MAC_IOCB_RSP_ERR_MASK 0x1c
1189#define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1190#define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1191#define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1192#define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1193#define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1194#define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1195#define IB_MAC_IOCB_RSP_U 0x20
1196#define IB_MAC_IOCB_RSP_T 0x40
1197#define IB_MAC_IOCB_RSP_FO 0x80
1198 u8 flags3;
1199#define IB_MAC_IOCB_RSP_RSS_MASK 0x07
1200#define IB_MAC_IOCB_RSP_M_NONE 0x00
1201#define IB_MAC_IOCB_RSP_M_IPV4 0x04
1202#define IB_MAC_IOCB_RSP_M_IPV6 0x02
1203#define IB_MAC_IOCB_RSP_M_TCP_V4 0x05
1204#define IB_MAC_IOCB_RSP_M_TCP_V6 0x03
1205#define IB_MAC_IOCB_RSP_V4 0x08
1206#define IB_MAC_IOCB_RSP_V6 0x10
1207#define IB_MAC_IOCB_RSP_IH 0x20
1208#define IB_MAC_IOCB_RSP_DS 0x40
1209#define IB_MAC_IOCB_RSP_DL 0x80
1210 __le32 data_len;
1211 __le64 data_addr;
1212 __le32 rss;
1213 __le16 vlan_id;
1214#define IB_MAC_IOCB_RSP_C 0x1000
1215#define IB_MAC_IOCB_RSP_COS_SHIFT 12
1216#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1217
1218 __le16 reserved1;
1219 __le32 reserved2[6];
1220 u8 reserved3[3];
1221 u8 flags4;
1222#define IB_MAC_IOCB_RSP_HV 0x20
1223#define IB_MAC_IOCB_RSP_HS 0x40
1224#define IB_MAC_IOCB_RSP_HL 0x80
1225 __le32 hdr_len;
1226 __le64 hdr_addr;
1227} __packed;
1228
1229struct ib_ae_iocb_rsp {
1230 u8 opcode;
1231 u8 flags1;
1232#define IB_AE_IOCB_RSP_OI 0x01
1233#define IB_AE_IOCB_RSP_I 0x02
1234 u8 event;
1235#define LINK_UP_EVENT 0x00
1236#define LINK_DOWN_EVENT 0x01
1237#define CAM_LOOKUP_ERR_EVENT 0x06
1238#define SOFT_ECC_ERROR_EVENT 0x07
1239#define MGMT_ERR_EVENT 0x08
1240#define TEN_GIG_MAC_EVENT 0x09
1241#define GPI0_H2L_EVENT 0x10
1242#define GPI0_L2H_EVENT 0x20
1243#define GPI1_H2L_EVENT 0x11
1244#define GPI1_L2H_EVENT 0x21
1245#define PCI_ERR_ANON_BUF_RD 0x40
1246 u8 q_id;
1247 __le32 reserved[15];
1248} __packed;
1249
1250
1251
1252
1253
1254struct ql_net_rsp_iocb {
1255 u8 opcode;
1256 u8 flags0;
1257 __le16 length;
1258 __le32 tid;
1259 __le32 reserved[14];
1260} __packed;
1261
1262struct net_req_iocb {
1263 u8 opcode;
1264 u8 flags0;
1265 __le16 flags1;
1266 __le32 tid;
1267 __le32 reserved1[30];
1268} __packed;
1269
1270
1271
1272
1273
1274
1275struct wqicb {
1276 __le16 len;
1277#define Q_LEN_V (1 << 4)
1278#define Q_LEN_CPP_CONT 0x0000
1279#define Q_LEN_CPP_16 0x0001
1280#define Q_LEN_CPP_32 0x0002
1281#define Q_LEN_CPP_64 0x0003
1282#define Q_LEN_CPP_512 0x0006
1283 __le16 flags;
1284#define Q_PRI_SHIFT 1
1285#define Q_FLAGS_LC 0x1000
1286#define Q_FLAGS_LB 0x2000
1287#define Q_FLAGS_LI 0x4000
1288#define Q_FLAGS_LO 0x8000
1289 __le16 cq_id_rss;
1290#define Q_CQ_ID_RSS_RV 0x8000
1291 __le16 rid;
1292 __le64 addr;
1293 __le64 cnsmr_idx_addr;
1294} __packed;
1295
1296
1297
1298
1299
1300
1301struct cqicb {
1302 u8 msix_vect;
1303 u8 reserved1;
1304 u8 reserved2;
1305 u8 flags;
1306#define FLAGS_LV 0x08
1307#define FLAGS_LS 0x10
1308#define FLAGS_LL 0x20
1309#define FLAGS_LI 0x40
1310#define FLAGS_LC 0x80
1311 __le16 len;
1312#define LEN_V (1 << 4)
1313#define LEN_CPP_CONT 0x0000
1314#define LEN_CPP_32 0x0001
1315#define LEN_CPP_64 0x0002
1316#define LEN_CPP_128 0x0003
1317 __le16 rid;
1318 __le64 addr;
1319 __le64 prod_idx_addr;
1320 __le16 pkt_delay;
1321 __le16 irq_delay;
1322 __le64 lbq_addr;
1323 __le16 lbq_buf_size;
1324 __le16 lbq_len;
1325 __le64 sbq_addr;
1326 __le16 sbq_buf_size;
1327 __le16 sbq_len;
1328} __packed;
1329
1330struct ricb {
1331 u8 base_cq;
1332#define RSS_L4K 0x80
1333 u8 flags;
1334#define RSS_L6K 0x01
1335#define RSS_LI 0x02
1336#define RSS_LB 0x04
1337#define RSS_LM 0x08
1338#define RSS_RI4 0x10
1339#define RSS_RT4 0x20
1340#define RSS_RI6 0x40
1341#define RSS_RT6 0x80
1342 __le16 mask;
1343 u8 hash_cq_id[1024];
1344 __le32 ipv6_hash_key[10];
1345 __le32 ipv4_hash_key[4];
1346} __packed;
1347
1348
1349
1350struct oal {
1351 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1352};
1353
1354struct map_list {
1355 DEFINE_DMA_UNMAP_ADDR(mapaddr);
1356 DEFINE_DMA_UNMAP_LEN(maplen);
1357};
1358
1359struct tx_ring_desc {
1360 struct sk_buff *skb;
1361 struct ob_mac_iocb_req *queue_entry;
1362 u32 index;
1363 struct oal oal;
1364 struct map_list map[MAX_SKB_FRAGS + 2];
1365 int map_cnt;
1366 struct tx_ring_desc *next;
1367};
1368
1369#define QL_TXQ_IDX(qdev, skb) (smp_processor_id() % (qdev->tx_ring_count))
1370
1371struct tx_ring {
1372
1373
1374
1375 struct wqicb wqicb;
1376 void *wq_base;
1377 dma_addr_t wq_base_dma;
1378 __le32 *cnsmr_idx_sh_reg;
1379 dma_addr_t cnsmr_idx_sh_reg_dma;
1380 u32 wq_size;
1381 u32 wq_len;
1382 void __iomem *prod_idx_db_reg;
1383 void __iomem *valid_db_reg;
1384 u16 prod_idx;
1385 u16 cq_id;
1386 u8 wq_id;
1387 u8 reserved1[3];
1388 struct tx_ring_desc *q;
1389 spinlock_t lock;
1390 atomic_t tx_count;
1391 struct delayed_work tx_work;
1392 struct ql_adapter *qdev;
1393 u64 tx_packets;
1394 u64 tx_bytes;
1395 u64 tx_errors;
1396};
1397
1398struct qlge_page_chunk {
1399 struct page *page;
1400 void *va;
1401 unsigned int offset;
1402};
1403
1404struct qlge_bq_desc {
1405 union {
1406
1407 struct qlge_page_chunk pg_chunk;
1408
1409 struct sk_buff *skb;
1410 } p;
1411 dma_addr_t dma_addr;
1412
1413 __le64 *buf_ptr;
1414 u32 index;
1415};
1416
1417
1418struct qlge_bq {
1419 __le64 *base;
1420 dma_addr_t base_dma;
1421 __le64 *base_indirect;
1422 dma_addr_t base_indirect_dma;
1423 struct qlge_bq_desc *queue;
1424
1425
1426
1427 void __iomem *prod_idx_db_reg;
1428
1429 u16 next_to_use;
1430
1431 u16 next_to_clean;
1432 enum {
1433 QLGE_SB,
1434 QLGE_LB,
1435 } type;
1436};
1437
1438#define QLGE_BQ_CONTAINER(bq) \
1439({ \
1440 typeof(bq) _bq = bq; \
1441 (struct rx_ring *)((char *)_bq - (_bq->type == QLGE_SB ? \
1442 offsetof(struct rx_ring, sbq) : \
1443 offsetof(struct rx_ring, lbq))); \
1444})
1445
1446
1447
1448
1449#define QLGE_BQ_ALIGN(index) ALIGN_DOWN(index, 16)
1450
1451#define QLGE_BQ_WRAP(index) ((index) & (QLGE_BQ_LEN - 1))
1452
1453#define QLGE_BQ_HW_OWNED(bq) \
1454({ \
1455 typeof(bq) _bq = bq; \
1456 QLGE_BQ_WRAP(QLGE_BQ_ALIGN((_bq)->next_to_use) - \
1457 (_bq)->next_to_clean); \
1458})
1459
1460struct rx_ring {
1461 struct cqicb cqicb;
1462
1463
1464 void *cq_base;
1465 dma_addr_t cq_base_dma;
1466 u32 cq_size;
1467 u32 cq_len;
1468 u16 cq_id;
1469 __le32 *prod_idx_sh_reg;
1470 dma_addr_t prod_idx_sh_reg_dma;
1471 void __iomem *cnsmr_idx_db_reg;
1472 u32 cnsmr_idx;
1473 struct ql_net_rsp_iocb *curr_entry;
1474 void __iomem *valid_db_reg;
1475
1476
1477 struct qlge_bq lbq;
1478 struct qlge_page_chunk master_chunk;
1479 dma_addr_t chunk_dma_addr;
1480
1481
1482 struct qlge_bq sbq;
1483
1484
1485 u32 irq;
1486 u32 cpu;
1487 struct delayed_work refill_work;
1488 char name[IFNAMSIZ + 5];
1489 struct napi_struct napi;
1490 u8 reserved;
1491 struct ql_adapter *qdev;
1492 u64 rx_packets;
1493 u64 rx_multicast;
1494 u64 rx_bytes;
1495 u64 rx_dropped;
1496 u64 rx_errors;
1497};
1498
1499
1500
1501
1502struct hash_id {
1503 u8 value[4];
1504};
1505
1506struct nic_stats {
1507
1508
1509
1510
1511 u64 tx_pkts;
1512 u64 tx_bytes;
1513 u64 tx_mcast_pkts;
1514 u64 tx_bcast_pkts;
1515 u64 tx_ucast_pkts;
1516 u64 tx_ctl_pkts;
1517 u64 tx_pause_pkts;
1518 u64 tx_64_pkt;
1519 u64 tx_65_to_127_pkt;
1520 u64 tx_128_to_255_pkt;
1521 u64 tx_256_511_pkt;
1522 u64 tx_512_to_1023_pkt;
1523 u64 tx_1024_to_1518_pkt;
1524 u64 tx_1519_to_max_pkt;
1525 u64 tx_undersize_pkt;
1526 u64 tx_oversize_pkt;
1527
1528
1529
1530
1531
1532 u64 rx_bytes;
1533 u64 rx_bytes_ok;
1534 u64 rx_pkts;
1535 u64 rx_pkts_ok;
1536 u64 rx_bcast_pkts;
1537 u64 rx_mcast_pkts;
1538 u64 rx_ucast_pkts;
1539 u64 rx_undersize_pkts;
1540 u64 rx_oversize_pkts;
1541 u64 rx_jabber_pkts;
1542 u64 rx_undersize_fcerr_pkts;
1543 u64 rx_drop_events;
1544 u64 rx_fcerr_pkts;
1545 u64 rx_align_err;
1546 u64 rx_symbol_err;
1547 u64 rx_mac_err;
1548 u64 rx_ctl_pkts;
1549 u64 rx_pause_pkts;
1550 u64 rx_64_pkts;
1551 u64 rx_65_to_127_pkts;
1552 u64 rx_128_255_pkts;
1553 u64 rx_256_511_pkts;
1554 u64 rx_512_to_1023_pkts;
1555 u64 rx_1024_to_1518_pkts;
1556 u64 rx_1519_to_max_pkts;
1557 u64 rx_len_err_pkts;
1558
1559 u64 rx_code_err;
1560 u64 rx_oversize_err;
1561 u64 rx_undersize_err;
1562 u64 rx_preamble_err;
1563 u64 rx_frame_len_err;
1564 u64 rx_crc_err;
1565 u64 rx_err_count;
1566
1567
1568
1569
1570 u64 tx_cbfc_pause_frames0;
1571 u64 tx_cbfc_pause_frames1;
1572 u64 tx_cbfc_pause_frames2;
1573 u64 tx_cbfc_pause_frames3;
1574 u64 tx_cbfc_pause_frames4;
1575 u64 tx_cbfc_pause_frames5;
1576 u64 tx_cbfc_pause_frames6;
1577 u64 tx_cbfc_pause_frames7;
1578 u64 rx_cbfc_pause_frames0;
1579 u64 rx_cbfc_pause_frames1;
1580 u64 rx_cbfc_pause_frames2;
1581 u64 rx_cbfc_pause_frames3;
1582 u64 rx_cbfc_pause_frames4;
1583 u64 rx_cbfc_pause_frames5;
1584 u64 rx_cbfc_pause_frames6;
1585 u64 rx_cbfc_pause_frames7;
1586 u64 rx_nic_fifo_drop;
1587};
1588
1589
1590enum {
1591 MPI_CORE_REGS_ADDR = 0x00030000,
1592 MPI_CORE_REGS_CNT = 127,
1593 MPI_CORE_SH_REGS_CNT = 16,
1594 TEST_REGS_ADDR = 0x00001000,
1595 TEST_REGS_CNT = 23,
1596 RMII_REGS_ADDR = 0x00001040,
1597 RMII_REGS_CNT = 64,
1598 FCMAC1_REGS_ADDR = 0x00001080,
1599 FCMAC2_REGS_ADDR = 0x000010c0,
1600 FCMAC_REGS_CNT = 64,
1601 FC1_MBX_REGS_ADDR = 0x00001100,
1602 FC2_MBX_REGS_ADDR = 0x00001240,
1603 FC_MBX_REGS_CNT = 64,
1604 IDE_REGS_ADDR = 0x00001140,
1605 IDE_REGS_CNT = 64,
1606 NIC1_MBX_REGS_ADDR = 0x00001180,
1607 NIC2_MBX_REGS_ADDR = 0x00001280,
1608 NIC_MBX_REGS_CNT = 64,
1609 SMBUS_REGS_ADDR = 0x00001200,
1610 SMBUS_REGS_CNT = 64,
1611 I2C_REGS_ADDR = 0x00001fc0,
1612 I2C_REGS_CNT = 64,
1613 MEMC_REGS_ADDR = 0x00003000,
1614 MEMC_REGS_CNT = 256,
1615 PBUS_REGS_ADDR = 0x00007c00,
1616 PBUS_REGS_CNT = 256,
1617 MDE_REGS_ADDR = 0x00010000,
1618 MDE_REGS_CNT = 6,
1619 CODE_RAM_ADDR = 0x00020000,
1620 CODE_RAM_CNT = 0x2000,
1621 MEMC_RAM_ADDR = 0x00100000,
1622 MEMC_RAM_CNT = 0x2000,
1623};
1624
1625#define MPI_COREDUMP_COOKIE 0x5555aaaa
1626struct mpi_coredump_global_header {
1627 u32 cookie;
1628 u8 id_string[16];
1629 u32 time_lo;
1630 u32 time_hi;
1631 u32 image_size;
1632 u32 header_size;
1633 u8 info[220];
1634};
1635
1636struct mpi_coredump_segment_header {
1637 u32 cookie;
1638 u32 seg_num;
1639 u32 seg_size;
1640 u32 extra;
1641 u8 description[16];
1642};
1643
1644
1645enum {
1646 CORE_SEG_NUM = 1,
1647 TEST_LOGIC_SEG_NUM = 2,
1648 RMII_SEG_NUM = 3,
1649 FCMAC1_SEG_NUM = 4,
1650 FCMAC2_SEG_NUM = 5,
1651 FC1_MBOX_SEG_NUM = 6,
1652 IDE_SEG_NUM = 7,
1653 NIC1_MBOX_SEG_NUM = 8,
1654 SMBUS_SEG_NUM = 9,
1655 FC2_MBOX_SEG_NUM = 10,
1656 NIC2_MBOX_SEG_NUM = 11,
1657 I2C_SEG_NUM = 12,
1658 MEMC_SEG_NUM = 13,
1659 PBUS_SEG_NUM = 14,
1660 MDE_SEG_NUM = 15,
1661 NIC1_CONTROL_SEG_NUM = 16,
1662 NIC2_CONTROL_SEG_NUM = 17,
1663 NIC1_XGMAC_SEG_NUM = 18,
1664 NIC2_XGMAC_SEG_NUM = 19,
1665 WCS_RAM_SEG_NUM = 20,
1666 MEMC_RAM_SEG_NUM = 21,
1667 XAUI_AN_SEG_NUM = 22,
1668 XAUI_HSS_PCS_SEG_NUM = 23,
1669 XFI_AN_SEG_NUM = 24,
1670 XFI_TRAIN_SEG_NUM = 25,
1671 XFI_HSS_PCS_SEG_NUM = 26,
1672 XFI_HSS_TX_SEG_NUM = 27,
1673 XFI_HSS_RX_SEG_NUM = 28,
1674 XFI_HSS_PLL_SEG_NUM = 29,
1675 MISC_NIC_INFO_SEG_NUM = 30,
1676 INTR_STATES_SEG_NUM = 31,
1677 CAM_ENTRIES_SEG_NUM = 32,
1678 ROUTING_WORDS_SEG_NUM = 33,
1679 ETS_SEG_NUM = 34,
1680 PROBE_DUMP_SEG_NUM = 35,
1681 ROUTING_INDEX_SEG_NUM = 36,
1682 MAC_PROTOCOL_SEG_NUM = 37,
1683 XAUI2_AN_SEG_NUM = 38,
1684 XAUI2_HSS_PCS_SEG_NUM = 39,
1685 XFI2_AN_SEG_NUM = 40,
1686 XFI2_TRAIN_SEG_NUM = 41,
1687 XFI2_HSS_PCS_SEG_NUM = 42,
1688 XFI2_HSS_TX_SEG_NUM = 43,
1689 XFI2_HSS_RX_SEG_NUM = 44,
1690 XFI2_HSS_PLL_SEG_NUM = 45,
1691 SEM_REGS_SEG_NUM = 50
1692
1693};
1694
1695
1696#define NIC_REGS_DUMP_WORD_COUNT 64
1697
1698#define XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4)
1699
1700#define XG_SERDES_XAUI_AN_COUNT 14
1701#define XG_SERDES_XAUI_HSS_PCS_COUNT 33
1702#define XG_SERDES_XFI_AN_COUNT 14
1703#define XG_SERDES_XFI_TRAIN_COUNT 12
1704#define XG_SERDES_XFI_HSS_PCS_COUNT 15
1705#define XG_SERDES_XFI_HSS_TX_COUNT 32
1706#define XG_SERDES_XFI_HSS_RX_COUNT 32
1707#define XG_SERDES_XFI_HSS_PLL_COUNT 32
1708
1709
1710#define ETS_REGS_DUMP_WORD_COUNT 10
1711
1712
1713
1714
1715
1716#define PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2))
1717#define PRB_MX_DUMP_TOT_COUNT (PRB_MX_ADDR_PRB_WORD_COUNT * \
1718 PRB_MX_ADDR_VALID_TOTAL)
1719
1720
1721
1722
1723
1724
1725#define RT_IDX_DUMP_ENTRIES 48
1726#define RT_IDX_DUMP_WORDS_PER_ENTRY 4
1727#define RT_IDX_DUMP_TOT_WORDS (RT_IDX_DUMP_ENTRIES * \
1728 RT_IDX_DUMP_WORDS_PER_ENTRY)
1729
1730
1731
1732#define MAC_ADDR_DUMP_ENTRIES \
1733 ((MAC_ADDR_MAX_CAM_ENTRIES * MAC_ADDR_MAX_CAM_WCOUNT) + \
1734 (MAC_ADDR_MAX_MULTICAST_ENTRIES * MAC_ADDR_MAX_MULTICAST_WCOUNT) + \
1735 (MAC_ADDR_MAX_VLAN_ENTRIES * MAC_ADDR_MAX_VLAN_WCOUNT) + \
1736 (MAC_ADDR_MAX_MCAST_FLTR_ENTRIES * MAC_ADDR_MAX_MCAST_FLTR_WCOUNT) + \
1737 (MAC_ADDR_MAX_FC_MAC_ENTRIES * MAC_ADDR_MAX_FC_MAC_WCOUNT) + \
1738 (MAC_ADDR_MAX_MGMT_MAC_ENTRIES * MAC_ADDR_MAX_MGMT_MAC_WCOUNT) + \
1739 (MAC_ADDR_MAX_MGMT_VLAN_ENTRIES * MAC_ADDR_MAX_MGMT_VLAN_WCOUNT) + \
1740 (MAC_ADDR_MAX_MGMT_V4_ENTRIES * MAC_ADDR_MAX_MGMT_V4_WCOUNT) + \
1741 (MAC_ADDR_MAX_MGMT_V6_ENTRIES * MAC_ADDR_MAX_MGMT_V6_WCOUNT) + \
1742 (MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES * MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT))
1743#define MAC_ADDR_DUMP_WORDS_PER_ENTRY 2
1744#define MAC_ADDR_DUMP_TOT_WORDS (MAC_ADDR_DUMP_ENTRIES * \
1745 MAC_ADDR_DUMP_WORDS_PER_ENTRY)
1746
1747
1748
1749#define MAX_SEMAPHORE_FUNCTIONS 4
1750
1751#define RISC_124 0x0003007c
1752#define RISC_127 0x0003007f
1753#define SHADOW_OFFSET 0xb0000000
1754#define SHADOW_REG_SHIFT 20
1755
1756struct ql_nic_misc {
1757 u32 rx_ring_count;
1758 u32 tx_ring_count;
1759 u32 intr_count;
1760 u32 function;
1761};
1762
1763struct ql_reg_dump {
1764
1765 struct mpi_coredump_global_header mpi_global_header;
1766
1767
1768 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1769 u32 nic_regs[64];
1770
1771
1772 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1773 struct ql_nic_misc misc_nic_info;
1774
1775
1776
1777 struct mpi_coredump_segment_header intr_states_seg_hdr;
1778 u32 intr_states[MAX_CPUS];
1779
1780
1781
1782
1783
1784 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1785 u32 cam_entries[(16 * 3) + (32 * 3)];
1786
1787
1788 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1789 u32 nic_routing_words[16];
1790
1791
1792 struct mpi_coredump_segment_header ets_seg_hdr;
1793 u32 ets[8 + 2];
1794};
1795
1796struct ql_mpi_coredump {
1797
1798 struct mpi_coredump_global_header mpi_global_header;
1799
1800
1801 struct mpi_coredump_segment_header core_regs_seg_hdr;
1802 u32 mpi_core_regs[MPI_CORE_REGS_CNT];
1803 u32 mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT];
1804
1805
1806 struct mpi_coredump_segment_header test_logic_regs_seg_hdr;
1807 u32 test_logic_regs[TEST_REGS_CNT];
1808
1809
1810 struct mpi_coredump_segment_header rmii_regs_seg_hdr;
1811 u32 rmii_regs[RMII_REGS_CNT];
1812
1813
1814 struct mpi_coredump_segment_header fcmac1_regs_seg_hdr;
1815 u32 fcmac1_regs[FCMAC_REGS_CNT];
1816
1817
1818 struct mpi_coredump_segment_header fcmac2_regs_seg_hdr;
1819 u32 fcmac2_regs[FCMAC_REGS_CNT];
1820
1821
1822 struct mpi_coredump_segment_header fc1_mbx_regs_seg_hdr;
1823 u32 fc1_mbx_regs[FC_MBX_REGS_CNT];
1824
1825
1826 struct mpi_coredump_segment_header ide_regs_seg_hdr;
1827 u32 ide_regs[IDE_REGS_CNT];
1828
1829
1830 struct mpi_coredump_segment_header nic1_mbx_regs_seg_hdr;
1831 u32 nic1_mbx_regs[NIC_MBX_REGS_CNT];
1832
1833
1834 struct mpi_coredump_segment_header smbus_regs_seg_hdr;
1835 u32 smbus_regs[SMBUS_REGS_CNT];
1836
1837
1838 struct mpi_coredump_segment_header fc2_mbx_regs_seg_hdr;
1839 u32 fc2_mbx_regs[FC_MBX_REGS_CNT];
1840
1841
1842 struct mpi_coredump_segment_header nic2_mbx_regs_seg_hdr;
1843 u32 nic2_mbx_regs[NIC_MBX_REGS_CNT];
1844
1845
1846 struct mpi_coredump_segment_header i2c_regs_seg_hdr;
1847 u32 i2c_regs[I2C_REGS_CNT];
1848
1849 struct mpi_coredump_segment_header memc_regs_seg_hdr;
1850 u32 memc_regs[MEMC_REGS_CNT];
1851
1852
1853 struct mpi_coredump_segment_header pbus_regs_seg_hdr;
1854 u32 pbus_regs[PBUS_REGS_CNT];
1855
1856
1857 struct mpi_coredump_segment_header mde_regs_seg_hdr;
1858 u32 mde_regs[MDE_REGS_CNT];
1859
1860
1861 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1862 u32 nic_regs[NIC_REGS_DUMP_WORD_COUNT];
1863
1864
1865 struct mpi_coredump_segment_header nic2_regs_seg_hdr;
1866 u32 nic2_regs[NIC_REGS_DUMP_WORD_COUNT];
1867
1868
1869 struct mpi_coredump_segment_header xgmac1_seg_hdr;
1870 u32 xgmac1[XGMAC_DUMP_WORD_COUNT];
1871
1872
1873 struct mpi_coredump_segment_header xgmac2_seg_hdr;
1874 u32 xgmac2[XGMAC_DUMP_WORD_COUNT];
1875
1876
1877 struct mpi_coredump_segment_header code_ram_seg_hdr;
1878 u32 code_ram[CODE_RAM_CNT];
1879
1880
1881 struct mpi_coredump_segment_header memc_ram_seg_hdr;
1882 u32 memc_ram[MEMC_RAM_CNT];
1883
1884
1885 struct mpi_coredump_segment_header xaui_an_hdr;
1886 u32 serdes_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1887
1888
1889 struct mpi_coredump_segment_header xaui_hss_pcs_hdr;
1890 u32 serdes_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1891
1892
1893 struct mpi_coredump_segment_header xfi_an_hdr;
1894 u32 serdes_xfi_an[XG_SERDES_XFI_AN_COUNT];
1895
1896
1897 struct mpi_coredump_segment_header xfi_train_hdr;
1898 u32 serdes_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1899
1900
1901 struct mpi_coredump_segment_header xfi_hss_pcs_hdr;
1902 u32 serdes_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1903
1904
1905 struct mpi_coredump_segment_header xfi_hss_tx_hdr;
1906 u32 serdes_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1907
1908
1909 struct mpi_coredump_segment_header xfi_hss_rx_hdr;
1910 u32 serdes_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1911
1912
1913 struct mpi_coredump_segment_header xfi_hss_pll_hdr;
1914 u32 serdes_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1915
1916
1917 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1918 struct ql_nic_misc misc_nic_info;
1919
1920
1921
1922 struct mpi_coredump_segment_header intr_states_seg_hdr;
1923 u32 intr_states[MAX_RX_RINGS];
1924
1925
1926
1927
1928
1929 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1930 u32 cam_entries[(16 * 3) + (32 * 3)];
1931
1932
1933 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1934 u32 nic_routing_words[16];
1935
1936 struct mpi_coredump_segment_header ets_seg_hdr;
1937 u32 ets[ETS_REGS_DUMP_WORD_COUNT];
1938
1939
1940 struct mpi_coredump_segment_header probe_dump_seg_hdr;
1941 u32 probe_dump[PRB_MX_DUMP_TOT_COUNT];
1942
1943
1944 struct mpi_coredump_segment_header routing_reg_seg_hdr;
1945 u32 routing_regs[RT_IDX_DUMP_TOT_WORDS];
1946
1947
1948 struct mpi_coredump_segment_header mac_prot_reg_seg_hdr;
1949 u32 mac_prot_regs[MAC_ADDR_DUMP_TOT_WORDS];
1950
1951
1952 struct mpi_coredump_segment_header xaui2_an_hdr;
1953 u32 serdes2_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1954
1955
1956 struct mpi_coredump_segment_header xaui2_hss_pcs_hdr;
1957 u32 serdes2_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1958
1959
1960 struct mpi_coredump_segment_header xfi2_an_hdr;
1961 u32 serdes2_xfi_an[XG_SERDES_XFI_AN_COUNT];
1962
1963
1964 struct mpi_coredump_segment_header xfi2_train_hdr;
1965 u32 serdes2_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1966
1967
1968 struct mpi_coredump_segment_header xfi2_hss_pcs_hdr;
1969 u32 serdes2_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1970
1971
1972 struct mpi_coredump_segment_header xfi2_hss_tx_hdr;
1973 u32 serdes2_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1974
1975
1976 struct mpi_coredump_segment_header xfi2_hss_rx_hdr;
1977 u32 serdes2_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1978
1979
1980 struct mpi_coredump_segment_header xfi2_hss_pll_hdr;
1981 u32 serdes2_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1982
1983
1984
1985 struct mpi_coredump_segment_header sem_regs_seg_hdr;
1986 u32 sem_regs[MAX_SEMAPHORE_FUNCTIONS];
1987};
1988
1989
1990
1991
1992
1993
1994struct intr_context {
1995 struct ql_adapter *qdev;
1996 u32 intr;
1997 u32 irq_mask;
1998 u32 hooked;
1999 u32 intr_en_mask;
2000 u32 intr_dis_mask;
2001 u32 intr_read_mask;
2002 char name[IFNAMSIZ * 2];
2003 irq_handler_t handler;
2004};
2005
2006
2007enum {
2008 QL_ADAPTER_UP = 0,
2009 QL_LEGACY_ENABLED = 1,
2010 QL_MSI_ENABLED = 2,
2011 QL_MSIX_ENABLED = 3,
2012 QL_DMA64 = 4,
2013 QL_PROMISCUOUS = 5,
2014 QL_ALLMULTI = 6,
2015 QL_PORT_CFG = 7,
2016 QL_CAM_RT_SET = 8,
2017 QL_SELFTEST = 9,
2018 QL_LB_LINK_UP = 10,
2019 QL_FRC_COREDUMP = 11,
2020 QL_EEH_FATAL = 12,
2021 QL_ASIC_RECOVERY = 14,
2022};
2023
2024
2025enum {
2026 STS_LOOPBACK_MASK = 0x00000700,
2027 STS_LOOPBACK_PCS = 0x00000100,
2028 STS_LOOPBACK_HSS = 0x00000200,
2029 STS_LOOPBACK_EXT = 0x00000300,
2030 STS_PAUSE_MASK = 0x000000c0,
2031 STS_PAUSE_STD = 0x00000040,
2032 STS_PAUSE_PRI = 0x00000080,
2033 STS_SPEED_MASK = 0x00000038,
2034 STS_SPEED_100Mb = 0x00000000,
2035 STS_SPEED_1Gb = 0x00000008,
2036 STS_SPEED_10Gb = 0x00000010,
2037 STS_LINK_TYPE_MASK = 0x00000007,
2038 STS_LINK_TYPE_XFI = 0x00000001,
2039 STS_LINK_TYPE_XAUI = 0x00000002,
2040 STS_LINK_TYPE_XFI_BP = 0x00000003,
2041 STS_LINK_TYPE_XAUI_BP = 0x00000004,
2042 STS_LINK_TYPE_10GBASET = 0x00000005,
2043};
2044
2045
2046enum {
2047 CFG_JUMBO_FRAME_SIZE = 0x00010000,
2048 CFG_PAUSE_MASK = 0x00000060,
2049 CFG_PAUSE_STD = 0x00000020,
2050 CFG_PAUSE_PRI = 0x00000040,
2051 CFG_DCBX = 0x00000010,
2052 CFG_LOOPBACK_MASK = 0x00000007,
2053 CFG_LOOPBACK_PCS = 0x00000002,
2054 CFG_LOOPBACK_HSS = 0x00000004,
2055 CFG_LOOPBACK_EXT = 0x00000006,
2056 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
2057};
2058
2059struct nic_operations {
2060 int (*get_flash) (struct ql_adapter *);
2061 int (*port_initialize) (struct ql_adapter *);
2062};
2063
2064
2065
2066
2067
2068struct ql_adapter {
2069 struct ricb ricb;
2070 unsigned long flags;
2071 u32 wol;
2072
2073 struct nic_stats nic_stats;
2074
2075 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
2076
2077
2078 struct pci_dev *pdev;
2079 struct net_device *ndev;
2080
2081
2082 u32 chip_rev_id;
2083 u32 fw_rev_id;
2084 u32 func;
2085 u32 alt_func;
2086 u32 port;
2087
2088 spinlock_t adapter_lock;
2089 spinlock_t stats_lock;
2090
2091
2092 void __iomem *reg_base;
2093 void __iomem *doorbell_area;
2094 u32 doorbell_area_size;
2095
2096 u32 msg_enable;
2097
2098
2099 void *rx_ring_shadow_reg_area;
2100 dma_addr_t rx_ring_shadow_reg_dma;
2101 void *tx_ring_shadow_reg_area;
2102 dma_addr_t tx_ring_shadow_reg_dma;
2103
2104 u32 mailbox_in;
2105 u32 mailbox_out;
2106 struct mbox_params idc_mbc;
2107 struct mutex mpi_mutex;
2108
2109 int tx_ring_size;
2110 int rx_ring_size;
2111 u32 intr_count;
2112 struct msix_entry *msi_x_entry;
2113 struct intr_context intr_context[MAX_RX_RINGS];
2114
2115 int tx_ring_count;
2116 u32 rss_ring_count;
2117
2118
2119
2120
2121
2122 int rx_ring_count;
2123 int ring_mem_size;
2124 void *ring_mem;
2125
2126 struct rx_ring rx_ring[MAX_RX_RINGS];
2127 struct tx_ring tx_ring[MAX_TX_RINGS];
2128 unsigned int lbq_buf_order;
2129 u32 lbq_buf_size;
2130
2131 int rx_csum;
2132 u32 default_rx_queue;
2133
2134 u16 rx_coalesce_usecs;
2135 u16 rx_max_coalesced_frames;
2136 u16 tx_coalesce_usecs;
2137 u16 tx_max_coalesced_frames;
2138
2139 u32 xg_sem_mask;
2140 u32 port_link_up;
2141 u32 port_init;
2142 u32 link_status;
2143 struct ql_mpi_coredump *mpi_coredump;
2144 u32 core_is_dumped;
2145 u32 link_config;
2146 u32 led_config;
2147 u32 max_frame_size;
2148
2149 union flash_params flash;
2150
2151 struct workqueue_struct *workqueue;
2152 struct delayed_work asic_reset_work;
2153 struct delayed_work mpi_reset_work;
2154 struct delayed_work mpi_work;
2155 struct delayed_work mpi_port_cfg_work;
2156 struct delayed_work mpi_idc_work;
2157 struct delayed_work mpi_core_to_log;
2158 struct completion ide_completion;
2159 const struct nic_operations *nic_ops;
2160 u16 device_id;
2161 struct timer_list timer;
2162 atomic_t lb_count;
2163
2164 char current_mac_addr[ETH_ALEN];
2165};
2166
2167
2168
2169
2170static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
2171{
2172 return readl(qdev->reg_base + reg);
2173}
2174
2175
2176
2177
2178static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
2179{
2180 writel(val, qdev->reg_base + reg);
2181}
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193static inline void ql_write_db_reg(u32 val, void __iomem *addr)
2194{
2195 writel(val, addr);
2196}
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209static inline void ql_write_db_reg_relaxed(u32 val, void __iomem *addr)
2210{
2211 writel_relaxed(val, addr);
2212}
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224static inline u32 ql_read_sh_reg(__le32 *addr)
2225{
2226 u32 reg;
2227 reg = le32_to_cpu(*addr);
2228 rmb();
2229 return reg;
2230}
2231
2232extern char qlge_driver_name[];
2233extern const char qlge_driver_version[];
2234extern const struct ethtool_ops qlge_ethtool_ops;
2235
2236int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
2237void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
2238int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2239int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
2240 u32 *value);
2241int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
2242int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
2243 u16 q_id);
2244void ql_queue_fw_error(struct ql_adapter *qdev);
2245void ql_mpi_work(struct work_struct *work);
2246void ql_mpi_reset_work(struct work_struct *work);
2247void ql_mpi_core_to_log(struct work_struct *work);
2248int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
2249void ql_queue_asic_error(struct ql_adapter *qdev);
2250void ql_set_ethtool_ops(struct net_device *ndev);
2251int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
2252void ql_mpi_idc_work(struct work_struct *work);
2253void ql_mpi_port_cfg_work(struct work_struct *work);
2254int ql_mb_get_fw_state(struct ql_adapter *qdev);
2255int ql_cam_route_initialize(struct ql_adapter *qdev);
2256int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2257int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data);
2258int ql_unpause_mpi_risc(struct ql_adapter *qdev);
2259int ql_pause_mpi_risc(struct ql_adapter *qdev);
2260int ql_hard_reset_mpi_risc(struct ql_adapter *qdev);
2261int ql_soft_reset_mpi_risc(struct ql_adapter *qdev);
2262int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf, u32 ram_addr,
2263 int word_count);
2264int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump);
2265int ql_mb_about_fw(struct ql_adapter *qdev);
2266int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol);
2267int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol);
2268int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config);
2269int ql_mb_get_led_cfg(struct ql_adapter *qdev);
2270void ql_link_on(struct ql_adapter *qdev);
2271void ql_link_off(struct ql_adapter *qdev);
2272int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
2273int ql_mb_get_port_cfg(struct ql_adapter *qdev);
2274int ql_mb_set_port_cfg(struct ql_adapter *qdev);
2275int ql_wait_fifo_empty(struct ql_adapter *qdev);
2276void ql_get_dump(struct ql_adapter *qdev, void *buff);
2277netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev);
2278void ql_check_lb_frame(struct ql_adapter *, struct sk_buff *);
2279int ql_own_firmware(struct ql_adapter *qdev);
2280int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget);
2281
2282
2283
2284
2285
2286
2287
2288
2289#ifdef QL_REG_DUMP
2290void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
2291void ql_dump_routing_entries(struct ql_adapter *qdev);
2292void ql_dump_regs(struct ql_adapter *qdev);
2293#define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
2294#define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
2295#define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
2296#else
2297#define QL_DUMP_REGS(qdev)
2298#define QL_DUMP_ROUTE(qdev)
2299#define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
2300#endif
2301
2302#ifdef QL_STAT_DUMP
2303void ql_dump_stat(struct ql_adapter *qdev);
2304#define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
2305#else
2306#define QL_DUMP_STAT(qdev)
2307#endif
2308
2309#ifdef QL_DEV_DUMP
2310void ql_dump_qdev(struct ql_adapter *qdev);
2311#define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
2312#else
2313#define QL_DUMP_QDEV(qdev)
2314#endif
2315
2316#ifdef QL_CB_DUMP
2317void ql_dump_wqicb(struct wqicb *wqicb);
2318void ql_dump_tx_ring(struct tx_ring *tx_ring);
2319void ql_dump_ricb(struct ricb *ricb);
2320void ql_dump_cqicb(struct cqicb *cqicb);
2321void ql_dump_rx_ring(struct rx_ring *rx_ring);
2322void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
2323#define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
2324#define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
2325#define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
2326#define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
2327#define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
2328#define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
2329 ql_dump_hw_cb(qdev, size, bit, q_id)
2330#else
2331#define QL_DUMP_RICB(ricb)
2332#define QL_DUMP_WQICB(wqicb)
2333#define QL_DUMP_TX_RING(tx_ring)
2334#define QL_DUMP_CQICB(cqicb)
2335#define QL_DUMP_RX_RING(rx_ring)
2336#define QL_DUMP_HW_CB(qdev, size, bit, q_id)
2337#endif
2338
2339#ifdef QL_OB_DUMP
2340void ql_dump_tx_desc(struct tx_buf_desc *tbd);
2341void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
2342void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
2343#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
2344#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
2345#else
2346#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
2347#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
2348#endif
2349
2350#ifdef QL_IB_DUMP
2351void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
2352#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
2353#else
2354#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
2355#endif
2356
2357#ifdef QL_ALL_DUMP
2358void ql_dump_all(struct ql_adapter *qdev);
2359#define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
2360#else
2361#define QL_DUMP_ALL(qdev)
2362#endif
2363
2364#endif
2365
