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8#include <linux/clk.h>
9#include <linux/dma-mapping.h>
10#include <linux/iopoll.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/platform_device.h>
16
17#include "mtu3.h"
18#include "mtu3_dr.h"
19#include "mtu3_debug.h"
20
21
22int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
23{
24 void __iomem *ibase = ssusb->ippc_base;
25 u32 value, check_val;
26 int ret;
27
28 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
29 SSUSB_REF_RST_B_STS;
30
31 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
32 (check_val == (value & check_val)), 100, 20000);
33 if (ret) {
34 dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
35 return ret;
36 }
37
38 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
39 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
40 if (ret) {
41 dev_err(ssusb->dev, "mac2 clock is not stable\n");
42 return ret;
43 }
44
45 return 0;
46}
47
48static int ssusb_phy_init(struct ssusb_mtk *ssusb)
49{
50 int i;
51 int ret;
52
53 for (i = 0; i < ssusb->num_phys; i++) {
54 ret = phy_init(ssusb->phys[i]);
55 if (ret)
56 goto exit_phy;
57 }
58 return 0;
59
60exit_phy:
61 for (; i > 0; i--)
62 phy_exit(ssusb->phys[i - 1]);
63
64 return ret;
65}
66
67static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
68{
69 int i;
70
71 for (i = 0; i < ssusb->num_phys; i++)
72 phy_exit(ssusb->phys[i]);
73
74 return 0;
75}
76
77static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
78{
79 int i;
80 int ret;
81
82 for (i = 0; i < ssusb->num_phys; i++) {
83 ret = phy_power_on(ssusb->phys[i]);
84 if (ret)
85 goto power_off_phy;
86 }
87 return 0;
88
89power_off_phy:
90 for (; i > 0; i--)
91 phy_power_off(ssusb->phys[i - 1]);
92
93 return ret;
94}
95
96static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
97{
98 unsigned int i;
99
100 for (i = 0; i < ssusb->num_phys; i++)
101 phy_power_off(ssusb->phys[i]);
102}
103
104static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
105{
106 int ret;
107
108 ret = clk_prepare_enable(ssusb->sys_clk);
109 if (ret) {
110 dev_err(ssusb->dev, "failed to enable sys_clk\n");
111 goto sys_clk_err;
112 }
113
114 ret = clk_prepare_enable(ssusb->ref_clk);
115 if (ret) {
116 dev_err(ssusb->dev, "failed to enable ref_clk\n");
117 goto ref_clk_err;
118 }
119
120 ret = clk_prepare_enable(ssusb->mcu_clk);
121 if (ret) {
122 dev_err(ssusb->dev, "failed to enable mcu_clk\n");
123 goto mcu_clk_err;
124 }
125
126 ret = clk_prepare_enable(ssusb->dma_clk);
127 if (ret) {
128 dev_err(ssusb->dev, "failed to enable dma_clk\n");
129 goto dma_clk_err;
130 }
131
132 return 0;
133
134dma_clk_err:
135 clk_disable_unprepare(ssusb->mcu_clk);
136mcu_clk_err:
137 clk_disable_unprepare(ssusb->ref_clk);
138ref_clk_err:
139 clk_disable_unprepare(ssusb->sys_clk);
140sys_clk_err:
141 return ret;
142}
143
144static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
145{
146 clk_disable_unprepare(ssusb->dma_clk);
147 clk_disable_unprepare(ssusb->mcu_clk);
148 clk_disable_unprepare(ssusb->ref_clk);
149 clk_disable_unprepare(ssusb->sys_clk);
150}
151
152static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
153{
154 int ret = 0;
155
156 ret = regulator_enable(ssusb->vusb33);
157 if (ret) {
158 dev_err(ssusb->dev, "failed to enable vusb33\n");
159 goto vusb33_err;
160 }
161
162 ret = ssusb_clks_enable(ssusb);
163 if (ret)
164 goto clks_err;
165
166 ret = ssusb_phy_init(ssusb);
167 if (ret) {
168 dev_err(ssusb->dev, "failed to init phy\n");
169 goto phy_init_err;
170 }
171
172 ret = ssusb_phy_power_on(ssusb);
173 if (ret) {
174 dev_err(ssusb->dev, "failed to power on phy\n");
175 goto phy_err;
176 }
177
178 return 0;
179
180phy_err:
181 ssusb_phy_exit(ssusb);
182phy_init_err:
183 ssusb_clks_disable(ssusb);
184clks_err:
185 regulator_disable(ssusb->vusb33);
186vusb33_err:
187 return ret;
188}
189
190static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
191{
192 ssusb_clks_disable(ssusb);
193 regulator_disable(ssusb->vusb33);
194 ssusb_phy_power_off(ssusb);
195 ssusb_phy_exit(ssusb);
196}
197
198static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
199{
200
201 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
202 udelay(1);
203 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
204
205
206
207
208
209
210
211 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
212}
213
214static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
215{
216 struct device_node *node = pdev->dev.of_node;
217 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
218 struct device *dev = &pdev->dev;
219 struct resource *res;
220 int i;
221 int ret;
222
223 ssusb->vusb33 = devm_regulator_get(dev, "vusb33");
224 if (IS_ERR(ssusb->vusb33)) {
225 dev_err(dev, "failed to get vusb33\n");
226 return PTR_ERR(ssusb->vusb33);
227 }
228
229 ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
230 if (IS_ERR(ssusb->sys_clk)) {
231 dev_err(dev, "failed to get sys clock\n");
232 return PTR_ERR(ssusb->sys_clk);
233 }
234
235 ssusb->ref_clk = devm_clk_get_optional(dev, "ref_ck");
236 if (IS_ERR(ssusb->ref_clk))
237 return PTR_ERR(ssusb->ref_clk);
238
239 ssusb->mcu_clk = devm_clk_get_optional(dev, "mcu_ck");
240 if (IS_ERR(ssusb->mcu_clk))
241 return PTR_ERR(ssusb->mcu_clk);
242
243 ssusb->dma_clk = devm_clk_get_optional(dev, "dma_ck");
244 if (IS_ERR(ssusb->dma_clk))
245 return PTR_ERR(ssusb->dma_clk);
246
247 ssusb->num_phys = of_count_phandle_with_args(node,
248 "phys", "#phy-cells");
249 if (ssusb->num_phys > 0) {
250 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
251 sizeof(*ssusb->phys), GFP_KERNEL);
252 if (!ssusb->phys)
253 return -ENOMEM;
254 } else {
255 ssusb->num_phys = 0;
256 }
257
258 for (i = 0; i < ssusb->num_phys; i++) {
259 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
260 if (IS_ERR(ssusb->phys[i])) {
261 dev_err(dev, "failed to get phy-%d\n", i);
262 return PTR_ERR(ssusb->phys[i]);
263 }
264 }
265
266 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
267 ssusb->ippc_base = devm_ioremap_resource(dev, res);
268 if (IS_ERR(ssusb->ippc_base))
269 return PTR_ERR(ssusb->ippc_base);
270
271 ssusb->dr_mode = usb_get_dr_mode(dev);
272 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
273 ssusb->dr_mode = USB_DR_MODE_OTG;
274
275 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
276 goto out;
277
278
279 ret = ssusb_wakeup_of_property_parse(ssusb, node);
280 if (ret) {
281 dev_err(dev, "failed to parse uwk property\n");
282 return ret;
283 }
284
285
286 of_property_read_u32(node, "mediatek,u3p-dis-msk",
287 &ssusb->u3p_dis_msk);
288
289 otg_sx->vbus = devm_regulator_get(dev, "vbus");
290 if (IS_ERR(otg_sx->vbus)) {
291 dev_err(dev, "failed to get vbus\n");
292 return PTR_ERR(otg_sx->vbus);
293 }
294
295 if (ssusb->dr_mode == USB_DR_MODE_HOST)
296 goto out;
297
298
299 otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
300 otg_sx->manual_drd_enabled =
301 of_property_read_bool(node, "enable-manual-drd");
302 otg_sx->role_sw_used = of_property_read_bool(node, "usb-role-switch");
303
304 if (!otg_sx->role_sw_used && of_property_read_bool(node, "extcon")) {
305 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
306 if (IS_ERR(otg_sx->edev)) {
307 dev_err(ssusb->dev, "couldn't get extcon device\n");
308 return PTR_ERR(otg_sx->edev);
309 }
310 }
311
312out:
313 dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
314 ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
315 otg_sx->manual_drd_enabled ? "manual" : "auto");
316
317 return 0;
318}
319
320static int mtu3_probe(struct platform_device *pdev)
321{
322 struct device_node *node = pdev->dev.of_node;
323 struct device *dev = &pdev->dev;
324 struct ssusb_mtk *ssusb;
325 int ret = -ENOMEM;
326
327
328 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
329 if (!ssusb)
330 return -ENOMEM;
331
332 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
333 if (ret) {
334 dev_err(dev, "No suitable DMA config available\n");
335 return -ENOTSUPP;
336 }
337
338 platform_set_drvdata(pdev, ssusb);
339 ssusb->dev = dev;
340
341 ret = get_ssusb_rscs(pdev, ssusb);
342 if (ret)
343 return ret;
344
345 ssusb_debugfs_create_root(ssusb);
346
347
348 pm_runtime_enable(dev);
349 pm_runtime_get_sync(dev);
350 device_enable_async_suspend(dev);
351
352 ret = ssusb_rscs_init(ssusb);
353 if (ret)
354 goto comm_init_err;
355
356 ssusb_ip_sw_reset(ssusb);
357
358 if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
359 ssusb->dr_mode = USB_DR_MODE_HOST;
360 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
361 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
362
363
364 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
365
366 switch (ssusb->dr_mode) {
367 case USB_DR_MODE_PERIPHERAL:
368 ret = ssusb_gadget_init(ssusb);
369 if (ret) {
370 dev_err(dev, "failed to initialize gadget\n");
371 goto comm_exit;
372 }
373 break;
374 case USB_DR_MODE_HOST:
375 ret = ssusb_host_init(ssusb, node);
376 if (ret) {
377 dev_err(dev, "failed to initialize host\n");
378 goto comm_exit;
379 }
380 break;
381 case USB_DR_MODE_OTG:
382 ret = ssusb_gadget_init(ssusb);
383 if (ret) {
384 dev_err(dev, "failed to initialize gadget\n");
385 goto comm_exit;
386 }
387
388 ret = ssusb_host_init(ssusb, node);
389 if (ret) {
390 dev_err(dev, "failed to initialize host\n");
391 goto gadget_exit;
392 }
393
394 ret = ssusb_otg_switch_init(ssusb);
395 if (ret) {
396 dev_err(dev, "failed to initialize switch\n");
397 goto host_exit;
398 }
399 break;
400 default:
401 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
402 ret = -EINVAL;
403 goto comm_exit;
404 }
405
406 return 0;
407
408host_exit:
409 ssusb_host_exit(ssusb);
410gadget_exit:
411 ssusb_gadget_exit(ssusb);
412comm_exit:
413 ssusb_rscs_exit(ssusb);
414comm_init_err:
415 pm_runtime_put_sync(dev);
416 pm_runtime_disable(dev);
417 ssusb_debugfs_remove_root(ssusb);
418
419 return ret;
420}
421
422static int mtu3_remove(struct platform_device *pdev)
423{
424 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
425
426 switch (ssusb->dr_mode) {
427 case USB_DR_MODE_PERIPHERAL:
428 ssusb_gadget_exit(ssusb);
429 break;
430 case USB_DR_MODE_HOST:
431 ssusb_host_exit(ssusb);
432 break;
433 case USB_DR_MODE_OTG:
434 ssusb_otg_switch_exit(ssusb);
435 ssusb_gadget_exit(ssusb);
436 ssusb_host_exit(ssusb);
437 break;
438 default:
439 return -EINVAL;
440 }
441
442 ssusb_rscs_exit(ssusb);
443 pm_runtime_put_sync(&pdev->dev);
444 pm_runtime_disable(&pdev->dev);
445 ssusb_debugfs_remove_root(ssusb);
446
447 return 0;
448}
449
450
451
452
453
454static int __maybe_unused mtu3_suspend(struct device *dev)
455{
456 struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
457
458 dev_dbg(dev, "%s\n", __func__);
459
460
461 if (!ssusb->is_host)
462 return 0;
463
464 ssusb_host_disable(ssusb, true);
465 ssusb_phy_power_off(ssusb);
466 ssusb_clks_disable(ssusb);
467 ssusb_wakeup_set(ssusb, true);
468
469 return 0;
470}
471
472static int __maybe_unused mtu3_resume(struct device *dev)
473{
474 struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
475 int ret;
476
477 dev_dbg(dev, "%s\n", __func__);
478
479 if (!ssusb->is_host)
480 return 0;
481
482 ssusb_wakeup_set(ssusb, false);
483 ret = ssusb_clks_enable(ssusb);
484 if (ret)
485 goto clks_err;
486
487 ret = ssusb_phy_power_on(ssusb);
488 if (ret)
489 goto phy_err;
490
491 ssusb_host_enable(ssusb);
492
493 return 0;
494
495phy_err:
496 ssusb_clks_disable(ssusb);
497clks_err:
498 return ret;
499}
500
501static const struct dev_pm_ops mtu3_pm_ops = {
502 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
503};
504
505#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
506
507#ifdef CONFIG_OF
508
509static const struct of_device_id mtu3_of_match[] = {
510 {.compatible = "mediatek,mt8173-mtu3",},
511 {.compatible = "mediatek,mtu3",},
512 {},
513};
514
515MODULE_DEVICE_TABLE(of, mtu3_of_match);
516
517#endif
518
519static struct platform_driver mtu3_driver = {
520 .probe = mtu3_probe,
521 .remove = mtu3_remove,
522 .driver = {
523 .name = MTU3_DRIVER_NAME,
524 .pm = DEV_PM_OPS,
525 .of_match_table = of_match_ptr(mtu3_of_match),
526 },
527};
528module_platform_driver(mtu3_driver);
529
530MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
531MODULE_LICENSE("GPL v2");
532MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");
533
