linux/include/dt-bindings/clock/stih407-clks.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * This header provides constants clk index STMicroelectronics
   4 * STiH407 SoC.
   5 */
   6#ifndef _DT_BINDINGS_CLK_STIH407
   7#define _DT_BINDINGS_CLK_STIH407
   8
   9/* CLOCKGEN A0 */
  10#define CLK_IC_LMI0             0
  11#define CLK_IC_LMI1             1
  12
  13/* CLOCKGEN C0 */
  14#define CLK_ICN_GPU             0
  15#define CLK_FDMA                1
  16#define CLK_NAND                2
  17#define CLK_HVA                 3
  18#define CLK_PROC_STFE           4
  19#define CLK_PROC_TP             5
  20#define CLK_RX_ICN_DMU          6
  21#define CLK_RX_ICN_DISP_0       6
  22#define CLK_RX_ICN_DISP_1       6
  23#define CLK_RX_ICN_HVA          7
  24#define CLK_RX_ICN_TS           7
  25#define CLK_ICN_CPU             8
  26#define CLK_TX_ICN_DMU          9
  27#define CLK_TX_ICN_HVA          9
  28#define CLK_TX_ICN_TS           9
  29#define CLK_ICN_COMPO           9
  30#define CLK_MMC_0               10
  31#define CLK_MMC_1               11
  32#define CLK_JPEGDEC             12
  33#define CLK_ICN_REG             13
  34#define CLK_TRACE_A9            13
  35#define CLK_PTI_STM             13
  36#define CLK_EXT2F_A9            13
  37#define CLK_IC_BDISP_0          14
  38#define CLK_IC_BDISP_1          15
  39#define CLK_PP_DMU              16
  40#define CLK_VID_DMU             17
  41#define CLK_DSS_LPC             18
  42#define CLK_ST231_AUD_0         19
  43#define CLK_ST231_GP_0          19
  44#define CLK_ST231_GP_1          20
  45#define CLK_ST231_DMU           21
  46#define CLK_ICN_LMI             22
  47#define CLK_TX_ICN_DISP_0       23
  48#define CLK_TX_ICN_DISP_1       23
  49#define CLK_ICN_SBC             24
  50#define CLK_STFE_FRC2           25
  51#define CLK_ETH_PHY             26
  52#define CLK_ETH_REF_PHYCLK      27
  53#define CLK_FLASH_PROMIP        28
  54#define CLK_MAIN_DISP           29
  55#define CLK_AUX_DISP            30
  56#define CLK_COMPO_DVP           31
  57
  58/* CLOCKGEN D0 */
  59#define CLK_PCM_0               0
  60#define CLK_PCM_1               1
  61#define CLK_PCM_2               2
  62#define CLK_SPDIFF              3
  63
  64/* CLOCKGEN D2 */
  65#define CLK_PIX_MAIN_DISP       0
  66#define CLK_PIX_PIP             1
  67#define CLK_PIX_GDP1            2
  68#define CLK_PIX_GDP2            3
  69#define CLK_PIX_GDP3            4
  70#define CLK_PIX_GDP4            5
  71#define CLK_PIX_AUX_DISP        6
  72#define CLK_DENC                7
  73#define CLK_PIX_HDDAC           8
  74#define CLK_HDDAC               9
  75#define CLK_SDDAC               10
  76#define CLK_PIX_DVO             11
  77#define CLK_DVO                 12
  78#define CLK_PIX_HDMI            13
  79#define CLK_TMDS_HDMI           14
  80#define CLK_REF_HDMIPHY         15
  81
  82/* CLOCKGEN D3 */
  83#define CLK_STFE_FRC1           0
  84#define CLK_TSOUT_0             1
  85#define CLK_TSOUT_1             2
  86#define CLK_MCHI                3
  87#define CLK_VSENS_COMPO         4
  88#define CLK_FRC1_REMOTE         5
  89#define CLK_LPC_0               6
  90#define CLK_LPC_1               7
  91#endif
  92