LXR linux/include/linux/mtd/spinand.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2016-2017 Micron Technology, Inc.
   4 *
   5 *  Authors:
   6 *      Peter Pan <peterpandong@micron.com>
   7 */
   8#ifndef __LINUX_MTD_SPINAND_H
   9#define __LINUX_MTD_SPINAND_H
  10
  11#include <linux/mutex.h>
  12#include <linux/bitops.h>
  13#include <linux/device.h>
  14#include <linux/mtd/mtd.h>
  15#include <linux/mtd/nand.h>
  16#include <linux/spi/spi.h>
  17#include <linux/spi/spi-mem.h>
  18
  19/**
  20 * Standard SPI NAND flash operations
  21 */
  22
  23#define SPINAND_RESET_OP                                                \
  24        SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1),                             \
  25                   SPI_MEM_OP_NO_ADDR,                                  \
  26                   SPI_MEM_OP_NO_DUMMY,                                 \
  27                   SPI_MEM_OP_NO_DATA)
  28
  29#define SPINAND_WR_EN_DIS_OP(enable)                                    \
  30        SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1),           \
  31                   SPI_MEM_OP_NO_ADDR,                                  \
  32                   SPI_MEM_OP_NO_DUMMY,                                 \
  33                   SPI_MEM_OP_NO_DATA)
  34
  35#define SPINAND_READID_OP(naddr, ndummy, buf, len)                      \
  36        SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),                             \
  37                   SPI_MEM_OP_ADDR(naddr, 0, 1),                        \
  38                   SPI_MEM_OP_DUMMY(ndummy, 1),                         \
  39                   SPI_MEM_OP_DATA_IN(len, buf, 1))
  40
  41#define SPINAND_SET_FEATURE_OP(reg, valptr)                             \
  42        SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1),                             \
  43                   SPI_MEM_OP_ADDR(1, reg, 1),                          \
  44                   SPI_MEM_OP_NO_DUMMY,                                 \
  45                   SPI_MEM_OP_DATA_OUT(1, valptr, 1))
  46
  47#define SPINAND_GET_FEATURE_OP(reg, valptr)                             \
  48        SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1),                             \
  49                   SPI_MEM_OP_ADDR(1, reg, 1),                          \
  50                   SPI_MEM_OP_NO_DUMMY,                                 \
  51                   SPI_MEM_OP_DATA_IN(1, valptr, 1))
  52
  53#define SPINAND_BLK_ERASE_OP(addr)                                      \
  54        SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1),                             \
  55                   SPI_MEM_OP_ADDR(3, addr, 1),                         \
  56                   SPI_MEM_OP_NO_DUMMY,                                 \
  57                   SPI_MEM_OP_NO_DATA)
  58
  59#define SPINAND_PAGE_READ_OP(addr)                                      \
  60        SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1),                             \
  61                   SPI_MEM_OP_ADDR(3, addr, 1),                         \
  62                   SPI_MEM_OP_NO_DUMMY,                                 \
  63                   SPI_MEM_OP_NO_DATA)
  64
  65#define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len)   \
  66        SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),               \
  67                   SPI_MEM_OP_ADDR(2, addr, 1),                         \
  68                   SPI_MEM_OP_DUMMY(ndummy, 1),                         \
  69                   SPI_MEM_OP_DATA_IN(len, buf, 1))
  70
  71#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \
  72        SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),               \
  73                   SPI_MEM_OP_ADDR(3, addr, 1),                         \
  74                   SPI_MEM_OP_DUMMY(ndummy, 1),                         \
  75                   SPI_MEM_OP_DATA_IN(len, buf, 1))
  76
  77#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len)      \
  78        SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),                             \
  79                   SPI_MEM_OP_ADDR(2, addr, 1),                         \
  80                   SPI_MEM_OP_DUMMY(ndummy, 1),                         \
  81                   SPI_MEM_OP_DATA_IN(len, buf, 2))
  82
  83#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len)   \
  84        SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),                             \
  85                   SPI_MEM_OP_ADDR(3, addr, 1),                         \
  86                   SPI_MEM_OP_DUMMY(ndummy, 1),                         \
  87                   SPI_MEM_OP_DATA_IN(len, buf, 2))
  88
  89#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len)      \
  90        SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),                             \
  91                   SPI_MEM_OP_ADDR(2, addr, 1),                         \
  92                   SPI_MEM_OP_DUMMY(ndummy, 1),                         \
  93                   SPI_MEM_OP_DATA_IN(len, buf, 4))
  94
  95#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len)   \
  96        SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),                             \
  97                   SPI_MEM_OP_ADDR(3, addr, 1),                         \
  98                   SPI_MEM_OP_DUMMY(ndummy, 1),                         \
  99                   SPI_MEM_OP_DATA_IN(len, buf, 4))
 100
 101#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len)  \
 102        SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),                             \
 103                   SPI_MEM_OP_ADDR(2, addr, 2),                         \
 104                   SPI_MEM_OP_DUMMY(ndummy, 2),                         \
 105                   SPI_MEM_OP_DATA_IN(len, buf, 2))
 106
 107#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \
 108        SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),                             \
 109                   SPI_MEM_OP_ADDR(3, addr, 2),                         \
 110                   SPI_MEM_OP_DUMMY(ndummy, 2),                         \
 111                   SPI_MEM_OP_DATA_IN(len, buf, 2))
 112
 113#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len)  \
 114        SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),                             \
 115                   SPI_MEM_OP_ADDR(2, addr, 4),                         \
 116                   SPI_MEM_OP_DUMMY(ndummy, 4),                         \
 117                   SPI_MEM_OP_DATA_IN(len, buf, 4))
 118
 119#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \
 120        SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),                             \
 121                   SPI_MEM_OP_ADDR(3, addr, 4),                         \
 122                   SPI_MEM_OP_DUMMY(ndummy, 4),                         \
 123                   SPI_MEM_OP_DATA_IN(len, buf, 4))
 124
 125#define SPINAND_PROG_EXEC_OP(addr)                                      \
 126        SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1),                             \
 127                   SPI_MEM_OP_ADDR(3, addr, 1),                         \
 128                   SPI_MEM_OP_NO_DUMMY,                                 \
 129                   SPI_MEM_OP_NO_DATA)
 130
 131#define SPINAND_PROG_LOAD(reset, addr, buf, len)                        \
 132        SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1),              \
 133                   SPI_MEM_OP_ADDR(2, addr, 1),                         \
 134                   SPI_MEM_OP_NO_DUMMY,                                 \
 135                   SPI_MEM_OP_DATA_OUT(len, buf, 1))
 136
 137#define SPINAND_PROG_LOAD_X4(reset, addr, buf, len)                     \
 138        SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1),              \
 139                   SPI_MEM_OP_ADDR(2, addr, 1),                         \
 140                   SPI_MEM_OP_NO_DUMMY,                                 \
 141                   SPI_MEM_OP_DATA_OUT(len, buf, 4))
 142
 143/**
 144 * Standard SPI NAND flash commands
 145 */
 146#define SPINAND_CMD_PROG_LOAD_X4                0x32
 147#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4       0x34
 148
 149/* feature register */
 150#define REG_BLOCK_LOCK          0xa0
 151#define BL_ALL_UNLOCKED         0x00
 152
 153/* configuration register */
 154#define REG_CFG                 0xb0
 155#define CFG_OTP_ENABLE          BIT(6)
 156#define CFG_ECC_ENABLE          BIT(4)
 157#define CFG_QUAD_ENABLE         BIT(0)
 158
 159/* status register */
 160#define REG_STATUS              0xc0
 161#define STATUS_BUSY             BIT(0)
 162#define STATUS_ERASE_FAILED     BIT(2)
 163#define STATUS_PROG_FAILED      BIT(3)
 164#define STATUS_ECC_MASK         GENMASK(5, 4)
 165#define STATUS_ECC_NO_BITFLIPS  (0 << 4)
 166#define STATUS_ECC_HAS_BITFLIPS (1 << 4)
 167#define STATUS_ECC_UNCOR_ERROR  (2 << 4)
 168
 169struct spinand_op;
 170struct spinand_device;
 171
 172#define SPINAND_MAX_ID_LEN      4
 173
 174/**
 175 * struct spinand_id - SPI NAND id structure
 176 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
 177 *        be extended if required
 178 * @len: ID length
 179 */
 180struct spinand_id {
 181        u8 data[SPINAND_MAX_ID_LEN];
 182        int len;
 183};
 184
 185enum spinand_readid_method {
 186        SPINAND_READID_METHOD_OPCODE,
 187        SPINAND_READID_METHOD_OPCODE_ADDR,
 188        SPINAND_READID_METHOD_OPCODE_DUMMY,
 189};
 190
 191/**
 192 * struct spinand_devid - SPI NAND device id structure
 193 * @id: device id of current chip
 194 * @len: number of bytes in device id
 195 * @method: method to read chip id
 196 *          There are 3 possible variants:
 197 *          SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
 198 *          after read_id opcode.
 199 *          SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
 200 *          read_id opcode + 1-byte address.
 201 *          SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
 202 *          read_id opcode + 1 dummy byte.
 203 */
 204struct spinand_devid {
 205        const u8 *id;
 206        const u8 len;
 207        const enum spinand_readid_method method;
 208};
 209
 210/**
 211 * struct manufacurer_ops - SPI NAND manufacturer specific operations
 212 * @init: initialize a SPI NAND device
 213 * @cleanup: cleanup a SPI NAND device
 214 *
 215 * Each SPI NAND manufacturer driver should implement this interface so that
 216 * NAND chips coming from this vendor can be initialized properly.
 217 */
 218struct spinand_manufacturer_ops {
 219        int (*init)(struct spinand_device *spinand);
 220        void (*cleanup)(struct spinand_device *spinand);
 221};
 222
 223/**
 224 * struct spinand_manufacturer - SPI NAND manufacturer instance
 225 * @id: manufacturer ID
 226 * @name: manufacturer name
 227 * @devid_len: number of bytes in device ID
 228 * @chips: supported SPI NANDs under current manufacturer
 229 * @nchips: number of SPI NANDs available in chips array
 230 * @ops: manufacturer operations
 231 */
 232struct spinand_manufacturer {
 233        u8 id;
 234        char *name;
 235        const struct spinand_info *chips;
 236        const size_t nchips;
 237        const struct spinand_manufacturer_ops *ops;
 238};
 239
 240/* SPI NAND manufacturers */
 241extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
 242extern const struct spinand_manufacturer macronix_spinand_manufacturer;
 243extern const struct spinand_manufacturer micron_spinand_manufacturer;
 244extern const struct spinand_manufacturer paragon_spinand_manufacturer;
 245extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
 246extern const struct spinand_manufacturer winbond_spinand_manufacturer;
 247
 248/**
 249 * struct spinand_op_variants - SPI NAND operation variants
 250 * @ops: the list of variants for a given operation
 251 * @nops: the number of variants
 252 *
 253 * Some operations like read-from-cache/write-to-cache have several variants
 254 * depending on the number of IO lines you use to transfer data or address
 255 * cycles. This structure is a way to describe the different variants supported
 256 * by a chip and let the core pick the best one based on the SPI mem controller
 257 * capabilities.
 258 */
 259struct spinand_op_variants {
 260        const struct spi_mem_op *ops;
 261        unsigned int nops;
 262};
 263
 264#define SPINAND_OP_VARIANTS(name, ...)                                  \
 265        const struct spinand_op_variants name = {                       \
 266                .ops = (struct spi_mem_op[]) { __VA_ARGS__ },           \
 267                .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) /  \
 268                        sizeof(struct spi_mem_op),                      \
 269        }
 270
 271/**
 272 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
 273 *                    chip
 274 * @get_status: get the ECC status. Should return a positive number encoding
 275 *              the number of corrected bitflips if correction was possible or
 276 *              -EBADMSG if there are uncorrectable errors. I can also return
 277 *              other negative error codes if the error is not caused by
 278 *              uncorrectable bitflips
 279 * @ooblayout: the OOB layout used by the on-die ECC implementation
 280 */
 281struct spinand_ecc_info {
 282        int (*get_status)(struct spinand_device *spinand, u8 status);
 283        const struct mtd_ooblayout_ops *ooblayout;
 284};
 285
 286#define SPINAND_HAS_QE_BIT              BIT(0)
 287#define SPINAND_HAS_CR_FEAT_BIT         BIT(1)
 288
 289/**
 290 * struct spinand_info - Structure used to describe SPI NAND chips
 291 * @model: model name
 292 * @devid: device ID
 293 * @flags: OR-ing of the SPINAND_XXX flags
 294 * @memorg: memory organization
 295 * @eccreq: ECC requirements
 296 * @eccinfo: on-die ECC info
 297 * @op_variants: operations variants
 298 * @op_variants.read_cache: variants of the read-cache operation
 299 * @op_variants.write_cache: variants of the write-cache operation
 300 * @op_variants.update_cache: variants of the update-cache operation
 301 * @select_target: function used to select a target/die. Required only for
 302 *                 multi-die chips
 303 *
 304 * Each SPI NAND manufacturer driver should have a spinand_info table
 305 * describing all the chips supported by the driver.
 306 */
 307struct spinand_info {
 308        const char *model;
 309        struct spinand_devid devid;
 310        u32 flags;
 311        struct nand_memory_organization memorg;
 312        struct nand_ecc_req eccreq;
 313        struct spinand_ecc_info eccinfo;
 314        struct {
 315                const struct spinand_op_variants *read_cache;
 316                const struct spinand_op_variants *write_cache;
 317                const struct spinand_op_variants *update_cache;
 318        } op_variants;
 319        int (*select_target)(struct spinand_device *spinand,
 320                             unsigned int target);
 321};
 322
 323#define SPINAND_ID(__method, ...)                                       \
 324        {                                                               \
 325                .id = (const u8[]){ __VA_ARGS__ },                      \
 326                .len = sizeof((u8[]){ __VA_ARGS__ }),                   \
 327                .method = __method,                                     \
 328        }
 329
 330#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)             \
 331        {                                                               \
 332                .read_cache = __read,                                   \
 333                .write_cache = __write,                                 \
 334                .update_cache = __update,                               \
 335        }
 336
 337#define SPINAND_ECCINFO(__ooblayout, __get_status)                      \
 338        .eccinfo = {                                                    \
 339                .ooblayout = __ooblayout,                               \
 340                .get_status = __get_status,                             \
 341        }
 342
 343#define SPINAND_SELECT_TARGET(__func)                                   \
 344        .select_target = __func,
 345
 346#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants,  \
 347                     __flags, ...)                                      \
 348        {                                                               \
 349                .model = __model,                                       \
 350                .devid = __id,                                          \
 351                .memorg = __memorg,                                     \
 352                .eccreq = __eccreq,                                     \
 353                .op_variants = __op_variants,                           \
 354                .flags = __flags,                                       \
 355                __VA_ARGS__                                             \
 356        }
 357
 358struct spinand_dirmap {
 359        struct spi_mem_dirmap_desc *wdesc;
 360        struct spi_mem_dirmap_desc *rdesc;
 361};
 362
 363/**
 364 * struct spinand_device - SPI NAND device instance
 365 * @base: NAND device instance
 366 * @spimem: pointer to the SPI mem object
 367 * @lock: lock used to serialize accesses to the NAND
 368 * @id: NAND ID as returned by READ_ID
 369 * @flags: NAND flags
 370 * @op_templates: various SPI mem op templates
 371 * @op_templates.read_cache: read cache op template
 372 * @op_templates.write_cache: write cache op template
 373 * @op_templates.update_cache: update cache op template
 374 * @select_target: select a specific target/die. Usually called before sending
 375 *                 a command addressing a page or an eraseblock embedded in
 376 *                 this die. Only required if your chip exposes several dies
 377 * @cur_target: currently selected target/die
 378 * @eccinfo: on-die ECC information
 379 * @cfg_cache: config register cache. One entry per die
 380 * @databuf: bounce buffer for data
 381 * @oobbuf: bounce buffer for OOB data
 382 * @scratchbuf: buffer used for everything but page accesses. This is needed
 383 *              because the spi-mem interface explicitly requests that buffers
 384 *              passed in spi_mem_op be DMA-able, so we can't based the bufs on
 385 *              the stack
 386 * @manufacturer: SPI NAND manufacturer information
 387 * @priv: manufacturer private data
 388 */
 389struct spinand_device {
 390        struct nand_device base;
 391        struct spi_mem *spimem;
 392        struct mutex lock;
 393        struct spinand_id id;
 394        u32 flags;
 395
 396        struct {
 397                const struct spi_mem_op *read_cache;
 398                const struct spi_mem_op *write_cache;
 399                const struct spi_mem_op *update_cache;
 400        } op_templates;
 401
 402        struct spinand_dirmap *dirmaps;
 403
 404        int (*select_target)(struct spinand_device *spinand,
 405                             unsigned int target);
 406        unsigned int cur_target;
 407
 408        struct spinand_ecc_info eccinfo;
 409
 410        u8 *cfg_cache;
 411        u8 *databuf;
 412        u8 *oobbuf;
 413        u8 *scratchbuf;
 414        const struct spinand_manufacturer *manufacturer;
 415        void *priv;
 416};
 417
 418/**
 419 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
 420 * @mtd: MTD instance
 421 *
 422 * Return: the SPI NAND device attached to @mtd.
 423 */
 424static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
 425{
 426        return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
 427}
 428
 429/**
 430 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
 431 * @spinand: SPI NAND device
 432 *
 433 * Return: the MTD device embedded in @spinand.
 434 */
 435static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
 436{
 437        return nanddev_to_mtd(&spinand->base);
 438}
 439
 440/**
 441 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
 442 * @nand: NAND object
 443 *
 444 * Return: the SPI NAND device embedding @nand.
 445 */
 446static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
 447{
 448        return container_of(nand, struct spinand_device, base);
 449}
 450
 451/**
 452 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
 453 * @spinand: SPI NAND device
 454 *
 455 * Return: the NAND device embedded in @spinand.
 456 */
 457static inline struct nand_device *
 458spinand_to_nand(struct spinand_device *spinand)
 459{
 460        return &spinand->base;
 461}
 462
 463/**
 464 * spinand_set_of_node - Attach a DT node to a SPI NAND device
 465 * @spinand: SPI NAND device
 466 * @np: DT node
 467 *
 468 * Attach a DT node to a SPI NAND device.
 469 */
 470static inline void spinand_set_of_node(struct spinand_device *spinand,
 471                                       struct device_node *np)
 472{
 473        nanddev_set_of_node(&spinand->base, np);
 474}
 475
 476int spinand_match_and_init(struct spinand_device *spinand,
 477                           const struct spinand_info *table,
 478                           unsigned int table_size,
 479                           enum spinand_readid_method rdid_method);
 480
 481int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
 482int spinand_select_target(struct spinand_device *spinand, unsigned int target);
 483
 484#endif /* __LINUX_MTD_SPINAND_H */
 485