1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15#ifndef _UAPI_LINUX_PERF_EVENT_H 16#define _UAPI_LINUX_PERF_EVENT_H 17 18#include <linux/types.h> 19#include <linux/ioctl.h> 20#include <asm/byteorder.h> 21 22/* 23 * User-space ABI bits: 24 */ 25 26/* 27 * attr.type 28 */ 29enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38}; 39 40/* 41 * Generalized performance event event_id types, used by the 42 * attr.event_id parameter of the sys_perf_event_open() 43 * syscall: 44 */ 45enum perf_hw_id { 46 /* 47 * Common hardware events, generalized by the kernel: 48 */ 49 PERF_COUNT_HW_CPU_CYCLES = 0, 50 PERF_COUNT_HW_INSTRUCTIONS = 1, 51 PERF_COUNT_HW_CACHE_REFERENCES = 2, 52 PERF_COUNT_HW_CACHE_MISSES = 3, 53 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 54 PERF_COUNT_HW_BRANCH_MISSES = 5, 55 PERF_COUNT_HW_BUS_CYCLES = 6, 56 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 57 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 58 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 59 60 PERF_COUNT_HW_MAX, /* non-ABI */ 61}; 62 63/* 64 * Generalized hardware cache events: 65 * 66 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 67 * { read, write, prefetch } x 68 * { accesses, misses } 69 */ 70enum perf_hw_cache_id { 71 PERF_COUNT_HW_CACHE_L1D = 0, 72 PERF_COUNT_HW_CACHE_L1I = 1, 73 PERF_COUNT_HW_CACHE_LL = 2, 74 PERF_COUNT_HW_CACHE_DTLB = 3, 75 PERF_COUNT_HW_CACHE_ITLB = 4, 76 PERF_COUNT_HW_CACHE_BPU = 5, 77 PERF_COUNT_HW_CACHE_NODE = 6, 78 79 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 80}; 81 82enum perf_hw_cache_op_id { 83 PERF_COUNT_HW_CACHE_OP_READ = 0, 84 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 85 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 86 87 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 88}; 89 90enum perf_hw_cache_op_result_id { 91 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 92 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 93 94 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 95}; 96 97/* 98 * Special "software" events provided by the kernel, even if the hardware 99 * does not support performance events. These events measure various 100 * physical and sw events of the kernel (and allow the profiling of them as 101 * well): 102 */ 103enum perf_sw_ids { 104 PERF_COUNT_SW_CPU_CLOCK = 0, 105 PERF_COUNT_SW_TASK_CLOCK = 1, 106 PERF_COUNT_SW_PAGE_FAULTS = 2, 107 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 108 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 109 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 110 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 111 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 112 PERF_COUNT_SW_EMULATION_FAULTS = 8, 113 PERF_COUNT_SW_DUMMY = 9, 114 PERF_COUNT_SW_BPF_OUTPUT = 10, 115 116 PERF_COUNT_SW_MAX, /* non-ABI */ 117}; 118 119/* 120 * Bits that can be set in attr.sample_type to request information 121 * in the overflow packets. 122 */ 123enum perf_event_sample_format { 124 PERF_SAMPLE_IP = 1U << 0, 125 PERF_SAMPLE_TID = 1U << 1, 126 PERF_SAMPLE_TIME = 1U << 2, 127 PERF_SAMPLE_ADDR = 1U << 3, 128 PERF_SAMPLE_READ = 1U << 4, 129 PERF_SAMPLE_CALLCHAIN = 1U << 5, 130 PERF_SAMPLE_ID = 1U << 6, 131 PERF_SAMPLE_CPU = 1U << 7, 132 PERF_SAMPLE_PERIOD = 1U << 8, 133 PERF_SAMPLE_STREAM_ID = 1U << 9, 134 PERF_SAMPLE_RAW = 1U << 10, 135 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 136 PERF_SAMPLE_REGS_USER = 1U << 12, 137 PERF_SAMPLE_STACK_USER = 1U << 13, 138 PERF_SAMPLE_WEIGHT = 1U << 14, 139 PERF_SAMPLE_DATA_SRC = 1U << 15, 140 PERF_SAMPLE_IDENTIFIER = 1U << 16, 141 PERF_SAMPLE_TRANSACTION = 1U << 17, 142 PERF_SAMPLE_REGS_INTR = 1U << 18, 143 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 144 PERF_SAMPLE_AUX = 1U << 20, 145 PERF_SAMPLE_CGROUP = 1U << 21, 146 147 PERF_SAMPLE_MAX = 1U << 22, /* non-ABI */ 148 149 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 150}; 151 152/* 153 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 154 * 155 * If the user does not pass priv level information via branch_sample_type, 156 * the kernel uses the event's priv level. Branch and event priv levels do 157 * not have to match. Branch priv level is checked for permissions. 158 * 159 * The branch types can be combined, however BRANCH_ANY covers all types 160 * of branches and therefore it supersedes all the other types. 161 */ 162enum perf_branch_sample_type_shift { 163 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 164 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 165 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 166 167 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 168 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 169 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 170 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 171 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 172 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 173 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 174 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 175 176 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 177 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 178 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 179 180 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 181 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 182 183 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 184 185 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 186 187 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 188}; 189 190enum perf_branch_sample_type { 191 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 192 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 193 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 194 195 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 196 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 197 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 198 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 199 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 200 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 201 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 202 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 203 204 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 205 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 206 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 207 208 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 209 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 210 211 PERF_SAMPLE_BRANCH_TYPE_SAVE = 212 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 213 214 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 215 216 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 217}; 218 219/* 220 * Common flow change classification 221 */ 222enum { 223 PERF_BR_UNKNOWN = 0, /* unknown */ 224 PERF_BR_COND = 1, /* conditional */ 225 PERF_BR_UNCOND = 2, /* unconditional */ 226 PERF_BR_IND = 3, /* indirect */ 227 PERF_BR_CALL = 4, /* function call */ 228 PERF_BR_IND_CALL = 5, /* indirect function call */ 229 PERF_BR_RET = 6, /* function return */ 230 PERF_BR_SYSCALL = 7, /* syscall */ 231 PERF_BR_SYSRET = 8, /* syscall return */ 232 PERF_BR_COND_CALL = 9, /* conditional function call */ 233 PERF_BR_COND_RET = 10, /* conditional function return */ 234 PERF_BR_MAX, 235}; 236 237#define PERF_SAMPLE_BRANCH_PLM_ALL \ 238 (PERF_SAMPLE_BRANCH_USER|\ 239 PERF_SAMPLE_BRANCH_KERNEL|\ 240 PERF_SAMPLE_BRANCH_HV) 241 242/* 243 * Values to determine ABI of the registers dump. 244 */ 245enum perf_sample_regs_abi { 246 PERF_SAMPLE_REGS_ABI_NONE = 0, 247 PERF_SAMPLE_REGS_ABI_32 = 1, 248 PERF_SAMPLE_REGS_ABI_64 = 2, 249}; 250 251/* 252 * Values for the memory transaction event qualifier, mostly for 253 * abort events. Multiple bits can be set. 254 */ 255enum { 256 PERF_TXN_ELISION = (1 << 0), /* From elision */ 257 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 258 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 259 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 260 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 261 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 262 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 263 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 264 265 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 266 267 /* bits 32..63 are reserved for the abort code */ 268 269 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 270 PERF_TXN_ABORT_SHIFT = 32, 271}; 272 273/* 274 * The format of the data returned by read() on a perf event fd, 275 * as specified by attr.read_format: 276 * 277 * struct read_format { 278 * { u64 value; 279 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 280 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 281 * { u64 id; } && PERF_FORMAT_ID 282 * } && !PERF_FORMAT_GROUP 283 * 284 * { u64 nr; 285 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 286 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 287 * { u64 value; 288 * { u64 id; } && PERF_FORMAT_ID 289 * } cntr[nr]; 290 * } && PERF_FORMAT_GROUP 291 * }; 292 */ 293enum perf_event_read_format { 294 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 295 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 296 PERF_FORMAT_ID = 1U << 2, 297 PERF_FORMAT_GROUP = 1U << 3, 298 299 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 300}; 301 302#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 303#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 304#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 305#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 306 /* add: sample_stack_user */ 307#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 308#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 309#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 310 311/* 312 * Hardware event_id to monitor via a performance monitoring event: 313 * 314 * @sample_max_stack: Max number of frame pointers in a callchain, 315 * should be < /proc/sys/kernel/perf_event_max_stack 316 */ 317struct perf_event_attr { 318 319 /* 320 * Major type: hardware/software/tracepoint/etc. 321 */ 322 __u32 type; 323 324 /* 325 * Size of the attr structure, for fwd/bwd compat. 326 */ 327 __u32 size; 328 329 /* 330 * Type specific configuration information. 331 */ 332 __u64 config; 333 334 union { 335 __u64 sample_period; 336 __u64 sample_freq; 337 }; 338 339 __u64 sample_type; 340 __u64 read_format; 341 342 __u64 disabled : 1, /* off by default */ 343 inherit : 1, /* children inherit it */ 344 pinned : 1, /* must always be on PMU */ 345 exclusive : 1, /* only group on PMU */ 346 exclude_user : 1, /* don't count user */ 347 exclude_kernel : 1, /* ditto kernel */ 348 exclude_hv : 1, /* ditto hypervisor */ 349 exclude_idle : 1, /* don't count when idle */ 350 mmap : 1, /* include mmap data */ 351 comm : 1, /* include comm data */ 352 freq : 1, /* use freq, not period */ 353 inherit_stat : 1, /* per task counts */ 354 enable_on_exec : 1, /* next exec enables */ 355 task : 1, /* trace fork/exit */ 356 watermark : 1, /* wakeup_watermark */ 357 /* 358 * precise_ip: 359 * 360 * 0 - SAMPLE_IP can have arbitrary skid 361 * 1 - SAMPLE_IP must have constant skid 362 * 2 - SAMPLE_IP requested to have 0 skid 363 * 3 - SAMPLE_IP must have 0 skid 364 * 365 * See also PERF_RECORD_MISC_EXACT_IP 366 */ 367 precise_ip : 2, /* skid constraint */ 368 mmap_data : 1, /* non-exec mmap data */ 369 sample_id_all : 1, /* sample_type all events */ 370 371 exclude_host : 1, /* don't count in host */ 372 exclude_guest : 1, /* don't count in guest */ 373 374 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 375 exclude_callchain_user : 1, /* exclude user callchains */ 376 mmap2 : 1, /* include mmap with inode data */ 377 comm_exec : 1, /* flag comm events that are due to an exec */ 378 use_clockid : 1, /* use @clockid for time fields */ 379 context_switch : 1, /* context switch data */ 380 write_backward : 1, /* Write ring buffer from end to beginning */ 381 namespaces : 1, /* include namespaces data */ 382 ksymbol : 1, /* include ksymbol events */ 383 bpf_event : 1, /* include bpf events */ 384 aux_output : 1, /* generate AUX records instead of events */ 385 cgroup : 1, /* include cgroup events */ 386 __reserved_1 : 31; 387 388 union { 389 __u32 wakeup_events; /* wakeup every n events */ 390 __u32 wakeup_watermark; /* bytes before wakeup */ 391 }; 392 393 __u32 bp_type; 394 union { 395 __u64 bp_addr; 396 __u64 kprobe_func; /* for perf_kprobe */ 397 __u64 uprobe_path; /* for perf_uprobe */ 398 __u64 config1; /* extension of config */ 399 }; 400 union { 401 __u64 bp_len; 402 __u64 kprobe_addr; /* when kprobe_func == NULL */ 403 __u64 probe_offset; /* for perf_[k,u]probe */ 404 __u64 config2; /* extension of config1 */ 405 }; 406 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 407 408 /* 409 * Defines set of user regs to dump on samples. 410 * See asm/perf_regs.h for details. 411 */ 412 __u64 sample_regs_user; 413 414 /* 415 * Defines size of the user stack to dump on samples. 416 */ 417 __u32 sample_stack_user; 418 419 __s32 clockid; 420 /* 421 * Defines set of regs to dump for each sample 422 * state captured on: 423 * - precise = 0: PMU interrupt 424 * - precise > 0: sampled instruction 425 * 426 * See asm/perf_regs.h for details. 427 */ 428 __u64 sample_regs_intr; 429 430 /* 431 * Wakeup watermark for AUX area 432 */ 433 __u32 aux_watermark; 434 __u16 sample_max_stack; 435 __u16 __reserved_2; 436 __u32 aux_sample_size; 437 __u32 __reserved_3; 438}; 439 440/* 441 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 442 * to query bpf programs attached to the same perf tracepoint 443 * as the given perf event. 444 */ 445struct perf_event_query_bpf { 446 /* 447 * The below ids array length 448 */ 449 __u32 ids_len; 450 /* 451 * Set by the kernel to indicate the number of 452 * available programs 453 */ 454 __u32 prog_cnt; 455 /* 456 * User provided buffer to store program ids 457 */ 458 __u32 ids[0]; 459}; 460 461/* 462 * Ioctls that can be done on a perf event fd: 463 */ 464#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 465#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 466#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 467#define PERF_EVENT_IOC_RESET _IO ('$', 3) 468#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 469#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 470#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 471#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 472#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 473#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 474#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 475#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 476 477enum perf_event_ioc_flags { 478 PERF_IOC_FLAG_GROUP = 1U << 0, 479}; 480 481/* 482 * Structure of the page that can be mapped via mmap 483 */ 484struct perf_event_mmap_page { 485 __u32 version; /* version number of this structure */ 486 __u32 compat_version; /* lowest version this is compat with */ 487 488 /* 489 * Bits needed to read the hw events in user-space. 490 * 491 * u32 seq, time_mult, time_shift, index, width; 492 * u64 count, enabled, running; 493 * u64 cyc, time_offset; 494 * s64 pmc = 0; 495 * 496 * do { 497 * seq = pc->lock; 498 * barrier() 499 * 500 * enabled = pc->time_enabled; 501 * running = pc->time_running; 502 * 503 * if (pc->cap_usr_time && enabled != running) { 504 * cyc = rdtsc(); 505 * time_offset = pc->time_offset; 506 * time_mult = pc->time_mult; 507 * time_shift = pc->time_shift; 508 * } 509 * 510 * index = pc->index; 511 * count = pc->offset; 512 * if (pc->cap_user_rdpmc && index) { 513 * width = pc->pmc_width; 514 * pmc = rdpmc(index - 1); 515 * } 516 * 517 * barrier(); 518 * } while (pc->lock != seq); 519 * 520 * NOTE: for obvious reason this only works on self-monitoring 521 * processes. 522 */ 523 __u32 lock; /* seqlock for synchronization */ 524 __u32 index; /* hardware event identifier */ 525 __s64 offset; /* add to hardware event value */ 526 __u64 time_enabled; /* time event active */ 527 __u64 time_running; /* time event on cpu */ 528 union { 529 __u64 capabilities; 530 struct { 531 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 532 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 533 534 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 535 cap_user_time : 1, /* The time_* fields are used */ 536 cap_user_time_zero : 1, /* The time_zero field is used */ 537 cap_____res : 59; 538 }; 539 }; 540 541 /* 542 * If cap_user_rdpmc this field provides the bit-width of the value 543 * read using the rdpmc() or equivalent instruction. This can be used 544 * to sign extend the result like: 545 * 546 * pmc <<= 64 - width; 547 * pmc >>= 64 - width; // signed shift right 548 * count += pmc; 549 */ 550 __u16 pmc_width; 551 552 /* 553 * If cap_usr_time the below fields can be used to compute the time 554 * delta since time_enabled (in ns) using rdtsc or similar. 555 * 556 * u64 quot, rem; 557 * u64 delta; 558 * 559 * quot = (cyc >> time_shift); 560 * rem = cyc & (((u64)1 << time_shift) - 1); 561 * delta = time_offset + quot * time_mult + 562 * ((rem * time_mult) >> time_shift); 563 * 564 * Where time_offset,time_mult,time_shift and cyc are read in the 565 * seqcount loop described above. This delta can then be added to 566 * enabled and possible running (if index), improving the scaling: 567 * 568 * enabled += delta; 569 * if (index) 570 * running += delta; 571 * 572 * quot = count / running; 573 * rem = count % running; 574 * count = quot * enabled + (rem * enabled) / running; 575 */ 576 __u16 time_shift; 577 __u32 time_mult; 578 __u64 time_offset; 579 /* 580 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 581 * from sample timestamps. 582 * 583 * time = timestamp - time_zero; 584 * quot = time / time_mult; 585 * rem = time % time_mult; 586 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 587 * 588 * And vice versa: 589 * 590 * quot = cyc >> time_shift; 591 * rem = cyc & (((u64)1 << time_shift) - 1); 592 * timestamp = time_zero + quot * time_mult + 593 * ((rem * time_mult) >> time_shift); 594 */ 595 __u64 time_zero; 596 __u32 size; /* Header size up to __reserved[] fields. */ 597 598 /* 599 * Hole for extension of the self monitor capabilities 600 */ 601 602 __u8 __reserved[118*8+4]; /* align to 1k. */ 603 604 /* 605 * Control data for the mmap() data buffer. 606 * 607 * User-space reading the @data_head value should issue an smp_rmb(), 608 * after reading this value. 609 * 610 * When the mapping is PROT_WRITE the @data_tail value should be 611 * written by userspace to reflect the last read data, after issueing 612 * an smp_mb() to separate the data read from the ->data_tail store. 613 * In this case the kernel will not over-write unread data. 614 * 615 * See perf_output_put_handle() for the data ordering. 616 * 617 * data_{offset,size} indicate the location and size of the perf record 618 * buffer within the mmapped area. 619 */ 620 __u64 data_head; /* head in the data section */ 621 __u64 data_tail; /* user-space written tail */ 622 __u64 data_offset; /* where the buffer starts */ 623 __u64 data_size; /* data buffer size */ 624 625 /* 626 * AUX area is defined by aux_{offset,size} fields that should be set 627 * by the userspace, so that 628 * 629 * aux_offset >= data_offset + data_size 630 * 631 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 632 * 633 * Ring buffer pointers aux_{head,tail} have the same semantics as 634 * data_{head,tail} and same ordering rules apply. 635 */ 636 __u64 aux_head; 637 __u64 aux_tail; 638 __u64 aux_offset; 639 __u64 aux_size; 640}; 641 642#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 643#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 644#define PERF_RECORD_MISC_KERNEL (1 << 0) 645#define PERF_RECORD_MISC_USER (2 << 0) 646#define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 647#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 648#define PERF_RECORD_MISC_GUEST_USER (5 << 0) 649 650/* 651 * Indicates that /proc/PID/maps parsing are truncated by time out. 652 */ 653#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 654/* 655 * Following PERF_RECORD_MISC_* are used on different 656 * events, so can reuse the same bit position: 657 * 658 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 659 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 660 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 661 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 662 */ 663#define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 664#define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 665#define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 666#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 667/* 668 * These PERF_RECORD_MISC_* flags below are safely reused 669 * for the following events: 670 * 671 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 672 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 673 * 674 * 675 * PERF_RECORD_MISC_EXACT_IP: 676 * Indicates that the content of PERF_SAMPLE_IP points to 677 * the actual instruction that triggered the event. See also 678 * perf_event_attr::precise_ip. 679 * 680 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 681 * Indicates that thread was preempted in TASK_RUNNING state. 682 */ 683#define PERF_RECORD_MISC_EXACT_IP (1 << 14) 684#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 685/* 686 * Reserve the last bit to indicate some extended misc field 687 */ 688#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 689 690struct perf_event_header { 691 __u32 type; 692 __u16 misc; 693 __u16 size; 694}; 695 696struct perf_ns_link_info { 697 __u64 dev; 698 __u64 ino; 699}; 700 701enum { 702 NET_NS_INDEX = 0, 703 UTS_NS_INDEX = 1, 704 IPC_NS_INDEX = 2, 705 PID_NS_INDEX = 3, 706 USER_NS_INDEX = 4, 707 MNT_NS_INDEX = 5, 708 CGROUP_NS_INDEX = 6, 709 710 NR_NAMESPACES, /* number of available namespaces */ 711}; 712 713enum perf_event_type { 714 715 /* 716 * If perf_event_attr.sample_id_all is set then all event types will 717 * have the sample_type selected fields related to where/when 718 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 719 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 720 * just after the perf_event_header and the fields already present for 721 * the existing fields, i.e. at the end of the payload. That way a newer 722 * perf.data file will be supported by older perf tools, with these new 723 * optional fields being ignored. 724 * 725 * struct sample_id { 726 * { u32 pid, tid; } && PERF_SAMPLE_TID 727 * { u64 time; } && PERF_SAMPLE_TIME 728 * { u64 id; } && PERF_SAMPLE_ID 729 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 730 * { u32 cpu, res; } && PERF_SAMPLE_CPU 731 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 732 * } && perf_event_attr::sample_id_all 733 * 734 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 735 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 736 * relative to header.size. 737 */ 738 739 /* 740 * The MMAP events record the PROT_EXEC mappings so that we can 741 * correlate userspace IPs to code. They have the following structure: 742 * 743 * struct { 744 * struct perf_event_header header; 745 * 746 * u32 pid, tid; 747 * u64 addr; 748 * u64 len; 749 * u64 pgoff; 750 * char filename[]; 751 * struct sample_id sample_id; 752 * }; 753 */ 754 PERF_RECORD_MMAP = 1, 755 756 /* 757 * struct { 758 * struct perf_event_header header; 759 * u64 id; 760 * u64 lost; 761 * struct sample_id sample_id; 762 * }; 763 */ 764 PERF_RECORD_LOST = 2, 765 766 /* 767 * struct { 768 * struct perf_event_header header; 769 * 770 * u32 pid, tid; 771 * char comm[]; 772 * struct sample_id sample_id; 773 * }; 774 */ 775 PERF_RECORD_COMM = 3, 776 777 /* 778 * struct { 779 * struct perf_event_header header; 780 * u32 pid, ppid; 781 * u32 tid, ptid; 782 * u64 time; 783 * struct sample_id sample_id; 784 * }; 785 */ 786 PERF_RECORD_EXIT = 4, 787 788 /* 789 * struct { 790 * struct perf_event_header header; 791 * u64 time; 792 * u64 id; 793 * u64 stream_id; 794 * struct sample_id sample_id; 795 * }; 796 */ 797 PERF_RECORD_THROTTLE = 5, 798 PERF_RECORD_UNTHROTTLE = 6, 799 800 /* 801 * struct { 802 * struct perf_event_header header; 803 * u32 pid, ppid; 804 * u32 tid, ptid; 805 * u64 time; 806 * struct sample_id sample_id; 807 * }; 808 */ 809 PERF_RECORD_FORK = 7, 810 811 /* 812 * struct { 813 * struct perf_event_header header; 814 * u32 pid, tid; 815 * 816 * struct read_format values; 817 * struct sample_id sample_id; 818 * }; 819 */ 820 PERF_RECORD_READ = 8, 821 822 /* 823 * struct { 824 * struct perf_event_header header; 825 * 826 * # 827 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 828 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 829 * # is fixed relative to header. 830 * # 831 * 832 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 833 * { u64 ip; } && PERF_SAMPLE_IP 834 * { u32 pid, tid; } && PERF_SAMPLE_TID 835 * { u64 time; } && PERF_SAMPLE_TIME 836 * { u64 addr; } && PERF_SAMPLE_ADDR 837 * { u64 id; } && PERF_SAMPLE_ID 838 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 839 * { u32 cpu, res; } && PERF_SAMPLE_CPU 840 * { u64 period; } && PERF_SAMPLE_PERIOD 841 * 842 * { struct read_format values; } && PERF_SAMPLE_READ 843 * 844 * { u64 nr, 845 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 846 * 847 * # 848 * # The RAW record below is opaque data wrt the ABI 849 * # 850 * # That is, the ABI doesn't make any promises wrt to 851 * # the stability of its content, it may vary depending 852 * # on event, hardware, kernel version and phase of 853 * # the moon. 854 * # 855 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 856 * # 857 * 858 * { u32 size; 859 * char data[size];}&& PERF_SAMPLE_RAW 860 * 861 * { u64 nr; 862 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 863 * { u64 from, to, flags } lbr[nr]; 864 * } && PERF_SAMPLE_BRANCH_STACK 865 * 866 * { u64 abi; # enum perf_sample_regs_abi 867 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 868 * 869 * { u64 size; 870 * char data[size]; 871 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 872 * 873 * { u64 weight; } && PERF_SAMPLE_WEIGHT 874 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 875 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 876 * { u64 abi; # enum perf_sample_regs_abi 877 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 878 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 879 * { u64 size; 880 * char data[size]; } && PERF_SAMPLE_AUX 881 * }; 882 */ 883 PERF_RECORD_SAMPLE = 9, 884 885 /* 886 * The MMAP2 records are an augmented version of MMAP, they add 887 * maj, min, ino numbers to be used to uniquely identify each mapping 888 * 889 * struct { 890 * struct perf_event_header header; 891 * 892 * u32 pid, tid; 893 * u64 addr; 894 * u64 len; 895 * u64 pgoff; 896 * u32 maj; 897 * u32 min; 898 * u64 ino; 899 * u64 ino_generation; 900 * u32 prot, flags; 901 * char filename[]; 902 * struct sample_id sample_id; 903 * }; 904 */ 905 PERF_RECORD_MMAP2 = 10, 906 907 /* 908 * Records that new data landed in the AUX buffer part. 909 * 910 * struct { 911 * struct perf_event_header header; 912 * 913 * u64 aux_offset; 914 * u64 aux_size; 915 * u64 flags; 916 * struct sample_id sample_id; 917 * }; 918 */ 919 PERF_RECORD_AUX = 11, 920 921 /* 922 * Indicates that instruction trace has started 923 * 924 * struct { 925 * struct perf_event_header header; 926 * u32 pid; 927 * u32 tid; 928 * struct sample_id sample_id; 929 * }; 930 */ 931 PERF_RECORD_ITRACE_START = 12, 932 933 /* 934 * Records the dropped/lost sample number. 935 * 936 * struct { 937 * struct perf_event_header header; 938 * 939 * u64 lost; 940 * struct sample_id sample_id; 941 * }; 942 */ 943 PERF_RECORD_LOST_SAMPLES = 13, 944 945 /* 946 * Records a context switch in or out (flagged by 947 * PERF_RECORD_MISC_SWITCH_OUT). See also 948 * PERF_RECORD_SWITCH_CPU_WIDE. 949 * 950 * struct { 951 * struct perf_event_header header; 952 * struct sample_id sample_id; 953 * }; 954 */ 955 PERF_RECORD_SWITCH = 14, 956 957 /* 958 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 959 * next_prev_tid that are the next (switching out) or previous 960 * (switching in) pid/tid. 961 * 962 * struct { 963 * struct perf_event_header header; 964 * u32 next_prev_pid; 965 * u32 next_prev_tid; 966 * struct sample_id sample_id; 967 * }; 968 */ 969 PERF_RECORD_SWITCH_CPU_WIDE = 15, 970 971 /* 972 * struct { 973 * struct perf_event_header header; 974 * u32 pid; 975 * u32 tid; 976 * u64 nr_namespaces; 977 * { u64 dev, inode; } [nr_namespaces]; 978 * struct sample_id sample_id; 979 * }; 980 */ 981 PERF_RECORD_NAMESPACES = 16, 982 983 /* 984 * Record ksymbol register/unregister events: 985 * 986 * struct { 987 * struct perf_event_header header; 988 * u64 addr; 989 * u32 len; 990 * u16 ksym_type; 991 * u16 flags; 992 * char name[]; 993 * struct sample_id sample_id; 994 * }; 995 */ 996 PERF_RECORD_KSYMBOL = 17, 997 998 /* 999 * Record bpf events: 1000 * enum perf_bpf_event_type {
1001 * PERF_BPF_EVENT_UNKNOWN = 0, 1002 * PERF_BPF_EVENT_PROG_LOAD = 1, 1003 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1004 * }; 1005 * 1006 * struct { 1007 * struct perf_event_header header; 1008 * u16 type; 1009 * u16 flags; 1010 * u32 id; 1011 * u8 tag[BPF_TAG_SIZE]; 1012 * struct sample_id sample_id; 1013 * }; 1014 */ 1015 PERF_RECORD_BPF_EVENT = 18, 1016 1017 /* 1018 * struct { 1019 * struct perf_event_header header; 1020 * u64 id; 1021 * char path[]; 1022 * struct sample_id sample_id; 1023 * }; 1024 */ 1025 PERF_RECORD_CGROUP = 19, 1026 1027 PERF_RECORD_MAX, /* non-ABI */ 1028}; 1029 1030enum perf_record_ksymbol_type { 1031 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1032 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1033 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1034}; 1035 1036#define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1037 1038enum perf_bpf_event_type { 1039 PERF_BPF_EVENT_UNKNOWN = 0, 1040 PERF_BPF_EVENT_PROG_LOAD = 1, 1041 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1042 PERF_BPF_EVENT_MAX, /* non-ABI */ 1043}; 1044 1045#define PERF_MAX_STACK_DEPTH 127 1046#define PERF_MAX_CONTEXTS_PER_STACK 8 1047 1048enum perf_callchain_context { 1049 PERF_CONTEXT_HV = (__u64)-32, 1050 PERF_CONTEXT_KERNEL = (__u64)-128, 1051 PERF_CONTEXT_USER = (__u64)-512, 1052 1053 PERF_CONTEXT_GUEST = (__u64)-2048, 1054 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1055 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1056 1057 PERF_CONTEXT_MAX = (__u64)-4095, 1058}; 1059 1060/** 1061 * PERF_RECORD_AUX::flags bits 1062 */ 1063#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1064#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1065#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1066#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1067 1068#define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1069#define PERF_FLAG_FD_OUTPUT (1UL << 1) 1070#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1071#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1072 1073#if defined(__LITTLE_ENDIAN_BITFIELD) 1074union perf_mem_data_src { 1075 __u64 val; 1076 struct { 1077 __u64 mem_op:5, /* type of opcode */ 1078 mem_lvl:14, /* memory hierarchy level */ 1079 mem_snoop:5, /* snoop mode */ 1080 mem_lock:2, /* lock instr */ 1081 mem_dtlb:7, /* tlb access */ 1082 mem_lvl_num:4, /* memory hierarchy level number */ 1083 mem_remote:1, /* remote */ 1084 mem_snoopx:2, /* snoop mode, ext */ 1085 mem_rsvd:24; 1086 }; 1087}; 1088#elif defined(__BIG_ENDIAN_BITFIELD) 1089union perf_mem_data_src { 1090 __u64 val; 1091 struct { 1092 __u64 mem_rsvd:24, 1093 mem_snoopx:2, /* snoop mode, ext */ 1094 mem_remote:1, /* remote */ 1095 mem_lvl_num:4, /* memory hierarchy level number */ 1096 mem_dtlb:7, /* tlb access */ 1097 mem_lock:2, /* lock instr */ 1098 mem_snoop:5, /* snoop mode */ 1099 mem_lvl:14, /* memory hierarchy level */ 1100 mem_op:5; /* type of opcode */ 1101 }; 1102}; 1103#else 1104#error "Unknown endianness" 1105#endif 1106 1107/* type of opcode (load/store/prefetch,code) */ 1108#define PERF_MEM_OP_NA 0x01 /* not available */ 1109#define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1110#define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1111#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1112#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1113#define PERF_MEM_OP_SHIFT 0 1114 1115/* memory hierarchy (memory level, hit or miss) */ 1116#define PERF_MEM_LVL_NA 0x01 /* not available */ 1117#define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1118#define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1119#define PERF_MEM_LVL_L1 0x08 /* L1 */ 1120#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1121#define PERF_MEM_LVL_L2 0x20 /* L2 */ 1122#define PERF_MEM_LVL_L3 0x40 /* L3 */ 1123#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1124#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1125#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1126#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1127#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1128#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1129#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1130#define PERF_MEM_LVL_SHIFT 5 1131 1132#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1133#define PERF_MEM_REMOTE_SHIFT 37 1134 1135#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1136#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1137#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1138#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1139/* 5-0xa available */ 1140#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1141#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1142#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1143#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1144#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1145 1146#define PERF_MEM_LVLNUM_SHIFT 33 1147 1148/* snoop mode */ 1149#define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1150#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1151#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1152#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1153#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1154#define PERF_MEM_SNOOP_SHIFT 19 1155 1156#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1157/* 1 free */ 1158#define PERF_MEM_SNOOPX_SHIFT 37 1159 1160/* locked instruction */ 1161#define PERF_MEM_LOCK_NA 0x01 /* not available */ 1162#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1163#define PERF_MEM_LOCK_SHIFT 24 1164 1165/* TLB access */ 1166#define PERF_MEM_TLB_NA 0x01 /* not available */ 1167#define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1168#define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1169#define PERF_MEM_TLB_L1 0x08 /* L1 */ 1170#define PERF_MEM_TLB_L2 0x10 /* L2 */ 1171#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1172#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1173#define PERF_MEM_TLB_SHIFT 26 1174 1175#define PERF_MEM_S(a, s) \ 1176 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1177 1178/* 1179 * single taken branch record layout: 1180 * 1181 * from: source instruction (may not always be a branch insn) 1182 * to: branch target 1183 * mispred: branch target was mispredicted 1184 * predicted: branch target was predicted 1185 * 1186 * support for mispred, predicted is optional. In case it 1187 * is not supported mispred = predicted = 0. 1188 * 1189 * in_tx: running in a hardware transaction 1190 * abort: aborting a hardware transaction 1191 * cycles: cycles from last branch (or 0 if not supported) 1192 * type: branch type 1193 */ 1194struct perf_branch_entry { 1195 __u64 from; 1196 __u64 to; 1197 __u64 mispred:1, /* target mispredicted */ 1198 predicted:1,/* target predicted */ 1199 in_tx:1, /* in transaction */ 1200 abort:1, /* transaction abort */ 1201 cycles:16, /* cycle count to last branch */ 1202 type:4, /* branch type */ 1203 reserved:40; 1204}; 1205 1206#endif /* _UAPI_LINUX_PERF_EVENT_H */ 1207