linux/arch/arm/mach-imx/common.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
   4 */
   5
   6
   7#ifndef __ASM_ARCH_MXC_COMMON_H__
   8#define __ASM_ARCH_MXC_COMMON_H__
   9
  10#include <linux/reboot.h>
  11
  12struct irq_data;
  13struct platform_device;
  14struct pt_regs;
  15struct clk;
  16struct device_node;
  17enum mxc_cpu_pwr_mode;
  18struct of_device_id;
  19
  20void mx21_map_io(void);
  21void mx27_map_io(void);
  22void mx31_map_io(void);
  23void mx35_map_io(void);
  24void imx21_init_early(void);
  25void imx27_init_early(void);
  26void imx31_init_early(void);
  27void imx35_init_early(void);
  28void mxc_init_irq(void __iomem *);
  29void mx21_init_irq(void);
  30void mx27_init_irq(void);
  31void mx31_init_irq(void);
  32void mx35_init_irq(void);
  33void imx21_soc_init(void);
  34void imx27_soc_init(void);
  35void imx31_soc_init(void);
  36void imx35_soc_init(void);
  37int mx21_clocks_init(unsigned long lref, unsigned long fref);
  38int mx27_clocks_init(unsigned long fref);
  39int mx31_clocks_init(unsigned long fref);
  40int mx35_clocks_init(void);
  41struct platform_device *mxc_register_gpio(char *name, int id,
  42        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
  43void mxc_set_cpu_type(unsigned int type);
  44void mxc_restart(enum reboot_mode, const char *);
  45void mxc_arch_reset_init(void __iomem *);
  46void imx1_reset_init(void __iomem *);
  47void imx_set_aips(void __iomem *);
  48void imx_aips_allow_unprivileged_access(const char *compat);
  49int mxc_device_init(void);
  50void imx_set_soc_revision(unsigned int rev);
  51void imx_init_revision_from_anatop(void);
  52void imx6_enable_rbc(bool enable);
  53void imx_gpc_check_dt(void);
  54void imx_gpc_set_arm_power_in_lpm(bool power_off);
  55void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);
  56void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
  57void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
  58void imx25_pm_init(void);
  59void imx27_pm_init(void);
  60void imx5_pmu_init(void);
  61
  62enum mxc_cpu_pwr_mode {
  63        WAIT_CLOCKED,           /* wfi only */
  64        WAIT_UNCLOCKED,         /* WAIT */
  65        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
  66        STOP_POWER_ON,          /* just STOP */
  67        STOP_POWER_OFF,         /* STOP + SRPG */
  68};
  69
  70enum ulp_cpu_pwr_mode {
  71        ULP_PM_HSRUN,    /* High speed run mode */
  72        ULP_PM_RUN,      /* Run mode */
  73        ULP_PM_WAIT,     /* Wait mode */
  74        ULP_PM_STOP,     /* Stop mode */
  75        ULP_PM_VLPS,     /* Very low power stop mode */
  76        ULP_PM_VLLS,     /* very low leakage stop mode */
  77};
  78
  79void imx_enable_cpu(int cpu, bool enable);
  80void imx_set_cpu_jump(int cpu, void *jump_addr);
  81u32 imx_get_cpu_arg(int cpu);
  82void imx_set_cpu_arg(int cpu, u32 arg);
  83#ifdef CONFIG_SMP
  84void v7_secondary_startup(void);
  85void imx_scu_map_io(void);
  86void imx_smp_prepare(void);
  87#else
  88static inline void imx_scu_map_io(void) {}
  89static inline void imx_smp_prepare(void) {}
  90#endif
  91void imx_src_init(void);
  92void imx_gpc_pre_suspend(bool arm_power_off);
  93void imx_gpc_post_resume(void);
  94void imx_gpc_mask_all(void);
  95void imx_gpc_restore_all(void);
  96void imx_gpc_hwirq_mask(unsigned int hwirq);
  97void imx_gpc_hwirq_unmask(unsigned int hwirq);
  98void imx_anatop_init(void);
  99void imx_anatop_pre_suspend(void);
 100void imx_anatop_post_resume(void);
 101int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
 102void imx6_set_int_mem_clk_lpm(bool enable);
 103void imx6sl_set_wait_clk(bool enter);
 104int imx_mmdc_get_ddr_type(void);
 105int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
 106
 107void imx_cpu_die(unsigned int cpu);
 108int imx_cpu_kill(unsigned int cpu);
 109
 110#ifdef CONFIG_SUSPEND
 111void imx53_suspend(void __iomem *ocram_vbase);
 112extern const u32 imx53_suspend_sz;
 113void imx6_suspend(void __iomem *ocram_vbase);
 114#else
 115static inline void imx53_suspend(void __iomem *ocram_vbase) {}
 116static const u32 imx53_suspend_sz;
 117static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 118#endif
 119
 120void v7_cpu_resume(void);
 121
 122void imx6_pm_ccm_init(const char *ccm_compat);
 123void imx6q_pm_init(void);
 124void imx6dl_pm_init(void);
 125void imx6sl_pm_init(void);
 126void imx6sx_pm_init(void);
 127void imx6ul_pm_init(void);
 128void imx7ulp_pm_init(void);
 129
 130#ifdef CONFIG_PM
 131void imx51_pm_init(void);
 132void imx53_pm_init(void);
 133#else
 134static inline void imx51_pm_init(void) {}
 135static inline void imx53_pm_init(void) {}
 136#endif
 137
 138#ifdef CONFIG_NEON
 139int mx51_neon_fixup(void);
 140#else
 141static inline int mx51_neon_fixup(void) { return 0; }
 142#endif
 143
 144#ifdef CONFIG_CACHE_L2X0
 145void imx_init_l2cache(void);
 146#else
 147static inline void imx_init_l2cache(void) {}
 148#endif
 149
 150extern const struct smp_operations imx_smp_ops;
 151extern const struct smp_operations ls1021a_smp_ops;
 152
 153#endif
 154