LXR linux/arch/arm/mach-imx/mach-imx7d.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4 */
   5#include <linux/irqchip.h>
   6#include <linux/mfd/syscon.h>
   7#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
   8#include <linux/of_platform.h>
   9#include <linux/phy.h>
  10#include <linux/regmap.h>
  11
  12#include <asm/mach/arch.h>
  13#include <asm/mach/map.h>
  14
  15#include "common.h"
  16
  17static int ar8031_phy_fixup(struct phy_device *dev)
  18{
  19        u16 val;
  20
  21        /* Set RGMII IO voltage to 1.8V */
  22        phy_write(dev, 0x1d, 0x1f);
  23        phy_write(dev, 0x1e, 0x8);
  24
  25        /* disable phy AR8031 SmartEEE function. */
  26        phy_write(dev, 0xd, 0x3);
  27        phy_write(dev, 0xe, 0x805d);
  28        phy_write(dev, 0xd, 0x4003);
  29        val = phy_read(dev, 0xe);
  30        val &= ~(0x1 << 8);
  31        phy_write(dev, 0xe, val);
  32
  33        return 0;
  34}
  35
  36static int bcm54220_phy_fixup(struct phy_device *dev)
  37{
  38        /* enable RXC skew select RGMII copper mode */
  39        phy_write(dev, 0x1e, 0x21);
  40        phy_write(dev, 0x1f, 0x7ea8);
  41        phy_write(dev, 0x1e, 0x2f);
  42        phy_write(dev, 0x1f, 0x71b7);
  43
  44        return 0;
  45}
  46
  47#define PHY_ID_AR8031   0x004dd074
  48#define PHY_ID_BCM54220 0x600d8589
  49
  50static void __init imx7d_enet_phy_init(void)
  51{
  52        if (IS_BUILTIN(CONFIG_PHYLIB)) {
  53                phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
  54                                           ar8031_phy_fixup);
  55                phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
  56                                           bcm54220_phy_fixup);
  57        }
  58}
  59
  60static void __init imx7d_enet_clk_sel(void)
  61{
  62        struct regmap *gpr;
  63
  64        gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
  65        if (!IS_ERR(gpr)) {
  66                regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
  67                regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
  68        } else {
  69                pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
  70        }
  71}
  72
  73static inline void imx7d_enet_init(void)
  74{
  75        imx7d_enet_phy_init();
  76        imx7d_enet_clk_sel();
  77}
  78
  79static void __init imx7d_init_machine(void)
  80{
  81        imx_anatop_init();
  82        imx7d_enet_init();
  83}
  84
  85static void __init imx7d_init_late(void)
  86{
  87        if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
  88                platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
  89}
  90
  91static void __init imx7d_init_irq(void)
  92{
  93        imx_init_revision_from_anatop();
  94        imx_src_init();
  95        irqchip_init();
  96}
  97
  98static const char *const imx7d_dt_compat[] __initconst = {
  99        "fsl,imx7d",
 100        "fsl,imx7s",
 101        NULL,
 102};
 103
 104DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
 105        .init_irq       = imx7d_init_irq,
 106        .init_machine   = imx7d_init_machine,
 107        .init_late      = imx7d_init_late,
 108        .dt_compat      = imx7d_dt_compat,
 109MACHINE_END
 110