LXR linux/arch/arm/mach-imx/mm-imx21.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * arch/arm/mach-imx/mm-imx21.c
   4 *
   5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   6 */
   7
   8#include <linux/mm.h>
   9#include <linux/init.h>
  10#include <linux/pinctrl/machine.h>
  11#include <asm/mach/map.h>
  12
  13#include "common.h"
  14#include "devices/devices-common.h"
  15#include "hardware.h"
  16#include "iomux-v1.h"
  17
  18/* MX21 memory map definition */
  19static struct map_desc imx21_io_desc[] __initdata = {
  20        /*
  21         * this fixed mapping covers:
  22         * - AIPI1
  23         * - AIPI2
  24         * - AITC
  25         * - ROM Patch
  26         * - and some reserved space
  27         */
  28        imx_map_entry(MX21, AIPI, MT_DEVICE),
  29        /*
  30         * this fixed mapping covers:
  31         * - CSI
  32         * - ATA
  33         */
  34        imx_map_entry(MX21, SAHB1, MT_DEVICE),
  35        /*
  36         * this fixed mapping covers:
  37         * - EMI
  38         */
  39        imx_map_entry(MX21, X_MEMC, MT_DEVICE),
  40};
  41
  42/*
  43 * Initialize the memory map. It is called during the
  44 * system startup to create static physical to virtual
  45 * memory map for the IO modules.
  46 */
  47void __init mx21_map_io(void)
  48{
  49        iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
  50}
  51
  52void __init imx21_init_early(void)
  53{
  54        mxc_set_cpu_type(MXC_CPU_MX21);
  55        imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
  56                        MX21_NUM_GPIO_PORT);
  57}
  58
  59void __init mx21_init_irq(void)
  60{
  61        mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
  62}
  63
  64static const struct resource imx21_audmux_res[] __initconst = {
  65        DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
  66};
  67
  68void __init imx21_soc_init(void)
  69{
  70        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
  71        mxc_device_init();
  72
  73        mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
  74        mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
  75        mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
  76        mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
  77        mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
  78        mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
  79
  80        pinctrl_provide_dummies();
  81        imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, MX21_INT_DMACH0);
  82        platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
  83                                        ARRAY_SIZE(imx21_audmux_res));
  84}
  85