LXR linux/arch/microblaze/include/asm/pci-bridge.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2#ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
   3#define _ASM_MICROBLAZE_PCI_BRIDGE_H
   4#ifdef __KERNEL__
   5/*
   6 */
   7#include <linux/pci.h>
   8#include <linux/list.h>
   9#include <linux/ioport.h>
  10
  11struct device_node;
  12
  13#ifdef CONFIG_PCI
  14extern struct list_head hose_list;
  15extern int pcibios_vaddr_is_ioport(void __iomem *address);
  16#else
  17static inline int pcibios_vaddr_is_ioport(void __iomem *address)
  18{
  19        return 0;
  20}
  21#endif
  22
  23/*
  24 * Structure of a PCI controller (host bridge)
  25 */
  26struct pci_controller {
  27        struct pci_bus *bus;
  28        char is_dynamic;
  29        struct device_node *dn;
  30        struct list_head list_node;
  31        struct device *parent;
  32
  33        int first_busno;
  34        int last_busno;
  35
  36        int self_busno;
  37
  38        void __iomem *io_base_virt;
  39        resource_size_t io_base_phys;
  40
  41        resource_size_t pci_io_size;
  42
  43        /* Some machines (PReP) have a non 1:1 mapping of
  44         * the PCI memory space in the CPU bus space
  45         */
  46        resource_size_t pci_mem_offset;
  47
  48        /* Some machines have a special region to forward the ISA
  49         * "memory" cycles such as VGA memory regions. Left to 0
  50         * if unsupported
  51         */
  52        resource_size_t isa_mem_phys;
  53        resource_size_t isa_mem_size;
  54
  55        struct pci_ops *ops;
  56        unsigned int __iomem *cfg_addr;
  57        void __iomem *cfg_data;
  58
  59        /*
  60         * Used for variants of PCI indirect handling and possible quirks:
  61         *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  62         *  EXT_REG - provides access to PCI-e extended registers
  63         *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  64         *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  65         *   to determine which bus number to match on when generating type0
  66         *   config cycles
  67         *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  68         *   hanging if we don't have link and try to do config cycles to
  69         *   anything but the PHB.  Only allow talking to the PHB if this is
  70         *   set.
  71         *  BIG_ENDIAN - cfg_addr is a big endian register
  72         *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
  73         *   on the PLB4.  Effectively disable MRM commands by setting this.
  74         */
  75#define INDIRECT_TYPE_SET_CFG_TYPE              0x00000001
  76#define INDIRECT_TYPE_EXT_REG           0x00000002
  77#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS      0x00000004
  78#define INDIRECT_TYPE_NO_PCIE_LINK              0x00000008
  79#define INDIRECT_TYPE_BIG_ENDIAN                0x00000010
  80#define INDIRECT_TYPE_BROKEN_MRM                0x00000020
  81        u32 indirect_type;
  82
  83        /* Currently, we limit ourselves to 1 IO range and 3 mem
  84         * ranges since the common pci_bus structure can't handle more
  85         */
  86        struct resource io_resource;
  87        struct resource mem_resources[3];
  88        int global_number;      /* PCI domain number */
  89};
  90
  91#ifdef CONFIG_PCI
  92static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
  93{
  94        return bus->sysdata;
  95}
  96
  97static inline int isa_vaddr_is_ioport(void __iomem *address)
  98{
  99        /* No specific ISA handling on ppc32 at this stage, it
 100         * all goes through PCI
 101         */
 102        return 0;
 103}
 104#endif /* CONFIG_PCI */
 105
 106/* These are used for config access before all the PCI probing
 107   has been done. */
 108extern int early_read_config_byte(struct pci_controller *hose, int bus,
 109                        int dev_fn, int where, u8 *val);
 110extern int early_read_config_word(struct pci_controller *hose, int bus,
 111                        int dev_fn, int where, u16 *val);
 112extern int early_read_config_dword(struct pci_controller *hose, int bus,
 113                        int dev_fn, int where, u32 *val);
 114extern int early_write_config_byte(struct pci_controller *hose, int bus,
 115                        int dev_fn, int where, u8 val);
 116extern int early_write_config_word(struct pci_controller *hose, int bus,
 117                        int dev_fn, int where, u16 val);
 118extern int early_write_config_dword(struct pci_controller *hose, int bus,
 119                        int dev_fn, int where, u32 val);
 120
 121extern int early_find_capability(struct pci_controller *hose, int bus,
 122                                 int dev_fn, int cap);
 123
 124extern void setup_indirect_pci(struct pci_controller *hose,
 125                               resource_size_t cfg_addr,
 126                               resource_size_t cfg_data, u32 flags);
 127
 128/* Get the PCI host controller for an OF device */
 129extern struct pci_controller *pci_find_hose_for_OF_device(
 130                        struct device_node *node);
 131
 132/* Fill up host controller resources from the OF node */
 133extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 134                        struct device_node *dev, int primary);
 135
 136/* Allocate & free a PCI host bridge structure */
 137extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 138extern void pcibios_free_controller(struct pci_controller *phb);
 139
 140#endif  /* __KERNEL__ */
 141#endif  /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
 142