LXR linux/arch/nds32/include/asm/nds32.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2// Copyright (C) 2005-2017 Andes Technology Corporation
   3
   4#ifndef _ASM_NDS32_NDS32_H_
   5#define _ASM_NDS32_NDS32_H_
   6
   7#include <asm/bitfield.h>
   8#include <asm/cachectl.h>
   9
  10#ifndef __ASSEMBLY__
  11#include <linux/init.h>
  12#include <asm/barrier.h>
  13#include <nds32_intrinsic.h>
  14
  15#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
  16#define FP_OFFSET (-3)
  17#else
  18#define FP_OFFSET (-2)
  19#endif
  20#define LP_OFFSET (-1)
  21
  22extern void __init early_trap_init(void);
  23static inline void GIE_ENABLE(void)
  24{
  25        mb();
  26        __nds32__gie_en();
  27}
  28
  29static inline void GIE_DISABLE(void)
  30{
  31        mb();
  32        __nds32__gie_dis();
  33}
  34
  35static inline unsigned long CACHE_SET(unsigned char cache)
  36{
  37
  38        if (cache == ICACHE)
  39                return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
  40                              ICM_CFG_offISET);
  41        else
  42                return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
  43                              DCM_CFG_offDSET);
  44}
  45
  46static inline unsigned long CACHE_WAY(unsigned char cache)
  47{
  48
  49        if (cache == ICACHE)
  50                return 1 +
  51                    ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
  52        else
  53                return 1 +
  54                    ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
  55}
  56
  57static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
  58{
  59
  60        if (cache == ICACHE)
  61                return 8 <<
  62                    (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
  63        else
  64                return 8 <<
  65                    (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
  66}
  67
  68#endif /* __ASSEMBLY__ */
  69
  70#define IVB_BASE                PHYS_OFFSET     /* in user space for intr/exc/trap/break table base, 64KB aligned
  71                                                 * We defined at the start of the physical memory */
  72
  73/* dispatched sub-entry exception handler numbering */
  74#define RD_PROT                 0       /* read protrection */
  75#define WRT_PROT                1       /* write protection */
  76#define NOEXEC                  2       /* non executable */
  77#define PAGE_MODIFY             3       /* page modified */
  78#define ACC_BIT                 4       /* access bit */
  79#define RESVED_PTE              5       /* reserved PTE attribute */
  80/* reserved 6 ~ 16 */
  81
  82#endif /* _ASM_NDS32_NDS32_H_ */
  83