1
2#ifndef _UAPI_PARISC_PDC_H
3#define _UAPI_PARISC_PDC_H
4
5
6
7
8
9
10#define PDC_WARN 3
11#define PDC_REQ_ERR_1 2
12#define PDC_REQ_ERR_0 1
13#define PDC_OK 0
14#define PDC_BAD_PROC -1
15#define PDC_BAD_OPTION -2
16#define PDC_ERROR -3
17#define PDC_NE_MOD -5
18#define PDC_NE_CELL_MOD -7
19#define PDC_NE_BOOTDEV -9
20#define PDC_INVALID_ARG -10
21#define PDC_BUS_POW_WARN -12
22#define PDC_NOT_NARROW -17
23
24
25
26
27
28#define PDC_POW_FAIL 1
29#define PDC_POW_FAIL_PREPARE 0
30
31#define PDC_CHASSIS 2
32#define PDC_CHASSIS_DISP 0
33#define PDC_CHASSIS_WARN 1
34#define PDC_CHASSIS_DISPWARN 2
35#define PDC_RETURN_CHASSIS_INFO 128
36
37#define PDC_PIM 3
38#define PDC_PIM_HPMC 0
39#define PDC_PIM_RETURN_SIZE 1
40#define PDC_PIM_LPMC 2
41#define PDC_PIM_SOFT_BOOT 3
42#define PDC_PIM_TOC 4
43
44#define PDC_MODEL 4
45#define PDC_MODEL_INFO 0
46#define PDC_MODEL_BOOTID 1
47#define PDC_MODEL_VERSIONS 2
48#define PDC_MODEL_SYSMODEL 3
49#define PDC_MODEL_ENSPEC 4
50#define PDC_MODEL_DISPEC 5
51#define PDC_MODEL_CPU_ID 6
52#define PDC_MODEL_CAPABILITIES 7
53
54#define PDC_MODEL_OS64 (1 << 0)
55#define PDC_MODEL_OS32 (1 << 1)
56#define PDC_MODEL_IOPDIR_FDC (1 << 2)
57#define PDC_MODEL_NVA_MASK (3 << 4)
58#define PDC_MODEL_NVA_SUPPORTED (0 << 4)
59#define PDC_MODEL_NVA_SLOW (1 << 4)
60#define PDC_MODEL_NVA_UNSUPPORTED (3 << 4)
61#define PDC_MODEL_GET_BOOT__OP 8
62#define PDC_MODEL_SET_BOOT__OP 9
63#define PDC_MODEL_GET_PLATFORM_INFO 10
64#define PDC_MODEL_GET_INSTALL_KERNEL 11
65
66#define PA89_INSTRUCTION_SET 0x4
67#define PA90_INSTRUCTION_SET 0x8
68
69#define PDC_CACHE 5
70#define PDC_CACHE_INFO 0
71#define PDC_CACHE_SET_COH 1
72#define PDC_CACHE_RET_SPID 2
73
74#define PDC_HPA 6
75#define PDC_HPA_PROCESSOR 0
76#define PDC_HPA_MODULES 1
77
78#define PDC_COPROC 7
79#define PDC_COPROC_CFG 0
80
81#define PDC_IODC 8
82#define PDC_IODC_READ 0
83
84#define PDC_IODC_RI_DATA_BYTES 0
85
86#define PDC_IODC_RI_INIT 3
87#define PDC_IODC_RI_IO 4
88#define PDC_IODC_RI_SPA 5
89#define PDC_IODC_RI_CONFIG 6
90
91#define PDC_IODC_RI_TEST 8
92#define PDC_IODC_RI_TLB 9
93#define PDC_IODC_NINIT 2
94#define PDC_IODC_DINIT 3
95#define PDC_IODC_MEMERR 4
96#define PDC_IODC_INDEX_DATA 0
97#define PDC_IODC_BUS_ERROR -4
98#define PDC_IODC_INVALID_INDEX -5
99#define PDC_IODC_COUNT -6
100
101#define PDC_TOD 9
102#define PDC_TOD_READ 0
103#define PDC_TOD_WRITE 1
104#define PDC_TOD_CALIBRATE 2
105
106#define PDC_STABLE 10
107#define PDC_STABLE_READ 0
108#define PDC_STABLE_WRITE 1
109#define PDC_STABLE_RETURN_SIZE 2
110#define PDC_STABLE_VERIFY_CONTENTS 3
111#define PDC_STABLE_INITIALIZE 4
112
113#define PDC_NVOLATILE 11
114#define PDC_NVOLATILE_READ 0
115#define PDC_NVOLATILE_WRITE 1
116#define PDC_NVOLATILE_RETURN_SIZE 2
117#define PDC_NVOLATILE_VERIFY_CONTENTS 3
118#define PDC_NVOLATILE_INITIALIZE 4
119
120#define PDC_ADD_VALID 12
121#define PDC_ADD_VALID_VERIFY 0
122
123#define PDC_DEBUG 14
124
125#define PDC_INSTR 15
126
127#define PDC_PROC 16
128
129#define PDC_CONFIG 17
130#define PDC_CONFIG_DECONFIG 0
131#define PDC_CONFIG_DRECONFIG 1
132#define PDC_CONFIG_DRETURN_CONFIG 2
133
134#define PDC_BLOCK_TLB 18
135#define PDC_BTLB_INFO 0
136#define PDC_BTLB_INSERT 1
137#define PDC_BTLB_PURGE 2
138#define PDC_BTLB_PURGE_ALL 3
139
140#define PDC_TLB 19
141#define PDC_TLB_INFO 0
142#define PDC_TLB_SETUP 1
143
144#define PDC_MEM 20
145#define PDC_MEM_MEMINFO 0
146#define PDC_MEM_ADD_PAGE 1
147#define PDC_MEM_CLEAR_PDT 2
148#define PDC_MEM_READ_PDT 3
149#define PDC_MEM_RESET_CLEAR 4
150#define PDC_MEM_GOODMEM 5
151#define PDC_MEM_TABLE 128
152#define PDC_MEM_RETURN_ADDRESS_TABLE PDC_MEM_TABLE
153#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE 131
154#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES 132
155#define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133
156
157#define PDC_MEM_RET_SBE_REPLACED 5
158#define PDC_MEM_RET_DUPLICATE_ENTRY 4
159#define PDC_MEM_RET_BUF_SIZE_SMALL 1
160#define PDC_MEM_RET_PDT_FULL -11
161#define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL
162
163#define PDC_PSW 21
164#define PDC_PSW_MASK 0
165#define PDC_PSW_GET_DEFAULTS 1
166#define PDC_PSW_SET_DEFAULTS 2
167#define PDC_PSW_ENDIAN_BIT 1
168#define PDC_PSW_WIDE_BIT 2
169
170#define PDC_SYSTEM_MAP 22
171#define PDC_FIND_MODULE 0
172#define PDC_FIND_ADDRESS 1
173#define PDC_TRANSLATE_PATH 2
174
175#define PDC_SOFT_POWER 23
176#define PDC_SOFT_POWER_INFO 0
177#define PDC_SOFT_POWER_ENABLE 1
178
179#define PDC_ALLOC 24
180
181#define PDC_CRASH_PREP 25
182#define PDC_CRASH_DUMP 0
183#define PDC_CRASH_LOG_CEC_ERROR 1
184
185#define PDC_SCSI_PARMS 26
186#define PDC_SCSI_GET_PARMS 0
187#define PDC_SCSI_SET_PARMS 1
188
189
190
191
192#define PDC_MEM_MAP 128
193#define PDC_MEM_MAP_HPA 0
194
195#define PDC_EEPROM 129
196#define PDC_EEPROM_READ_WORD 0
197#define PDC_EEPROM_WRITE_WORD 1
198#define PDC_EEPROM_READ_BYTE 2
199#define PDC_EEPROM_WRITE_BYTE 3
200#define PDC_EEPROM_EEPROM_PASSWORD -1000
201
202#define PDC_NVM 130
203#define PDC_NVM_READ_WORD 0
204#define PDC_NVM_WRITE_WORD 1
205#define PDC_NVM_READ_BYTE 2
206#define PDC_NVM_WRITE_BYTE 3
207
208#define PDC_SEED_ERROR 132
209
210#define PDC_IO 135
211#define PDC_IO_READ_AND_CLEAR_ERRORS 0
212#define PDC_IO_RESET 1
213#define PDC_IO_RESET_DEVICES 2
214
215#define PDC_IO_USB_SUSPEND 0xC000000000000000
216#define PDC_IO_EEPROM_IO_ERR_TABLE_FULL -5
217#define PDC_IO_NO_SUSPEND -6
218
219#define PDC_BROADCAST_RESET 136
220#define PDC_DO_RESET 0
221#define PDC_DO_FIRM_TEST_RESET 1
222#define PDC_BR_RECONFIGURATION 2
223#define PDC_FIRM_TEST_MAGIC 0xab9ec36fUL
224
225#define PDC_LAN_STATION_ID 138
226#define PDC_LAN_STATION_ID_READ 0
227
228#define PDC_LAN_STATION_ID_SIZE 6
229
230#define PDC_CHECK_RANGES 139
231
232#define PDC_NV_SECTIONS 141
233
234#define PDC_PERFORMANCE 142
235
236#define PDC_SYSTEM_INFO 143
237#define PDC_SYSINFO_RETURN_INFO_SIZE 0
238#define PDC_SYSINFO_RRETURN_SYS_INFO 1
239#define PDC_SYSINFO_RRETURN_ERRORS 2
240#define PDC_SYSINFO_RRETURN_WARNINGS 3
241#define PDC_SYSINFO_RETURN_REVISIONS 4
242#define PDC_SYSINFO_RRETURN_DIAGNOSE 5
243#define PDC_SYSINFO_RRETURN_HV_DIAGNOSE 1005
244
245#define PDC_RDR 144
246#define PDC_RDR_READ_BUFFER 0
247#define PDC_RDR_READ_SINGLE 1
248#define PDC_RDR_WRITE_SINGLE 2
249
250#define PDC_INTRIGUE 145
251#define PDC_INTRIGUE_WRITE_BUFFER 0
252#define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1
253#define PDC_INTRIGUE_START_CPU_COUNTERS 2
254#define PDC_INTRIGUE_STOP_CPU_COUNTERS 3
255
256#define PDC_STI 146
257
258
259
260#define PDC_PCI_INDEX 147
261#define PDC_PCI_INTERFACE_INFO 0
262#define PDC_PCI_SLOT_INFO 1
263#define PDC_PCI_INFLIGHT_BYTES 2
264#define PDC_PCI_READ_CONFIG 3
265#define PDC_PCI_WRITE_CONFIG 4
266#define PDC_PCI_READ_PCI_IO 5
267#define PDC_PCI_WRITE_PCI_IO 6
268#define PDC_PCI_READ_CONFIG_DELAY 7
269#define PDC_PCI_UPDATE_CONFIG_DELAY 8
270#define PDC_PCI_PCI_PATH_TO_PCI_HPA 9
271#define PDC_PCI_PCI_HPA_TO_PCI_PATH 10
272#define PDC_PCI_PCI_PATH_TO_PCI_BUS 11
273#define PDC_PCI_PCI_RESERVED 12
274#define PDC_PCI_PCI_INT_ROUTE_SIZE 13
275#define PDC_PCI_GET_INT_TBL_SIZE PDC_PCI_PCI_INT_ROUTE_SIZE
276#define PDC_PCI_PCI_INT_ROUTE 14
277#define PDC_PCI_GET_INT_TBL PDC_PCI_PCI_INT_ROUTE
278#define PDC_PCI_READ_MON_TYPE 15
279#define PDC_PCI_WRITE_MON_TYPE 16
280
281#define PDC_RELOCATE 149
282#define PDC_RELOCATE_GET_RELOCINFO 0
283#define PDC_RELOCATE_CHECKSUM 1
284#define PDC_RELOCATE_RELOCATE 2
285
286
287#define PDC_INITIATOR 163
288#define PDC_GET_INITIATOR 0
289#define PDC_SET_INITIATOR 1
290#define PDC_DELETE_INITIATOR 2
291#define PDC_RETURN_TABLE_SIZE 3
292#define PDC_RETURN_TABLE 4
293
294#define PDC_LINK 165
295#define PDC_LINK_PCI_ENTRY_POINTS 0
296#define PDC_LINK_USB_ENTRY_POINTS 1
297
298
299
300
301
302#define CL_NULL 0
303#define CL_RANDOM 1
304#define CL_SEQU 2
305#define CL_DUPLEX 7
306#define CL_KEYBD 8
307#define CL_DISPL 9
308#define CL_FC 10
309
310
311#define ENTRY_INIT_SRCH_FRST 2
312#define ENTRY_INIT_SRCH_NEXT 3
313#define ENTRY_INIT_MOD_DEV 4
314#define ENTRY_INIT_DEV 5
315#define ENTRY_INIT_MOD 6
316#define ENTRY_INIT_MSG 9
317
318
319#define ENTRY_IO_BOOTIN 0
320#define ENTRY_IO_BOOTOUT 1
321#define ENTRY_IO_CIN 2
322#define ENTRY_IO_COUT 3
323#define ENTRY_IO_CLOSE 4
324#define ENTRY_IO_GETMSG 9
325#define ENTRY_IO_BBLOCK_IN 16
326#define ENTRY_IO_BBLOCK_OUT 17
327
328
329
330
331
332
333
334
335
336
337#define OS_ID_NONE 0
338#define OS_ID_HPUX 1
339#define OS_ID_MPEXL 2
340#define OS_ID_OSF 3
341#define OS_ID_HPRT 4
342#define OS_ID_NOVEL 5
343#define OS_ID_LINUX 6
344
345
346
347#define OSTAT_OFF 0
348#define OSTAT_FLT 1
349#define OSTAT_TEST 2
350#define OSTAT_INIT 3
351#define OSTAT_SHUT 4
352#define OSTAT_WARN 5
353#define OSTAT_RUN 6
354#define OSTAT_ON 7
355
356
357#define BOOT_CONSOLE_HPA_OFFSET 0x3c0
358#define BOOT_CONSOLE_SPA_OFFSET 0x3c4
359#define BOOT_CONSOLE_PATH_OFFSET 0x3a8
360
361
362#define NUM_PDC_RESULT 32
363
364#if !defined(__ASSEMBLY__)
365
366
367#define PF_AUTOBOOT 0x80
368#define PF_AUTOSEARCH 0x40
369#define PF_TIMER 0x0F
370
371struct device_path {
372 unsigned char flags;
373 unsigned char bc[6];
374 unsigned char mod;
375 unsigned int layers[6];
376} __attribute__((aligned(8))) ;
377
378struct pz_device {
379 struct device_path dp;
380
381 unsigned int hpa;
382
383 unsigned int spa;
384
385 unsigned int iodc_io;
386 short pad;
387 unsigned short cl_class;
388} __attribute__((aligned(8))) ;
389
390struct zeropage {
391
392 unsigned int vec_special;
393
394 unsigned int vec_pow_fail;
395
396 unsigned int vec_toc;
397 unsigned int vec_toclen;
398
399 unsigned int vec_rendz;
400 int vec_pow_fail_flen;
401 int vec_pad[10];
402
403
404 int pad0[112];
405
406
407 int pad1[84];
408
409
410 int memc_cont;
411 int memc_phsize;
412 int memc_adsize;
413 unsigned int mem_pdc_hi;
414
415
416
417 unsigned int mem_booterr[8];
418 unsigned int mem_free;
419
420 unsigned int mem_hpa;
421
422 unsigned int mem_pdc;
423 unsigned int mem_10msec;
424
425
426
427 unsigned int imm_hpa;
428 int imm_soft_boot;
429 unsigned int imm_spa_size;
430 unsigned int imm_max_mem;
431
432
433 struct pz_device mem_cons;
434 struct pz_device mem_boot;
435 struct pz_device mem_kbd;
436
437
438 int pad430[116];
439
440
441 unsigned int pad600[1];
442 unsigned int proc_sti;
443 unsigned int pad608[126];
444};
445
446struct pdc_chassis_info {
447 unsigned long actcnt;
448 unsigned long maxcnt;
449};
450
451struct pdc_coproc_cfg {
452 unsigned long ccr_functional;
453 unsigned long ccr_present;
454 unsigned long revision;
455 unsigned long model;
456};
457
458struct pdc_model {
459 unsigned long hversion;
460 unsigned long sversion;
461 unsigned long hw_id;
462 unsigned long boot_id;
463 unsigned long sw_id;
464 unsigned long sw_cap;
465 unsigned long arch_rev;
466 unsigned long pot_key;
467 unsigned long curr_key;
468};
469
470struct pdc_cache_cf {
471 unsigned long
472#ifdef __LP64__
473 cc_padW:32,
474#endif
475 cc_alias: 4,
476 cc_block: 4,
477 cc_line : 3,
478 cc_shift: 2,
479 cc_wt : 1,
480 cc_sh : 2,
481 cc_cst : 3,
482 cc_pad1 : 10,
483 cc_hv : 3;
484};
485
486struct pdc_tlb_cf {
487 unsigned long tc_pad0:12,
488#ifdef __LP64__
489 tc_padW:32,
490#endif
491 tc_sh : 2,
492 tc_hv : 1,
493 tc_page : 1,
494 tc_cst : 3,
495 tc_aid : 5,
496 tc_sr : 8;
497};
498
499struct pdc_cache_info {
500
501 unsigned long ic_size;
502 struct pdc_cache_cf ic_conf;
503 unsigned long ic_base;
504 unsigned long ic_stride;
505 unsigned long ic_count;
506 unsigned long ic_loop;
507
508 unsigned long dc_size;
509 struct pdc_cache_cf dc_conf;
510 unsigned long dc_base;
511 unsigned long dc_stride;
512 unsigned long dc_count;
513 unsigned long dc_loop;
514
515 unsigned long it_size;
516 struct pdc_tlb_cf it_conf;
517 unsigned long it_sp_base;
518 unsigned long it_sp_stride;
519 unsigned long it_sp_count;
520 unsigned long it_off_base;
521 unsigned long it_off_stride;
522 unsigned long it_off_count;
523 unsigned long it_loop;
524
525 unsigned long dt_size;
526 struct pdc_tlb_cf dt_conf;
527 unsigned long dt_sp_base;
528 unsigned long dt_sp_stride;
529 unsigned long dt_sp_count;
530 unsigned long dt_off_base;
531 unsigned long dt_off_stride;
532 unsigned long dt_off_count;
533 unsigned long dt_loop;
534};
535
536
537struct pdc_iodc {
538 unsigned char hversion_model;
539 unsigned char hversion;
540 unsigned char spa;
541 unsigned char type;
542 unsigned int sversion_rev:4;
543 unsigned int sversion_model:19;
544 unsigned int sversion_opt:8;
545 unsigned char rev;
546 unsigned char dep;
547 unsigned char features;
548 unsigned char pad1;
549 unsigned int checksum:16;
550 unsigned int length:16;
551 unsigned int pad[15];
552} __attribute__((aligned(8))) ;
553
554
555struct pdc_btlb_info_range {
556 unsigned char res00;
557 unsigned char num_i;
558 unsigned char num_d;
559 unsigned char num_comb;
560};
561
562struct pdc_btlb_info {
563 unsigned int min_size;
564 unsigned int max_size;
565 struct pdc_btlb_info_range fixed_range_info;
566 struct pdc_btlb_info_range variable_range_info;
567};
568
569struct pdc_mem_retinfo {
570 unsigned long pdt_size;
571 unsigned long pdt_entries;
572 unsigned long pdt_status;
573 unsigned long first_dbe_loc;
574 unsigned long good_mem;
575};
576
577struct pdc_mem_read_pdt {
578 unsigned long pdt_entries;
579};
580
581#ifdef __LP64__
582struct pdc_memory_table_raddr {
583 unsigned long entries_returned;
584 unsigned long entries_total;
585};
586
587struct pdc_memory_table {
588 unsigned long paddr;
589 unsigned int pages;
590 unsigned int reserved;
591};
592#endif
593
594struct pdc_system_map_mod_info {
595 unsigned long mod_addr;
596 unsigned long mod_pgs;
597 unsigned long add_addrs;
598};
599
600struct pdc_system_map_addr_info {
601 unsigned long mod_addr;
602 unsigned long mod_pgs;
603};
604
605struct pdc_initiator {
606 int host_id;
607 int factor;
608 int width;
609 int mode;
610};
611
612struct hardware_path {
613 char flags;
614 char bc[6];
615
616 char mod;
617};
618
619
620
621
622struct pdc_module_path {
623 struct hardware_path path;
624 unsigned int layers[6];
625};
626
627
628struct pdc_memory_map {
629 unsigned long hpa;
630 unsigned long more_pgs;
631};
632
633struct pdc_tod {
634 unsigned long tod_sec;
635 unsigned long tod_usec;
636};
637
638
639
640struct pdc_hpmc_pim_11 {
641 unsigned int gr[32];
642 unsigned int cr[32];
643 unsigned int sr[8];
644 unsigned int iasq_back;
645 unsigned int iaoq_back;
646 unsigned int check_type;
647 unsigned int cpu_state;
648 unsigned int rsvd1;
649 unsigned int cache_check;
650 unsigned int tlb_check;
651 unsigned int bus_check;
652 unsigned int assists_check;
653 unsigned int rsvd2;
654 unsigned int assist_state;
655 unsigned int responder_addr;
656 unsigned int requestor_addr;
657 unsigned int path_info;
658 unsigned long long fr[32];
659};
660
661
662
663
664
665
666
667
668
669
670
671
672
673struct pdc_hpmc_pim_20 {
674 unsigned long long gr[32];
675 unsigned long long cr[32];
676 unsigned long long sr[8];
677 unsigned long long iasq_back;
678 unsigned long long iaoq_back;
679 unsigned int check_type;
680 unsigned int cpu_state;
681 unsigned int cache_check;
682 unsigned int tlb_check;
683 unsigned int bus_check;
684 unsigned int assists_check;
685 unsigned int assist_state;
686 unsigned int path_info;
687 unsigned long long responder_addr;
688 unsigned long long requestor_addr;
689 unsigned long long fr[32];
690};
691
692#endif
693
694#endif
695