1
2#ifndef _ASM_POWERPC_IO_H
3#define _ASM_POWERPC_IO_H
4#ifdef __KERNEL__
5
6#define ARCH_HAS_IOREMAP_WC
7#ifdef CONFIG_PPC32
8#define ARCH_HAS_IOREMAP_WT
9#endif
10
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14
15extern int check_legacy_ioport(unsigned long base_port);
16#define I8042_DATA_REG 0x60
17#define FDC_BASE 0x3f0
18
19#if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20extern struct pci_dev *isa_bridge_pcidev;
21
22
23
24#define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
25#endif
26
27#include <linux/device.h>
28#include <linux/compiler.h>
29#include <linux/mm.h>
30#include <asm/page.h>
31#include <asm/byteorder.h>
32#include <asm/synch.h>
33#include <asm/delay.h>
34#include <asm/mmiowb.h>
35#include <asm/mmu.h>
36#include <asm/ppc_asm.h>
37
38#define SIO_CONFIG_RA 0x398
39#define SIO_CONFIG_RD 0x399
40
41#define SLOW_DOWN_IO
42
43
44
45
46
47#ifndef CONFIG_PCI
48#define _IO_BASE 0
49#define _ISA_MEM_BASE 0
50#define PCI_DRAM_OFFSET 0
51#elif defined(CONFIG_PPC32)
52#define _IO_BASE isa_io_base
53#define _ISA_MEM_BASE isa_mem_base
54#define PCI_DRAM_OFFSET pci_dram_offset
55#else
56#define _IO_BASE pci_io_base
57#define _ISA_MEM_BASE isa_mem_base
58#define PCI_DRAM_OFFSET 0
59#endif
60
61extern unsigned long isa_io_base;
62extern unsigned long pci_io_base;
63extern unsigned long pci_dram_offset;
64
65extern resource_size_t isa_mem_base;
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72
73extern bool isa_io_special;
74
75#ifdef CONFIG_PPC32
76#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
77#error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
78#endif
79#endif
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103#define DEF_MMIO_IN_X(name, size, insn) \
104static inline u##size name(const volatile u##size __iomem *addr) \
105{ \
106 u##size ret; \
107 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
108 : "=r" (ret) : "Z" (*addr) : "memory"); \
109 return ret; \
110}
111
112#define DEF_MMIO_OUT_X(name, size, insn) \
113static inline void name(volatile u##size __iomem *addr, u##size val) \
114{ \
115 __asm__ __volatile__("sync;"#insn" %1,%y0" \
116 : "=Z" (*addr) : "r" (val) : "memory"); \
117 mmiowb_set_pending(); \
118}
119
120#define DEF_MMIO_IN_D(name, size, insn) \
121static inline u##size name(const volatile u##size __iomem *addr) \
122{ \
123 u##size ret; \
124 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
125 : "=r" (ret) : "m" (*addr) : "memory"); \
126 return ret; \
127}
128
129#define DEF_MMIO_OUT_D(name, size, insn) \
130static inline void name(volatile u##size __iomem *addr, u##size val) \
131{ \
132 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
133 : "=m" (*addr) : "r" (val) : "memory"); \
134 mmiowb_set_pending(); \
135}
136
137DEF_MMIO_IN_D(in_8, 8, lbz);
138DEF_MMIO_OUT_D(out_8, 8, stb);
139
140#ifdef __BIG_ENDIAN__
141DEF_MMIO_IN_D(in_be16, 16, lhz);
142DEF_MMIO_IN_D(in_be32, 32, lwz);
143DEF_MMIO_IN_X(in_le16, 16, lhbrx);
144DEF_MMIO_IN_X(in_le32, 32, lwbrx);
145
146DEF_MMIO_OUT_D(out_be16, 16, sth);
147DEF_MMIO_OUT_D(out_be32, 32, stw);
148DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
149DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
150#else
151DEF_MMIO_IN_X(in_be16, 16, lhbrx);
152DEF_MMIO_IN_X(in_be32, 32, lwbrx);
153DEF_MMIO_IN_D(in_le16, 16, lhz);
154DEF_MMIO_IN_D(in_le32, 32, lwz);
155
156DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
157DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
158DEF_MMIO_OUT_D(out_le16, 16, sth);
159DEF_MMIO_OUT_D(out_le32, 32, stw);
160
161#endif
162
163#ifdef __powerpc64__
164
165#ifdef __BIG_ENDIAN__
166DEF_MMIO_OUT_D(out_be64, 64, std);
167DEF_MMIO_IN_D(in_be64, 64, ld);
168
169
170static inline u64 in_le64(const volatile u64 __iomem *addr)
171{
172 return swab64(in_be64(addr));
173}
174
175static inline void out_le64(volatile u64 __iomem *addr, u64 val)
176{
177 out_be64(addr, swab64(val));
178}
179#else
180DEF_MMIO_OUT_D(out_le64, 64, std);
181DEF_MMIO_IN_D(in_le64, 64, ld);
182
183
184static inline u64 in_be64(const volatile u64 __iomem *addr)
185{
186 return swab64(in_le64(addr));
187}
188
189static inline void out_be64(volatile u64 __iomem *addr, u64 val)
190{
191 out_le64(addr, swab64(val));
192}
193
194#endif
195#endif
196
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199
200extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
201extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
202extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
203extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
204extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
205extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
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210#define _insw _insw_ns
211#define _insl _insl_ns
212#define _outsw _outsw_ns
213#define _outsl _outsl_ns
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220extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
221extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
222 unsigned long n);
223extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
224 unsigned long n);
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244#ifdef CONFIG_EEH
245#include <asm/eeh.h>
246#endif
247
248
249#define PCI_IO_ADDR volatile void __iomem *
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277#ifdef CONFIG_PPC_INDIRECT_MMIO
278#define PCI_IO_IND_TOKEN_SHIFT 52
279#define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
280#define PCI_FIX_ADDR(addr) \
281 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
282#define PCI_GET_ADDR_TOKEN(addr) \
283 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
284 PCI_IO_IND_TOKEN_SHIFT)
285#define PCI_SET_ADDR_TOKEN(addr, token) \
286do { \
287 unsigned long __a = (unsigned long)(addr); \
288 __a &= ~PCI_IO_IND_TOKEN_MASK; \
289 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
290 (addr) = (void __iomem *)__a; \
291} while(0)
292#else
293#define PCI_FIX_ADDR(addr) (addr)
294#endif
295
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299
300
301static inline unsigned char __raw_readb(const volatile void __iomem *addr)
302{
303 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
304}
305static inline unsigned short __raw_readw(const volatile void __iomem *addr)
306{
307 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
308}
309static inline unsigned int __raw_readl(const volatile void __iomem *addr)
310{
311 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
312}
313static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
314{
315 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
316}
317static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
318{
319 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
320}
321static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
322{
323 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
324}
325
326#ifdef __powerpc64__
327static inline unsigned long __raw_readq(const volatile void __iomem *addr)
328{
329 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
330}
331static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
332{
333 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
334}
335
336static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
337{
338 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
339}
340
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344
345static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
346{
347 __asm__ __volatile__("stbcix %0,0,%1"
348 : : "r" (val), "r" (paddr) : "memory");
349}
350
351static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
352{
353 __asm__ __volatile__("sthcix %0,0,%1"
354 : : "r" (val), "r" (paddr) : "memory");
355}
356
357static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
358{
359 __asm__ __volatile__("stwcix %0,0,%1"
360 : : "r" (val), "r" (paddr) : "memory");
361}
362
363static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
364{
365 __asm__ __volatile__("stdcix %0,0,%1"
366 : : "r" (val), "r" (paddr) : "memory");
367}
368
369static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
370{
371 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
372}
373
374static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
375{
376 u8 ret;
377 __asm__ __volatile__("lbzcix %0,0, %1"
378 : "=r" (ret) : "r" (paddr) : "memory");
379 return ret;
380}
381
382static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
383{
384 u16 ret;
385 __asm__ __volatile__("lhzcix %0,0, %1"
386 : "=r" (ret) : "r" (paddr) : "memory");
387 return ret;
388}
389
390static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
391{
392 u32 ret;
393 __asm__ __volatile__("lwzcix %0,0, %1"
394 : "=r" (ret) : "r" (paddr) : "memory");
395 return ret;
396}
397
398static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
399{
400 u64 ret;
401 __asm__ __volatile__("ldcix %0,0, %1"
402 : "=r" (ret) : "r" (paddr) : "memory");
403 return ret;
404}
405#endif
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420
421#ifdef CONFIG_PPC32
422
423#define __do_in_asm(name, op) \
424static inline unsigned int name(unsigned int port) \
425{ \
426 unsigned int x; \
427 __asm__ __volatile__( \
428 "sync\n" \
429 "0:" op " %0,0,%1\n" \
430 "1: twi 0,%0,0\n" \
431 "2: isync\n" \
432 "3: nop\n" \
433 "4:\n" \
434 ".section .fixup,\"ax\"\n" \
435 "5: li %0,-1\n" \
436 " b 4b\n" \
437 ".previous\n" \
438 EX_TABLE(0b, 5b) \
439 EX_TABLE(1b, 5b) \
440 EX_TABLE(2b, 5b) \
441 EX_TABLE(3b, 5b) \
442 : "=&r" (x) \
443 : "r" (port + _IO_BASE) \
444 : "memory"); \
445 return x; \
446}
447
448#define __do_out_asm(name, op) \
449static inline void name(unsigned int val, unsigned int port) \
450{ \
451 __asm__ __volatile__( \
452 "sync\n" \
453 "0:" op " %0,0,%1\n" \
454 "1: sync\n" \
455 "2:\n" \
456 EX_TABLE(0b, 2b) \
457 EX_TABLE(1b, 2b) \
458 : : "r" (val), "r" (port + _IO_BASE) \
459 : "memory"); \
460}
461
462__do_in_asm(_rec_inb, "lbzx")
463__do_in_asm(_rec_inw, "lhbrx")
464__do_in_asm(_rec_inl, "lwbrx")
465__do_out_asm(_rec_outb, "stbx")
466__do_out_asm(_rec_outw, "sthbrx")
467__do_out_asm(_rec_outl, "stwbrx")
468
469#endif
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486#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
487#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
488#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
489#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
490#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
491#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
492#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
493
494#ifdef CONFIG_EEH
495#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
496#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
497#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
498#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
499#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
500#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
501#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
502#else
503#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
504#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
505#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
506#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
507#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
508#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
509#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
510#endif
511
512#ifdef CONFIG_PPC32
513#define __do_outb(val, port) _rec_outb(val, port)
514#define __do_outw(val, port) _rec_outw(val, port)
515#define __do_outl(val, port) _rec_outl(val, port)
516#define __do_inb(port) _rec_inb(port)
517#define __do_inw(port) _rec_inw(port)
518#define __do_inl(port) _rec_inl(port)
519#else
520#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
521#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
522#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
523#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
524#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
525#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
526#endif
527
528#ifdef CONFIG_EEH
529#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
530#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
531#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
532#else
533#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
534#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
535#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
536#endif
537#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
538#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
539#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
540
541#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
542#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
543#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
544#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
545#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
546#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
547
548#define __do_memset_io(addr, c, n) \
549 _memset_io(PCI_FIX_ADDR(addr), c, n)
550#define __do_memcpy_toio(dst, src, n) \
551 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
552
553#ifdef CONFIG_EEH
554#define __do_memcpy_fromio(dst, src, n) \
555 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
556#else
557#define __do_memcpy_fromio(dst, src, n) \
558 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
559#endif
560
561#ifdef CONFIG_PPC_INDIRECT_PIO
562#define DEF_PCI_HOOK_pio(x) x
563#else
564#define DEF_PCI_HOOK_pio(x) NULL
565#endif
566
567#ifdef CONFIG_PPC_INDIRECT_MMIO
568#define DEF_PCI_HOOK_mem(x) x
569#else
570#define DEF_PCI_HOOK_mem(x) NULL
571#endif
572
573
574extern struct ppc_pci_io {
575
576#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
577#define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
578
579#include <asm/io-defs.h>
580
581#undef DEF_PCI_AC_RET
582#undef DEF_PCI_AC_NORET
583
584} ppc_pci_io;
585
586
587#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
588static inline ret name at \
589{ \
590 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
591 return ppc_pci_io.name al; \
592 return __do_##name al; \
593}
594
595#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
596static inline void name at \
597{ \
598 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
599 ppc_pci_io.name al; \
600 else \
601 __do_##name al; \
602}
603
604#include <asm/io-defs.h>
605
606#undef DEF_PCI_AC_RET
607#undef DEF_PCI_AC_NORET
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611
612#ifdef __powerpc64__
613#define readq readq
614#define writeq writeq
615#endif
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621#define xlate_dev_mem_ptr(p) __va(p)
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626#define xlate_dev_kmem_ptr(p) p
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631#define readb_relaxed(addr) readb(addr)
632#define readw_relaxed(addr) readw(addr)
633#define readl_relaxed(addr) readl(addr)
634#define readq_relaxed(addr) readq(addr)
635#define writeb_relaxed(v, addr) writeb(v, addr)
636#define writew_relaxed(v, addr) writew(v, addr)
637#define writel_relaxed(v, addr) writel(v, addr)
638#define writeq_relaxed(v, addr) writeq(v, addr)
639
640#include <asm-generic/iomap.h>
641
642static inline void iosync(void)
643{
644 __asm__ __volatile__ ("sync" : : : "memory");
645}
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653
654#define iobarrier_rw() eieio()
655#define iobarrier_r() eieio()
656#define iobarrier_w() eieio()
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662
663#define inb_p(port) inb(port)
664#define outb_p(val, port) (udelay(1), outb((val), (port)))
665#define inw_p(port) inw(port)
666#define outw_p(val, port) (udelay(1), outw((val), (port)))
667#define inl_p(port) inl(port)
668#define outl_p(val, port) (udelay(1), outl((val), (port)))
669
670
671#define IO_SPACE_LIMIT ~(0UL)
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705extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
706extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
707 unsigned long flags);
708extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
709void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
710void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
711#define ioremap_uc(addr, size) ioremap((addr), (size))
712#define ioremap_cache(addr, size) \
713 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
714
715extern void iounmap(volatile void __iomem *addr);
716
717void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
718
719int early_ioremap_range(unsigned long ea, phys_addr_t pa,
720 unsigned long size, pgprot_t prot);
721void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
722 pgprot_t prot, void *caller);
723
724extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
725 pgprot_t prot, void *caller);
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733#define HAVE_ARCH_PIO_SIZE 1
734#define PIO_OFFSET 0x00000000UL
735#define PIO_MASK (FULL_IO_SIZE - 1)
736#define PIO_RESERVED (FULL_IO_SIZE)
737
738#define mmio_read16be(addr) readw_be(addr)
739#define mmio_read32be(addr) readl_be(addr)
740#define mmio_read64be(addr) readq_be(addr)
741#define mmio_write16be(val, addr) writew_be(val, addr)
742#define mmio_write32be(val, addr) writel_be(val, addr)
743#define mmio_write64be(val, addr) writeq_be(val, addr)
744#define mmio_insb(addr, dst, count) readsb(addr, dst, count)
745#define mmio_insw(addr, dst, count) readsw(addr, dst, count)
746#define mmio_insl(addr, dst, count) readsl(addr, dst, count)
747#define mmio_outsb(addr, src, count) writesb(addr, src, count)
748#define mmio_outsw(addr, src, count) writesw(addr, src, count)
749#define mmio_outsl(addr, src, count) writesl(addr, src, count)
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763static inline unsigned long virt_to_phys(volatile void * address)
764{
765 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
766
767 return __pa((unsigned long)address);
768}
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781
782static inline void * phys_to_virt(unsigned long address)
783{
784 return (void *)__va(address);
785}
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789
790static inline phys_addr_t page_to_phys(struct page *page)
791{
792 unsigned long pfn = page_to_pfn(page);
793
794 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
795
796 return PFN_PHYS(pfn);
797}
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805#ifdef CONFIG_PPC32
806
807static inline unsigned long virt_to_bus(volatile void * address)
808{
809 if (address == NULL)
810 return 0;
811 return __pa(address) + PCI_DRAM_OFFSET;
812}
813
814static inline void * bus_to_virt(unsigned long address)
815{
816 if (address == 0)
817 return NULL;
818 return __va(address - PCI_DRAM_OFFSET);
819}
820
821#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
822
823#endif
824
825
826#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
827#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
828
829#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
830#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
831
832#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
833#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
834
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841
842#define clrsetbits(type, addr, clear, set) \
843 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
844
845#ifdef __powerpc64__
846#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
847#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
848#endif
849
850#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
851#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
852
853#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
854#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
855
856#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
857
858#endif
859
860#endif
861