1
2#ifndef _ASM_POWERPC_PCI_BRIDGE_H
3#define _ASM_POWERPC_PCI_BRIDGE_H
4#ifdef __KERNEL__
5
6
7#include <linux/pci.h>
8#include <linux/list.h>
9#include <linux/ioport.h>
10#include <linux/numa.h>
11
12struct device_node;
13
14
15
16
17struct pci_controller_ops {
18 void (*dma_dev_setup)(struct pci_dev *pdev);
19 void (*dma_bus_setup)(struct pci_bus *bus);
20 bool (*iommu_bypass_supported)(struct pci_dev *pdev,
21 u64 mask);
22
23 int (*probe_mode)(struct pci_bus *bus);
24
25
26
27 bool (*enable_device_hook)(struct pci_dev *pdev);
28
29 void (*disable_device)(struct pci_dev *pdev);
30
31 void (*release_device)(struct pci_dev *pdev);
32
33
34 resource_size_t (*window_alignment)(struct pci_bus *bus,
35 unsigned long type);
36 void (*setup_bridge)(struct pci_bus *bus,
37 unsigned long type);
38 void (*reset_secondary_bus)(struct pci_dev *pdev);
39
40#ifdef CONFIG_PCI_MSI
41 int (*setup_msi_irqs)(struct pci_dev *pdev,
42 int nvec, int type);
43 void (*teardown_msi_irqs)(struct pci_dev *pdev);
44#endif
45
46 void (*shutdown)(struct pci_controller *hose);
47};
48
49
50
51
52struct pci_controller {
53 struct pci_bus *bus;
54 char is_dynamic;
55#ifdef CONFIG_PPC64
56 int node;
57#endif
58 struct device_node *dn;
59 struct list_head list_node;
60 struct device *parent;
61
62 int first_busno;
63 int last_busno;
64 int self_busno;
65 struct resource busn;
66
67 void __iomem *io_base_virt;
68#ifdef CONFIG_PPC64
69 void __iomem *io_base_alloc;
70#endif
71 resource_size_t io_base_phys;
72 resource_size_t pci_io_size;
73
74
75
76
77
78 resource_size_t isa_mem_phys;
79 resource_size_t isa_mem_size;
80
81 struct pci_controller_ops controller_ops;
82 struct pci_ops *ops;
83 unsigned int __iomem *cfg_addr;
84 void __iomem *cfg_data;
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
105#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
106#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
107#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
108#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
109#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
110#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
111 u32 indirect_type;
112
113
114
115 struct resource io_resource;
116 struct resource mem_resources[3];
117 resource_size_t mem_offset[3];
118 int global_number;
119
120 resource_size_t dma_window_base_cur;
121 resource_size_t dma_window_size;
122
123#ifdef CONFIG_PPC64
124 unsigned long buid;
125 struct pci_dn *pci_data;
126#endif
127
128 void *private_data;
129 struct npu *npu;
130};
131
132
133
134extern int early_read_config_byte(struct pci_controller *hose, int bus,
135 int dev_fn, int where, u8 *val);
136extern int early_read_config_word(struct pci_controller *hose, int bus,
137 int dev_fn, int where, u16 *val);
138extern int early_read_config_dword(struct pci_controller *hose, int bus,
139 int dev_fn, int where, u32 *val);
140extern int early_write_config_byte(struct pci_controller *hose, int bus,
141 int dev_fn, int where, u8 val);
142extern int early_write_config_word(struct pci_controller *hose, int bus,
143 int dev_fn, int where, u16 val);
144extern int early_write_config_dword(struct pci_controller *hose, int bus,
145 int dev_fn, int where, u32 val);
146
147extern int early_find_capability(struct pci_controller *hose, int bus,
148 int dev_fn, int cap);
149
150extern void setup_indirect_pci(struct pci_controller* hose,
151 resource_size_t cfg_addr,
152 resource_size_t cfg_data, u32 flags);
153
154extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
155 int offset, int len, u32 *val);
156
157extern int __indirect_read_config(struct pci_controller *hose,
158 unsigned char bus_number, unsigned int devfn,
159 int offset, int len, u32 *val);
160
161extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
162 int offset, int len, u32 val);
163
164static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
165{
166 return bus->sysdata;
167}
168
169#ifndef CONFIG_PPC64
170
171extern int pci_device_from_OF_node(struct device_node *node,
172 u8 *bus, u8 *devfn);
173extern void pci_create_OF_bus_map(void);
174
175#else
176
177
178
179
180
181struct iommu_table;
182
183struct pci_dn {
184 int flags;
185#define PCI_DN_FLAG_IOV_VF 0x01
186#define PCI_DN_FLAG_DEAD 0x02
187
188 int busno;
189 int devfn;
190 int vendor_id;
191 int device_id;
192 int class_code;
193
194 struct pci_dn *parent;
195 struct pci_controller *phb;
196 struct iommu_table_group *table_group;
197
198 int pci_ext_config_space;
199#ifdef CONFIG_EEH
200 struct eeh_dev *edev;
201#endif
202#define IODA_INVALID_PE 0xFFFFFFFF
203 unsigned int pe_number;
204#ifdef CONFIG_PCI_IOV
205 u16 vfs_expanded;
206 u16 num_vfs;
207 unsigned int *pe_num_map;
208 bool m64_single_mode;
209#define IODA_INVALID_M64 (-1)
210 int (*m64_map)[PCI_SRIOV_NUM_BARS];
211 int last_allow_rc;
212#endif
213 int mps;
214 struct list_head child_list;
215 struct list_head list;
216 struct resource holes[PCI_SRIOV_NUM_BARS];
217};
218
219
220#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
221
222extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
223 int devfn);
224extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
225extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
226 struct device_node *dn);
227extern void pci_remove_device_node_info(struct device_node *dn);
228
229#ifdef CONFIG_PCI_IOV
230struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
231void remove_sriov_vf_pdns(struct pci_dev *pdev);
232#endif
233
234static inline int pci_device_from_OF_node(struct device_node *np,
235 u8 *bus, u8 *devfn)
236{
237 if (!PCI_DN(np))
238 return -ENODEV;
239 *bus = PCI_DN(np)->busno;
240 *devfn = PCI_DN(np)->devfn;
241 return 0;
242}
243
244#if defined(CONFIG_EEH)
245static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
246{
247 return pdn ? pdn->edev : NULL;
248}
249#else
250#define pdn_to_eeh_dev(x) (NULL)
251#endif
252
253
254extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
255
256
257extern void pci_hp_remove_devices(struct pci_bus *bus);
258
259
260extern void pci_hp_add_devices(struct pci_bus *bus);
261
262extern int pcibios_unmap_io_space(struct pci_bus *bus);
263extern int pcibios_map_io_space(struct pci_bus *bus);
264
265#ifdef CONFIG_NUMA
266#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
267#else
268#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
269#endif
270
271#endif
272
273
274extern struct pci_controller *pci_find_hose_for_OF_device(
275 struct device_node* node);
276
277extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
278
279
280extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281 struct device_node *dev, int primary);
282
283
284extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
285extern void pcibios_free_controller(struct pci_controller *phb);
286extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
287
288#ifdef CONFIG_PCI
289extern int pcibios_vaddr_is_ioport(void __iomem *address);
290#else
291static inline int pcibios_vaddr_is_ioport(void __iomem *address)
292{
293 return 0;
294}
295#endif
296
297#endif
298#endif
299