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15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/export.h>
21#include <linux/of_address.h>
22#include <linux/of_pci.h>
23#include <linux/mm.h>
24#include <linux/shmem_fs.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/vgaarb.h>
31#include <linux/numa.h>
32
33#include <asm/processor.h>
34#include <asm/io.h>
35#include <asm/prom.h>
36#include <asm/pci-bridge.h>
37#include <asm/byteorder.h>
38#include <asm/machdep.h>
39#include <asm/ppc-pci.h>
40#include <asm/eeh.h>
41
42#include "../../../drivers/pci/pci.h"
43
44
45static DEFINE_SPINLOCK(hose_spinlock);
46LIST_HEAD(hose_list);
47
48
49#define MAX_PHBS 0x10000
50
51
52
53
54
55static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
56
57
58resource_size_t isa_mem_base;
59EXPORT_SYMBOL(isa_mem_base);
60
61
62static const struct dma_map_ops *pci_dma_ops;
63
64void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
65{
66 pci_dma_ops = dma_ops;
67}
68
69
70
71
72
73static int get_phb_number(struct device_node *dn)
74{
75 int ret, phb_id = -1;
76 u32 prop_32;
77 u64 prop;
78
79
80
81
82
83
84 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
85 if (ret) {
86 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
87 prop = prop_32;
88 }
89
90 if (!ret)
91 phb_id = (int)(prop & (MAX_PHBS - 1));
92
93
94 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
95 return phb_id;
96
97
98
99
100
101 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
102 BUG_ON(phb_id >= MAX_PHBS);
103 set_bit(phb_id, phb_bitmap);
104
105 return phb_id;
106}
107
108struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
109{
110 struct pci_controller *phb;
111
112 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
113 if (phb == NULL)
114 return NULL;
115 spin_lock(&hose_spinlock);
116 phb->global_number = get_phb_number(dev);
117 list_add_tail(&phb->list_node, &hose_list);
118 spin_unlock(&hose_spinlock);
119 phb->dn = dev;
120 phb->is_dynamic = slab_is_available();
121#ifdef CONFIG_PPC64
122 if (dev) {
123 int nid = of_node_to_nid(dev);
124
125 if (nid < 0 || !node_online(nid))
126 nid = NUMA_NO_NODE;
127
128 PHB_SET_NODE(phb, nid);
129 }
130#endif
131 return phb;
132}
133EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
134
135void pcibios_free_controller(struct pci_controller *phb)
136{
137 spin_lock(&hose_spinlock);
138
139
140 if (phb->global_number < MAX_PHBS)
141 clear_bit(phb->global_number, phb_bitmap);
142
143 list_del(&phb->list_node);
144 spin_unlock(&hose_spinlock);
145
146 if (phb->is_dynamic)
147 kfree(phb);
148}
149EXPORT_SYMBOL_GPL(pcibios_free_controller);
150
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174
175
176void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
177{
178 struct pci_controller *phb = (struct pci_controller *)
179 bridge->release_data;
180
181 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
182
183 pcibios_free_controller(phb);
184}
185EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
186
187
188
189
190
191
192
193resource_size_t pcibios_window_alignment(struct pci_bus *bus,
194 unsigned long type)
195{
196 struct pci_controller *phb = pci_bus_to_host(bus);
197
198 if (phb->controller_ops.window_alignment)
199 return phb->controller_ops.window_alignment(bus, type);
200
201
202
203
204
205
206 return 1;
207}
208
209void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
210{
211 struct pci_controller *hose = pci_bus_to_host(bus);
212
213 if (hose->controller_ops.setup_bridge)
214 hose->controller_ops.setup_bridge(bus, type);
215}
216
217void pcibios_reset_secondary_bus(struct pci_dev *dev)
218{
219 struct pci_controller *phb = pci_bus_to_host(dev->bus);
220
221 if (phb->controller_ops.reset_secondary_bus) {
222 phb->controller_ops.reset_secondary_bus(dev);
223 return;
224 }
225
226 pci_reset_secondary_bus(dev);
227}
228
229resource_size_t pcibios_default_alignment(void)
230{
231 if (ppc_md.pcibios_default_alignment)
232 return ppc_md.pcibios_default_alignment();
233
234 return 0;
235}
236
237#ifdef CONFIG_PCI_IOV
238resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
239{
240 if (ppc_md.pcibios_iov_resource_alignment)
241 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
242
243 return pci_iov_resource_size(pdev, resno);
244}
245
246int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
247{
248 if (ppc_md.pcibios_sriov_enable)
249 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
250
251 return 0;
252}
253
254int pcibios_sriov_disable(struct pci_dev *pdev)
255{
256 if (ppc_md.pcibios_sriov_disable)
257 return ppc_md.pcibios_sriov_disable(pdev);
258
259 return 0;
260}
261
262#endif
263
264static resource_size_t pcibios_io_size(const struct pci_controller *hose)
265{
266#ifdef CONFIG_PPC64
267 return hose->pci_io_size;
268#else
269 return resource_size(&hose->io_resource);
270#endif
271}
272
273int pcibios_vaddr_is_ioport(void __iomem *address)
274{
275 int ret = 0;
276 struct pci_controller *hose;
277 resource_size_t size;
278
279 spin_lock(&hose_spinlock);
280 list_for_each_entry(hose, &hose_list, list_node) {
281 size = pcibios_io_size(hose);
282 if (address >= hose->io_base_virt &&
283 address < (hose->io_base_virt + size)) {
284 ret = 1;
285 break;
286 }
287 }
288 spin_unlock(&hose_spinlock);
289 return ret;
290}
291
292unsigned long pci_address_to_pio(phys_addr_t address)
293{
294 struct pci_controller *hose;
295 resource_size_t size;
296 unsigned long ret = ~0;
297
298 spin_lock(&hose_spinlock);
299 list_for_each_entry(hose, &hose_list, list_node) {
300 size = pcibios_io_size(hose);
301 if (address >= hose->io_base_phys &&
302 address < (hose->io_base_phys + size)) {
303 unsigned long base =
304 (unsigned long)hose->io_base_virt - _IO_BASE;
305 ret = base + (address - hose->io_base_phys);
306 break;
307 }
308 }
309 spin_unlock(&hose_spinlock);
310
311 return ret;
312}
313EXPORT_SYMBOL_GPL(pci_address_to_pio);
314
315
316
317
318int pci_domain_nr(struct pci_bus *bus)
319{
320 struct pci_controller *hose = pci_bus_to_host(bus);
321
322 return hose->global_number;
323}
324EXPORT_SYMBOL(pci_domain_nr);
325
326
327
328
329
330
331
332
333struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
334{
335 while(node) {
336 struct pci_controller *hose, *tmp;
337 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
338 if (hose->dn == node)
339 return hose;
340 node = node->parent;
341 }
342 return NULL;
343}
344
345struct pci_controller *pci_find_controller_for_domain(int domain_nr)
346{
347 struct pci_controller *hose;
348
349 list_for_each_entry(hose, &hose_list, list_node)
350 if (hose->global_number == domain_nr)
351 return hose;
352
353 return NULL;
354}
355
356
357
358
359
360
361static int pci_read_irq_line(struct pci_dev *pci_dev)
362{
363 int virq;
364
365 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
366
367
368 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
369 if (virq <= 0) {
370 u8 line, pin;
371
372
373
374
375
376
377
378
379 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
380 return -1;
381 if (pin == 0)
382 return -1;
383 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
384 line == 0xff || line == 0) {
385 return -1;
386 }
387 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
388 line, pin);
389
390 virq = irq_create_mapping(NULL, line);
391 if (virq)
392 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
393 }
394
395 if (!virq) {
396 pr_debug(" Failed to map !\n");
397 return -1;
398 }
399
400 pr_debug(" Mapped to linux irq %d\n", virq);
401
402 pci_dev->irq = virq;
403
404 return 0;
405}
406
407
408
409
410
411int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
412{
413 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
414 resource_size_t ioaddr = pci_resource_start(pdev, bar);
415
416 if (!hose)
417 return -EINVAL;
418
419
420 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
421
422 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
423 return 0;
424}
425
426
427
428
429
430
431pgprot_t pci_phys_mem_access_prot(struct file *file,
432 unsigned long pfn,
433 unsigned long size,
434 pgprot_t prot)
435{
436 struct pci_dev *pdev = NULL;
437 struct resource *found = NULL;
438 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
439 int i;
440
441 if (page_is_ram(pfn))
442 return prot;
443
444 prot = pgprot_noncached(prot);
445 for_each_pci_dev(pdev) {
446 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
447 struct resource *rp = &pdev->resource[i];
448 int flags = rp->flags;
449
450
451 if ((flags & IORESOURCE_MEM) == 0)
452 continue;
453
454 if (offset < (rp->start & PAGE_MASK) ||
455 offset > rp->end)
456 continue;
457 found = rp;
458 break;
459 }
460 if (found)
461 break;
462 }
463 if (found) {
464 if (found->flags & IORESOURCE_PREFETCH)
465 prot = pgprot_noncached_wc(prot);
466 pci_dev_put(pdev);
467 }
468
469 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
470 (unsigned long long)offset, pgprot_val(prot));
471
472 return prot;
473}
474
475
476int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
477{
478 unsigned long offset;
479 struct pci_controller *hose = pci_bus_to_host(bus);
480 struct resource *rp = &hose->io_resource;
481 void __iomem *addr;
482
483
484
485
486
487
488 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
489 offset += port;
490
491 if (!(rp->flags & IORESOURCE_IO))
492 return -ENXIO;
493 if (offset < rp->start || (offset + size) > rp->end)
494 return -ENXIO;
495 addr = hose->io_base_virt + port;
496
497 switch(size) {
498 case 1:
499 *((u8 *)val) = in_8(addr);
500 return 1;
501 case 2:
502 if (port & 1)
503 return -EINVAL;
504 *((u16 *)val) = in_le16(addr);
505 return 2;
506 case 4:
507 if (port & 3)
508 return -EINVAL;
509 *((u32 *)val) = in_le32(addr);
510 return 4;
511 }
512 return -EINVAL;
513}
514
515
516int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
517{
518 unsigned long offset;
519 struct pci_controller *hose = pci_bus_to_host(bus);
520 struct resource *rp = &hose->io_resource;
521 void __iomem *addr;
522
523
524
525
526
527
528 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
529 offset += port;
530
531 if (!(rp->flags & IORESOURCE_IO))
532 return -ENXIO;
533 if (offset < rp->start || (offset + size) > rp->end)
534 return -ENXIO;
535 addr = hose->io_base_virt + port;
536
537
538
539
540
541
542 switch(size) {
543 case 1:
544 out_8(addr, val >> 24);
545 return 1;
546 case 2:
547 if (port & 1)
548 return -EINVAL;
549 out_le16(addr, val >> 16);
550 return 2;
551 case 4:
552 if (port & 3)
553 return -EINVAL;
554 out_le32(addr, val);
555 return 4;
556 }
557 return -EINVAL;
558}
559
560
561int pci_mmap_legacy_page_range(struct pci_bus *bus,
562 struct vm_area_struct *vma,
563 enum pci_mmap_state mmap_state)
564{
565 struct pci_controller *hose = pci_bus_to_host(bus);
566 resource_size_t offset =
567 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
568 resource_size_t size = vma->vm_end - vma->vm_start;
569 struct resource *rp;
570
571 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
572 pci_domain_nr(bus), bus->number,
573 mmap_state == pci_mmap_mem ? "MEM" : "IO",
574 (unsigned long long)offset,
575 (unsigned long long)(offset + size - 1));
576
577 if (mmap_state == pci_mmap_mem) {
578
579
580
581
582
583
584
585 if ((offset + size) > hose->isa_mem_size) {
586 printk(KERN_DEBUG
587 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
588 current->comm, current->pid, pci_domain_nr(bus), bus->number);
589 if (vma->vm_flags & VM_SHARED)
590 return shmem_zero_setup(vma);
591 return 0;
592 }
593 offset += hose->isa_mem_phys;
594 } else {
595 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
596 unsigned long roffset = offset + io_offset;
597 rp = &hose->io_resource;
598 if (!(rp->flags & IORESOURCE_IO))
599 return -ENXIO;
600 if (roffset < rp->start || (roffset + size) > rp->end)
601 return -ENXIO;
602 offset += hose->io_base_phys;
603 }
604 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
605
606 vma->vm_pgoff = offset >> PAGE_SHIFT;
607 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
608 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
609 vma->vm_end - vma->vm_start,
610 vma->vm_page_prot);
611}
612
613void pci_resource_to_user(const struct pci_dev *dev, int bar,
614 const struct resource *rsrc,
615 resource_size_t *start, resource_size_t *end)
616{
617 struct pci_bus_region region;
618
619 if (rsrc->flags & IORESOURCE_IO) {
620 pcibios_resource_to_bus(dev->bus, ®ion,
621 (struct resource *) rsrc);
622 *start = region.start;
623 *end = region.end;
624 return;
625 }
626
627
628
629
630
631
632
633
634 *start = rsrc->start;
635 *end = rsrc->end;
636}
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661
662void pci_process_bridge_OF_ranges(struct pci_controller *hose,
663 struct device_node *dev, int primary)
664{
665 int memno = 0;
666 struct resource *res;
667 struct of_pci_range range;
668 struct of_pci_range_parser parser;
669
670 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
671 dev, primary ? "(primary)" : "");
672
673
674 if (of_pci_range_parser_init(&parser, dev))
675 return;
676
677
678 for_each_of_pci_range(&parser, &range) {
679
680
681
682
683
684 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
685 continue;
686
687
688 res = NULL;
689 switch (range.flags & IORESOURCE_TYPE_BITS) {
690 case IORESOURCE_IO:
691 printk(KERN_INFO
692 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
693 range.cpu_addr, range.cpu_addr + range.size - 1,
694 range.pci_addr);
695
696
697 if (hose->pci_io_size) {
698 printk(KERN_INFO
699 " \\--> Skipped (too many) !\n");
700 continue;
701 }
702#ifdef CONFIG_PPC32
703
704 if (range.size > 0x01000000)
705 range.size = 0x01000000;
706
707
708 hose->io_base_virt = ioremap(range.cpu_addr,
709 range.size);
710
711
712 if (primary)
713 isa_io_base =
714 (unsigned long)hose->io_base_virt;
715#endif
716
717
718
719 hose->pci_io_size = range.pci_addr + range.size;
720 hose->io_base_phys = range.cpu_addr - range.pci_addr;
721
722
723 res = &hose->io_resource;
724 range.cpu_addr = range.pci_addr;
725 break;
726 case IORESOURCE_MEM:
727 printk(KERN_INFO
728 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
729 range.cpu_addr, range.cpu_addr + range.size - 1,
730 range.pci_addr,
731 (range.flags & IORESOURCE_PREFETCH) ?
732 "Prefetch" : "");
733
734
735 if (memno >= 3) {
736 printk(KERN_INFO
737 " \\--> Skipped (too many) !\n");
738 continue;
739 }
740
741 if (range.pci_addr == 0) {
742 if (primary || isa_mem_base == 0)
743 isa_mem_base = range.cpu_addr;
744 hose->isa_mem_phys = range.cpu_addr;
745 hose->isa_mem_size = range.size;
746 }
747
748
749 hose->mem_offset[memno] = range.cpu_addr -
750 range.pci_addr;
751 res = &hose->mem_resources[memno++];
752 break;
753 }
754 if (res != NULL) {
755 res->name = dev->full_name;
756 res->flags = range.flags;
757 res->start = range.cpu_addr;
758 res->end = range.cpu_addr + range.size - 1;
759 res->parent = res->child = res->sibling = NULL;
760 }
761 }
762}
763
764
765int pci_proc_domain(struct pci_bus *bus)
766{
767 struct pci_controller *hose = pci_bus_to_host(bus);
768
769 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
770 return 0;
771 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
772 return hose->global_number != 0;
773 return 1;
774}
775
776int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
777{
778 if (ppc_md.pcibios_root_bridge_prepare)
779 return ppc_md.pcibios_root_bridge_prepare(bridge);
780
781 return 0;
782}
783
784
785
786
787static void pcibios_fixup_resources(struct pci_dev *dev)
788{
789 struct pci_controller *hose = pci_bus_to_host(dev->bus);
790 int i;
791
792 if (!hose) {
793 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
794 pci_name(dev));
795 return;
796 }
797
798 if (dev->is_virtfn)
799 return;
800
801 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
802 struct resource *res = dev->resource + i;
803 struct pci_bus_region reg;
804 if (!res->flags)
805 continue;
806
807
808
809
810
811
812 pcibios_resource_to_bus(dev->bus, ®, res);
813 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
814 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
815
816 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
817 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
818 pci_name(dev), i, res);
819 res->end -= res->start;
820 res->start = 0;
821 res->flags |= IORESOURCE_UNSET;
822 continue;
823 }
824
825 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
826 }
827
828
829 if (ppc_md.pcibios_fixup_resources)
830 ppc_md.pcibios_fixup_resources(dev);
831}
832DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
833
834
835
836
837
838
839static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
840 struct resource *res)
841{
842 struct pci_controller *hose = pci_bus_to_host(bus);
843 struct pci_dev *dev = bus->self;
844 resource_size_t offset;
845 struct pci_bus_region region;
846 u16 command;
847 int i;
848
849
850 if (pci_has_flag(PCI_PROBE_ONLY))
851 return 0;
852
853
854 if (res->flags & IORESOURCE_MEM) {
855 pcibios_resource_to_bus(dev->bus, ®ion, res);
856
857
858 if (region.start != 0)
859 return 0;
860
861
862
863
864 pci_read_config_word(dev, PCI_COMMAND, &command);
865 if ((command & PCI_COMMAND_MEMORY) == 0)
866 return 1;
867
868
869
870
871
872 for (i = 0; i < 3; i++) {
873 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
874 hose->mem_resources[i].start == hose->mem_offset[i])
875 return 0;
876 }
877
878
879
880
881 return 1;
882 } else {
883
884 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
885 if (((res->start - offset) & 0xfffffffful) != 0)
886 return 0;
887
888
889
890
891
892
893 pci_read_config_word(dev, PCI_COMMAND, &command);
894 if (command & PCI_COMMAND_IO)
895 return 0;
896
897
898
899
900 return 1;
901 }
902}
903
904
905static void pcibios_fixup_bridge(struct pci_bus *bus)
906{
907 struct resource *res;
908 int i;
909
910 struct pci_dev *dev = bus->self;
911
912 pci_bus_for_each_resource(bus, res, i) {
913 if (!res || !res->flags)
914 continue;
915 if (i >= 3 && bus->self->transparent)
916 continue;
917
918
919
920
921
922 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
923 res->flags |= IORESOURCE_UNSET;
924 res->start = 0;
925 res->end = -1;
926 continue;
927 }
928
929 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
930
931
932
933
934 if (pcibios_uninitialized_bridge_resource(bus, res)) {
935 res->flags = 0;
936 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
937 }
938 }
939}
940
941void pcibios_setup_bus_self(struct pci_bus *bus)
942{
943 struct pci_controller *phb;
944
945
946 if (bus->self != NULL)
947 pcibios_fixup_bridge(bus);
948
949
950
951
952 if (ppc_md.pcibios_fixup_bus)
953 ppc_md.pcibios_fixup_bus(bus);
954
955
956 phb = pci_bus_to_host(bus);
957 if (phb->controller_ops.dma_bus_setup)
958 phb->controller_ops.dma_bus_setup(bus);
959}
960
961void pcibios_bus_add_device(struct pci_dev *dev)
962{
963 struct pci_controller *phb;
964
965
966
967 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
968
969
970 set_dma_ops(&dev->dev, pci_dma_ops);
971 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
972
973
974 phb = pci_bus_to_host(dev->bus);
975 if (phb->controller_ops.dma_dev_setup)
976 phb->controller_ops.dma_dev_setup(dev);
977
978
979 pci_read_irq_line(dev);
980 if (ppc_md.pci_irq_fixup)
981 ppc_md.pci_irq_fixup(dev);
982
983 if (ppc_md.pcibios_bus_add_device)
984 ppc_md.pcibios_bus_add_device(dev);
985}
986
987int pcibios_add_device(struct pci_dev *dev)
988{
989#ifdef CONFIG_PCI_IOV
990 if (ppc_md.pcibios_fixup_sriov)
991 ppc_md.pcibios_fixup_sriov(dev);
992#endif
993
994 return 0;
995}
996
997void pcibios_set_master(struct pci_dev *dev)
998{
999
1000}
1001
1002void pcibios_fixup_bus(struct pci_bus *bus)
1003{
1004
1005
1006
1007
1008 pci_read_bridge_bases(bus);
1009
1010
1011 pcibios_setup_bus_self(bus);
1012}
1013EXPORT_SYMBOL(pcibios_fixup_bus);
1014
1015static int skip_isa_ioresource_align(struct pci_dev *dev)
1016{
1017 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1018 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1019 return 1;
1020 return 0;
1021}
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1037 resource_size_t size, resource_size_t align)
1038{
1039 struct pci_dev *dev = data;
1040 resource_size_t start = res->start;
1041
1042 if (res->flags & IORESOURCE_IO) {
1043 if (skip_isa_ioresource_align(dev))
1044 return start;
1045 if (start & 0x300)
1046 start = (start + 0x3ff) & ~0x3ff;
1047 }
1048
1049 return start;
1050}
1051EXPORT_SYMBOL(pcibios_align_resource);
1052
1053
1054
1055
1056
1057static int reparent_resources(struct resource *parent,
1058 struct resource *res)
1059{
1060 struct resource *p, **pp;
1061 struct resource **firstpp = NULL;
1062
1063 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1064 if (p->end < res->start)
1065 continue;
1066 if (res->end < p->start)
1067 break;
1068 if (p->start < res->start || p->end > res->end)
1069 return -1;
1070 if (firstpp == NULL)
1071 firstpp = pp;
1072 }
1073 if (firstpp == NULL)
1074 return -1;
1075 res->parent = parent;
1076 res->child = *firstpp;
1077 res->sibling = *pp;
1078 *firstpp = res;
1079 *pp = NULL;
1080 for (p = res->child; p != NULL; p = p->sibling) {
1081 p->parent = res;
1082 pr_debug("PCI: Reparented %s %pR under %s\n",
1083 p->name, p, res->name);
1084 }
1085 return 0;
1086}
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1122{
1123 struct pci_bus *b;
1124 int i;
1125 struct resource *res, *pr;
1126
1127 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1128 pci_domain_nr(bus), bus->number);
1129
1130 pci_bus_for_each_resource(bus, res, i) {
1131 if (!res || !res->flags || res->start > res->end || res->parent)
1132 continue;
1133
1134
1135 if (res->flags & IORESOURCE_UNSET)
1136 goto clear_resource;
1137
1138 if (bus->parent == NULL)
1139 pr = (res->flags & IORESOURCE_IO) ?
1140 &ioport_resource : &iomem_resource;
1141 else {
1142 pr = pci_find_parent_resource(bus->self, res);
1143 if (pr == res) {
1144
1145
1146
1147
1148 continue;
1149 }
1150 }
1151
1152 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1153 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1154 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1155
1156 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1157 struct pci_dev *dev = bus->self;
1158
1159 if (request_resource(pr, res) == 0)
1160 continue;
1161
1162
1163
1164
1165
1166 if (reparent_resources(pr, res) == 0)
1167 continue;
1168
1169 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1170 pci_claim_bridge_resource(dev,
1171 i + PCI_BRIDGE_RESOURCES) == 0)
1172 continue;
1173 }
1174 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1175 i, bus->number);
1176 clear_resource:
1177
1178
1179
1180
1181
1182
1183 res->start = 0;
1184 res->end = -1;
1185 res->flags = 0;
1186 }
1187
1188 list_for_each_entry(b, &bus->children, node)
1189 pcibios_allocate_bus_resources(b);
1190}
1191
1192static inline void alloc_resource(struct pci_dev *dev, int idx)
1193{
1194 struct resource *pr, *r = &dev->resource[idx];
1195
1196 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1197 pci_name(dev), idx, r);
1198
1199 pr = pci_find_parent_resource(dev, r);
1200 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1201 request_resource(pr, r) < 0) {
1202 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1203 " of device %s, will remap\n", idx, pci_name(dev));
1204 if (pr)
1205 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1206
1207 r->flags |= IORESOURCE_UNSET;
1208 r->end -= r->start;
1209 r->start = 0;
1210 }
1211}
1212
1213static void __init pcibios_allocate_resources(int pass)
1214{
1215 struct pci_dev *dev = NULL;
1216 int idx, disabled;
1217 u16 command;
1218 struct resource *r;
1219
1220 for_each_pci_dev(dev) {
1221 pci_read_config_word(dev, PCI_COMMAND, &command);
1222 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1223 r = &dev->resource[idx];
1224 if (r->parent)
1225 continue;
1226 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1227 continue;
1228
1229
1230
1231 if (idx == PCI_ROM_RESOURCE )
1232 disabled = 1;
1233 if (r->flags & IORESOURCE_IO)
1234 disabled = !(command & PCI_COMMAND_IO);
1235 else
1236 disabled = !(command & PCI_COMMAND_MEMORY);
1237 if (pass == disabled)
1238 alloc_resource(dev, idx);
1239 }
1240 if (pass)
1241 continue;
1242 r = &dev->resource[PCI_ROM_RESOURCE];
1243 if (r->flags) {
1244
1245
1246
1247 u32 reg;
1248 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1249 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1250 pr_debug("PCI: Switching off ROM of %s\n",
1251 pci_name(dev));
1252 r->flags &= ~IORESOURCE_ROM_ENABLE;
1253 pci_write_config_dword(dev, dev->rom_base_reg,
1254 reg & ~PCI_ROM_ADDRESS_ENABLE);
1255 }
1256 }
1257 }
1258}
1259
1260static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1261{
1262 struct pci_controller *hose = pci_bus_to_host(bus);
1263 resource_size_t offset;
1264 struct resource *res, *pres;
1265 int i;
1266
1267 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1268
1269
1270 if (!(hose->io_resource.flags & IORESOURCE_IO))
1271 goto no_io;
1272 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1273 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1274 BUG_ON(res == NULL);
1275 res->name = "Legacy IO";
1276 res->flags = IORESOURCE_IO;
1277 res->start = offset;
1278 res->end = (offset + 0xfff) & 0xfffffffful;
1279 pr_debug("Candidate legacy IO: %pR\n", res);
1280 if (request_resource(&hose->io_resource, res)) {
1281 printk(KERN_DEBUG
1282 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1283 pci_domain_nr(bus), bus->number, res);
1284 kfree(res);
1285 }
1286
1287 no_io:
1288
1289 for (i = 0; i < 3; i++) {
1290 pres = &hose->mem_resources[i];
1291 offset = hose->mem_offset[i];
1292 if (!(pres->flags & IORESOURCE_MEM))
1293 continue;
1294 pr_debug("hose mem res: %pR\n", pres);
1295 if ((pres->start - offset) <= 0xa0000 &&
1296 (pres->end - offset) >= 0xbffff)
1297 break;
1298 }
1299 if (i >= 3)
1300 return;
1301 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1302 BUG_ON(res == NULL);
1303 res->name = "Legacy VGA memory";
1304 res->flags = IORESOURCE_MEM;
1305 res->start = 0xa0000 + offset;
1306 res->end = 0xbffff + offset;
1307 pr_debug("Candidate VGA memory: %pR\n", res);
1308 if (request_resource(pres, res)) {
1309 printk(KERN_DEBUG
1310 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1311 pci_domain_nr(bus), bus->number, res);
1312 kfree(res);
1313 }
1314}
1315
1316void __init pcibios_resource_survey(void)
1317{
1318 struct pci_bus *b;
1319
1320
1321 list_for_each_entry(b, &pci_root_buses, node)
1322 pcibios_allocate_bus_resources(b);
1323 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1324 pcibios_allocate_resources(0);
1325 pcibios_allocate_resources(1);
1326 }
1327
1328
1329
1330
1331
1332 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1333 list_for_each_entry(b, &pci_root_buses, node)
1334 pcibios_reserve_legacy_regions(b);
1335 }
1336
1337
1338
1339
1340 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1341 pr_debug("PCI: Assigning unassigned resources...\n");
1342 pci_assign_unassigned_resources();
1343 }
1344}
1345
1346
1347
1348
1349
1350
1351void pcibios_claim_one_bus(struct pci_bus *bus)
1352{
1353 struct pci_dev *dev;
1354 struct pci_bus *child_bus;
1355
1356 list_for_each_entry(dev, &bus->devices, bus_list) {
1357 int i;
1358
1359 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1360 struct resource *r = &dev->resource[i];
1361
1362 if (r->parent || !r->start || !r->flags)
1363 continue;
1364
1365 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1366 pci_name(dev), i, r);
1367
1368 if (pci_claim_resource(dev, i) == 0)
1369 continue;
1370
1371 pci_claim_bridge_resource(dev, i);
1372 }
1373 }
1374
1375 list_for_each_entry(child_bus, &bus->children, node)
1376 pcibios_claim_one_bus(child_bus);
1377}
1378EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1379
1380
1381
1382
1383
1384
1385
1386
1387void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1388{
1389 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1390 pci_domain_nr(bus), bus->number);
1391
1392
1393 pcibios_allocate_bus_resources(bus);
1394 pcibios_claim_one_bus(bus);
1395 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1396 if (bus->self)
1397 pci_assign_unassigned_bridge_resources(bus->self);
1398 else
1399 pci_assign_unassigned_bus_resources(bus);
1400 }
1401
1402
1403 pci_bus_add_devices(bus);
1404}
1405EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1406
1407int pcibios_enable_device(struct pci_dev *dev, int mask)
1408{
1409 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1410
1411 if (phb->controller_ops.enable_device_hook)
1412 if (!phb->controller_ops.enable_device_hook(dev))
1413 return -EINVAL;
1414
1415 return pci_enable_resources(dev, mask);
1416}
1417
1418void pcibios_disable_device(struct pci_dev *dev)
1419{
1420 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1421
1422 if (phb->controller_ops.disable_device)
1423 phb->controller_ops.disable_device(dev);
1424}
1425
1426resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1427{
1428 return (unsigned long) hose->io_base_virt - _IO_BASE;
1429}
1430
1431static void pcibios_setup_phb_resources(struct pci_controller *hose,
1432 struct list_head *resources)
1433{
1434 struct resource *res;
1435 resource_size_t offset;
1436 int i;
1437
1438
1439 res = &hose->io_resource;
1440
1441 if (!res->flags) {
1442 pr_debug("PCI: I/O resource not set for host"
1443 " bridge %pOF (domain %d)\n",
1444 hose->dn, hose->global_number);
1445 } else {
1446 offset = pcibios_io_space_offset(hose);
1447
1448 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1449 res, (unsigned long long)offset);
1450 pci_add_resource_offset(resources, res, offset);
1451 }
1452
1453
1454 for (i = 0; i < 3; ++i) {
1455 res = &hose->mem_resources[i];
1456 if (!res->flags)
1457 continue;
1458
1459 offset = hose->mem_offset[i];
1460 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1461 res, (unsigned long long)offset);
1462
1463 pci_add_resource_offset(resources, res, offset);
1464 }
1465}
1466
1467
1468
1469
1470
1471#define NULL_PCI_OP(rw, size, type) \
1472static int \
1473null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1474{ \
1475 return PCIBIOS_DEVICE_NOT_FOUND; \
1476}
1477
1478static int
1479null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1480 int len, u32 *val)
1481{
1482 return PCIBIOS_DEVICE_NOT_FOUND;
1483}
1484
1485static int
1486null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1487 int len, u32 val)
1488{
1489 return PCIBIOS_DEVICE_NOT_FOUND;
1490}
1491
1492static struct pci_ops null_pci_ops =
1493{
1494 .read = null_read_config,
1495 .write = null_write_config,
1496};
1497
1498
1499
1500
1501
1502static struct pci_bus *
1503fake_pci_bus(struct pci_controller *hose, int busnr)
1504{
1505 static struct pci_bus bus;
1506
1507 if (hose == NULL) {
1508 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1509 }
1510 bus.number = busnr;
1511 bus.sysdata = hose;
1512 bus.ops = hose? hose->ops: &null_pci_ops;
1513 return &bus;
1514}
1515
1516#define EARLY_PCI_OP(rw, size, type) \
1517int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1518 int devfn, int offset, type value) \
1519{ \
1520 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1521 devfn, offset, value); \
1522}
1523
1524EARLY_PCI_OP(read, byte, u8 *)
1525EARLY_PCI_OP(read, word, u16 *)
1526EARLY_PCI_OP(read, dword, u32 *)
1527EARLY_PCI_OP(write, byte, u8)
1528EARLY_PCI_OP(write, word, u16)
1529EARLY_PCI_OP(write, dword, u32)
1530
1531int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1532 int cap)
1533{
1534 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1535}
1536
1537struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1538{
1539 struct pci_controller *hose = bus->sysdata;
1540
1541 return of_node_get(hose->dn);
1542}
1543
1544
1545
1546
1547
1548void pcibios_scan_phb(struct pci_controller *hose)
1549{
1550 LIST_HEAD(resources);
1551 struct pci_bus *bus;
1552 struct device_node *node = hose->dn;
1553 int mode;
1554
1555 pr_debug("PCI: Scanning PHB %pOF\n", node);
1556
1557
1558 pcibios_setup_phb_io_space(hose);
1559
1560
1561 pcibios_setup_phb_resources(hose, &resources);
1562
1563 hose->busn.start = hose->first_busno;
1564 hose->busn.end = hose->last_busno;
1565 hose->busn.flags = IORESOURCE_BUS;
1566 pci_add_resource(&resources, &hose->busn);
1567
1568
1569 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1570 hose->ops, hose, &resources);
1571 if (bus == NULL) {
1572 pr_err("Failed to create bus for PCI domain %04x\n",
1573 hose->global_number);
1574 pci_free_resource_list(&resources);
1575 return;
1576 }
1577 hose->bus = bus;
1578
1579
1580 mode = PCI_PROBE_NORMAL;
1581 if (node && hose->controller_ops.probe_mode)
1582 mode = hose->controller_ops.probe_mode(bus);
1583 pr_debug(" probe mode: %d\n", mode);
1584 if (mode == PCI_PROBE_DEVTREE)
1585 of_scan_bus(node, bus);
1586
1587 if (mode == PCI_PROBE_NORMAL) {
1588 pci_bus_update_busn_res_end(bus, 255);
1589 hose->last_busno = pci_scan_child_bus(bus);
1590 pci_bus_update_busn_res_end(bus, hose->last_busno);
1591 }
1592
1593
1594
1595
1596 if (ppc_md.pcibios_fixup_phb)
1597 ppc_md.pcibios_fixup_phb(hose);
1598
1599
1600 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1601 struct pci_bus *child;
1602 list_for_each_entry(child, &bus->children, node)
1603 pcie_bus_configure_settings(child);
1604 }
1605}
1606EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1607
1608static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1609{
1610 int i, class = dev->class >> 8;
1611
1612 int prog_if = dev->class & 0xf;
1613
1614 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1615 class == PCI_CLASS_BRIDGE_OTHER) &&
1616 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1617 (prog_if == 0) &&
1618 (dev->bus->parent == NULL)) {
1619 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1620 dev->resource[i].start = 0;
1621 dev->resource[i].end = 0;
1622 dev->resource[i].flags = 0;
1623 }
1624 }
1625}
1626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1628