LXR linux/arch/riscv/include/asm/hwcap.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copied from arch/arm64/include/asm/hwcap.h
   4 *
   5 * Copyright (C) 2012 ARM Ltd.
   6 * Copyright (C) 2017 SiFive
   7 */
   8#ifndef _ASM_RISCV_HWCAP_H
   9#define _ASM_RISCV_HWCAP_H
  10
  11#include <linux/bits.h>
  12#include <uapi/asm/hwcap.h>
  13
  14#ifndef __ASSEMBLY__
  15/*
  16 * This yields a mask that user programs can use to figure out what
  17 * instruction set this cpu supports.
  18 */
  19#define ELF_HWCAP               (elf_hwcap)
  20
  21enum {
  22        CAP_HWCAP = 1,
  23};
  24
  25extern unsigned long elf_hwcap;
  26
  27#define RISCV_ISA_EXT_a         ('a' - 'a')
  28#define RISCV_ISA_EXT_c         ('c' - 'a')
  29#define RISCV_ISA_EXT_d         ('d' - 'a')
  30#define RISCV_ISA_EXT_f         ('f' - 'a')
  31#define RISCV_ISA_EXT_h         ('h' - 'a')
  32#define RISCV_ISA_EXT_i         ('i' - 'a')
  33#define RISCV_ISA_EXT_m         ('m' - 'a')
  34#define RISCV_ISA_EXT_s         ('s' - 'a')
  35#define RISCV_ISA_EXT_u         ('u' - 'a')
  36
  37#define RISCV_ISA_EXT_MAX       64
  38
  39unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
  40
  41#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
  42
  43bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
  44#define riscv_isa_extension_available(isa_bitmap, ext)  \
  45        __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
  46
  47#endif
  48
  49#endif /* _ASM_RISCV_HWCAP_H */
  50