1
2#include <asm/thread_info.h>
3#include <asm/trap_block.h>
4#include <asm/spitfire.h>
5#include <asm/ptrace.h>
6#include <asm/head.h>
7
8 .text
9 .align 8
10 .globl user_rtt_fill_fixup_common
11user_rtt_fill_fixup_common:
12 rdpr %cwp, %g1
13 add %g1, 1, %g1
14 wrpr %g1, 0x0, %cwp
15
16 rdpr %wstate, %g2
17 sll %g2, 3, %g2
18 wrpr %g2, 0x0, %wstate
19
20
21
22 sethi %hi(sparc64_kern_pri_context), %g2
23 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
24 mov PRIMARY_CONTEXT, %g1
25
26661: stxa %g2, [%g1] ASI_DMMU
27 .section .sun4v_1insn_patch, "ax"
28 .word 661b
29 stxa %g2, [%g1] ASI_MMU
30 .previous
31
32 sethi %hi(KERNBASE), %g1
33 flush %g1
34
35 mov %g4, %l4
36 mov %g5, %l5
37 brnz,pn %g3, 1f
38 mov %g3, %l3
39
40 or %g4, FAULT_CODE_WINFIXUP, %g4
41 stb %g4, [%g6 + TI_FAULT_CODE]
42 stx %g5, [%g6 + TI_FAULT_ADDR]
431:
44 mov %g6, %l1
45 wrpr %g0, 0x0, %tl
46
47661: nop
48 .section .sun4v_1insn_patch, "ax"
49 .word 661b
50 SET_GL(0)
51 .previous
52
53661: wrpr %g0, RTRAP_PSTATE, %pstate
54 .section .sun_m7_1insn_patch, "ax"
55 .word 661b
56
57 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
58 .previous
59
60 mov %l1, %g6
61 ldx [%g6 + TI_TASK], %g4
62 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
63
64 brnz,pn %l3, 1f
65 nop
66
67 call do_sparc64_fault
68 add %sp, PTREGS_OFF, %o0
69 ba,pt %xcc, rtrap
70 nop
71
721: cmp %g3, 2
73 bne,pn %xcc, 2f
74 nop
75
76 sethi %hi(tlb_type), %g1
77 lduw [%g1 + %lo(tlb_type)], %g1
78 cmp %g1, 3
79 bne,pt %icc, 1f
80 add %sp, PTREGS_OFF, %o0
81 mov %l4, %o2
82 call sun4v_do_mna
83 mov %l5, %o1
84 ba,a,pt %xcc, rtrap
851: mov %l4, %o1
86 mov %l5, %o2
87 call mem_address_unaligned
88 nop
89 ba,a,pt %xcc, rtrap
90
912: sethi %hi(tlb_type), %g1
92 mov %l4, %o1
93 lduw [%g1 + %lo(tlb_type)], %g1
94 mov %l5, %o2
95 cmp %g1, 3
96 bne,pt %icc, 1f
97 add %sp, PTREGS_OFF, %o0
98 call sun4v_data_access_exception
99 nop
100 ba,a,pt %xcc, rtrap
101 nop
102
1031: call spitfire_data_access_exception
104 nop
105 ba,a,pt %xcc, rtrap
106
