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5#ifndef _ASM_X86_FPU_H
6#define _ASM_X86_FPU_H
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11
12struct fregs_state {
13 u32 cwd;
14 u32 swd;
15 u32 twd;
16 u32 fip;
17 u32 fcs;
18 u32 foo;
19 u32 fos;
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21
22 u32 st_space[20];
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24
25 u32 status;
26};
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34struct fxregs_state {
35 u16 cwd;
36 u16 swd;
37 u16 twd;
38 u16 fop;
39 union {
40 struct {
41 u64 rip;
42 u64 rdp;
43 };
44 struct {
45 u32 fip;
46 u32 fcs;
47 u32 foo;
48 u32 fos;
49 };
50 };
51 u32 mxcsr;
52 u32 mxcsr_mask;
53
54
55 u32 st_space[32];
56
57
58 u32 xmm_space[64];
59
60 u32 padding[12];
61
62 union {
63 u32 padding1[12];
64 u32 sw_reserved[12];
65 };
66
67} __attribute__((aligned(16)));
68
69
70#define MXCSR_DEFAULT 0x1f80
71
72
73#define MXCSR_AND_FLAGS_SIZE sizeof(u64)
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78
79struct swregs_state {
80 u32 cwd;
81 u32 swd;
82 u32 twd;
83 u32 fip;
84 u32 fcs;
85 u32 foo;
86 u32 fos;
87
88 u32 st_space[20];
89 u8 ftop;
90 u8 changed;
91 u8 lookahead;
92 u8 no_update;
93 u8 rm;
94 u8 alimit;
95 struct math_emu_info *info;
96 u32 entry_eip;
97};
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101
102enum xfeature {
103 XFEATURE_FP,
104 XFEATURE_SSE,
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109 XFEATURE_YMM,
110 XFEATURE_BNDREGS,
111 XFEATURE_BNDCSR,
112 XFEATURE_OPMASK,
113 XFEATURE_ZMM_Hi256,
114 XFEATURE_Hi16_ZMM,
115 XFEATURE_PT_UNIMPLEMENTED_SO_FAR,
116 XFEATURE_PKRU,
117 XFEATURE_RSRVD_COMP_10,
118 XFEATURE_RSRVD_COMP_11,
119 XFEATURE_RSRVD_COMP_12,
120 XFEATURE_RSRVD_COMP_13,
121 XFEATURE_RSRVD_COMP_14,
122 XFEATURE_LBR,
123
124 XFEATURE_MAX,
125};
126
127#define XFEATURE_MASK_FP (1 << XFEATURE_FP)
128#define XFEATURE_MASK_SSE (1 << XFEATURE_SSE)
129#define XFEATURE_MASK_YMM (1 << XFEATURE_YMM)
130#define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS)
131#define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR)
132#define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK)
133#define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256)
134#define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
135#define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR)
136#define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
137#define XFEATURE_MASK_LBR (1 << XFEATURE_LBR)
138
139#define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
140#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \
141 | XFEATURE_MASK_ZMM_Hi256 \
142 | XFEATURE_MASK_Hi16_ZMM)
143
144#define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
145
146struct reg_128_bit {
147 u8 regbytes[128/8];
148};
149struct reg_256_bit {
150 u8 regbytes[256/8];
151};
152struct reg_512_bit {
153 u8 regbytes[512/8];
154};
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166struct ymmh_struct {
167 struct reg_128_bit hi_ymm[16];
168} __packed;
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172struct mpx_bndreg {
173 u64 lower_bound;
174 u64 upper_bound;
175} __packed;
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179struct mpx_bndreg_state {
180 struct mpx_bndreg bndreg[4];
181} __packed;
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188struct mpx_bndcsr {
189 u64 bndcfgu;
190 u64 bndstatus;
191} __packed;
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195
196struct mpx_bndcsr_state {
197 union {
198 struct mpx_bndcsr bndcsr;
199 u8 pad_to_64_bytes[64];
200 };
201} __packed;
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209struct avx_512_opmask_state {
210 u64 opmask_reg[8];
211} __packed;
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218struct avx_512_zmm_uppers_state {
219 struct reg_256_bit zmm_upper[16];
220} __packed;
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226struct avx_512_hi16_state {
227 struct reg_512_bit hi16_zmm[16];
228} __packed;
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234struct pkru_state {
235 u32 pkru;
236 u32 pad;
237} __packed;
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243
244struct lbr_entry {
245 u64 from;
246 u64 to;
247 u64 info;
248};
249
250struct arch_lbr_state {
251 u64 lbr_ctl;
252 u64 lbr_depth;
253 u64 ler_from;
254 u64 ler_to;
255 u64 ler_info;
256 struct lbr_entry entries[];
257} __packed;
258
259struct xstate_header {
260 u64 xfeatures;
261 u64 xcomp_bv;
262 u64 reserved[6];
263} __attribute__((packed));
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269#define XCOMP_BV_COMPACTED_FORMAT ((u64)1 << 63)
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280struct xregs_state {
281 struct fxregs_state i387;
282 struct xstate_header header;
283 u8 extended_state_area[0];
284} __attribute__ ((packed, aligned (64)));
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295union fpregs_state {
296 struct fregs_state fsave;
297 struct fxregs_state fxsave;
298 struct swregs_state soft;
299 struct xregs_state xsave;
300 u8 __padding[PAGE_SIZE];
301};
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308struct fpu {
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321 unsigned int last_cpu;
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328 unsigned long avx512_timestamp;
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339 union fpregs_state state;
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343
344};
345
346#endif
347