1
2#ifndef ARCH_X86_KVM_X86_H
3#define ARCH_X86_KVM_X86_H
4
5#include <linux/kvm_host.h>
6#include <asm/pvclock.h>
7#include "kvm_cache_regs.h"
8#include "kvm_emulate.h"
9
10#define KVM_DEFAULT_PLE_GAP 128
11#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
12#define KVM_DEFAULT_PLE_WINDOW_GROW 2
13#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
14#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
15#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
16#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
17
18static inline unsigned int __grow_ple_window(unsigned int val,
19 unsigned int base, unsigned int modifier, unsigned int max)
20{
21 u64 ret = val;
22
23 if (modifier < 1)
24 return base;
25
26 if (modifier < base)
27 ret *= modifier;
28 else
29 ret += modifier;
30
31 return min(ret, (u64)max);
32}
33
34static inline unsigned int __shrink_ple_window(unsigned int val,
35 unsigned int base, unsigned int modifier, unsigned int min)
36{
37 if (modifier < 1)
38 return base;
39
40 if (modifier < base)
41 val /= modifier;
42 else
43 val -= modifier;
44
45 return max(val, min);
46}
47
48#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
49
50static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
51{
52 vcpu->arch.exception.pending = false;
53 vcpu->arch.exception.injected = false;
54}
55
56static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
57 bool soft)
58{
59 vcpu->arch.interrupt.injected = true;
60 vcpu->arch.interrupt.soft = soft;
61 vcpu->arch.interrupt.nr = vector;
62}
63
64static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
65{
66 vcpu->arch.interrupt.injected = false;
67}
68
69static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
70{
71 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
72 vcpu->arch.nmi_injected;
73}
74
75static inline bool kvm_exception_is_soft(unsigned int nr)
76{
77 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
78}
79
80static inline bool is_protmode(struct kvm_vcpu *vcpu)
81{
82 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
83}
84
85static inline int is_long_mode(struct kvm_vcpu *vcpu)
86{
87#ifdef CONFIG_X86_64
88 return vcpu->arch.efer & EFER_LMA;
89#else
90 return 0;
91#endif
92}
93
94static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
95{
96 int cs_db, cs_l;
97
98 if (!is_long_mode(vcpu))
99 return false;
100 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
101 return cs_l;
102}
103
104static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
105{
106#ifdef CONFIG_X86_64
107 return (vcpu->arch.efer & EFER_LMA) &&
108 kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
109#else
110 return 0;
111#endif
112}
113
114static inline bool x86_exception_has_error_code(unsigned int vector)
115{
116 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
117 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
118 BIT(PF_VECTOR) | BIT(AC_VECTOR);
119
120 return (1U << vector) & exception_has_error_code;
121}
122
123static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
124{
125 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
126}
127
128static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
129{
130 ++vcpu->stat.tlb_flush;
131 kvm_x86_ops.tlb_flush_current(vcpu);
132}
133
134static inline int is_pae(struct kvm_vcpu *vcpu)
135{
136 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
137}
138
139static inline int is_pse(struct kvm_vcpu *vcpu)
140{
141 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
142}
143
144static inline int is_paging(struct kvm_vcpu *vcpu)
145{
146 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
147}
148
149static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
150{
151 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
152}
153
154static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
155{
156 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
157}
158
159static inline u64 get_canonical(u64 la, u8 vaddr_bits)
160{
161 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
162}
163
164static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
165{
166 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
167}
168
169static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
170 gva_t gva, gfn_t gfn, unsigned access)
171{
172 u64 gen = kvm_memslots(vcpu->kvm)->generation;
173
174 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
175 return;
176
177
178
179
180
181 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
182 vcpu->arch.mmio_access = access;
183 vcpu->arch.mmio_gfn = gfn;
184 vcpu->arch.mmio_gen = gen;
185}
186
187static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
188{
189 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
190}
191
192
193
194
195
196#define MMIO_GVA_ANY (~(gva_t)0)
197
198static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
199{
200 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
201 return;
202
203 vcpu->arch.mmio_gva = 0;
204}
205
206static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
207{
208 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
209 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
210 return true;
211
212 return false;
213}
214
215static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
216{
217 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
218 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
219 return true;
220
221 return false;
222}
223
224static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, int reg)
225{
226 unsigned long val = kvm_register_read(vcpu, reg);
227
228 return is_64_bit_mode(vcpu) ? val : (u32)val;
229}
230
231static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
232 int reg, unsigned long val)
233{
234 if (!is_64_bit_mode(vcpu))
235 val = (u32)val;
236 return kvm_register_write(vcpu, reg, val);
237}
238
239static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
240{
241 return !(kvm->arch.disabled_quirks & quirk);
242}
243
244static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
245{
246 return is_smm(vcpu) || kvm_x86_ops.apic_init_signal_blocked(vcpu);
247}
248
249void kvm_set_pending_timer(struct kvm_vcpu *vcpu);
250void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
251
252void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
253u64 get_kvmclock_ns(struct kvm *kvm);
254
255int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
256 gva_t addr, void *val, unsigned int bytes,
257 struct x86_exception *exception);
258
259int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
260 gva_t addr, void *val, unsigned int bytes,
261 struct x86_exception *exception);
262
263int handle_ud(struct kvm_vcpu *vcpu);
264
265void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
266
267void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
268u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
269bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
270int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
271int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
272bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
273 int page_num);
274bool kvm_vector_hashing_enabled(void);
275void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
276int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
277 int emulation_type, void *insn, int insn_len);
278fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
279
280extern u64 host_xcr0;
281extern u64 supported_xcr0;
282extern u64 supported_xss;
283
284static inline bool kvm_mpx_supported(void)
285{
286 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
287 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
288}
289
290extern unsigned int min_timer_period_us;
291
292extern bool enable_vmware_backdoor;
293
294extern int pi_inject_timer;
295
296extern struct static_key kvm_no_apic_vcpu;
297
298static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
299{
300 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
301 vcpu->arch.virtual_tsc_shift);
302}
303
304
305
306
307
308
309#define do_shl32_div32(n, base) \
310 ({ \
311 u32 __quot, __rem; \
312 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
313 : "rm" (base), "0" (0), "1" ((u32) n)); \
314 n = __quot; \
315 __rem; \
316 })
317
318static inline bool kvm_mwait_in_guest(struct kvm *kvm)
319{
320 return kvm->arch.mwait_in_guest;
321}
322
323static inline bool kvm_hlt_in_guest(struct kvm *kvm)
324{
325 return kvm->arch.hlt_in_guest;
326}
327
328static inline bool kvm_pause_in_guest(struct kvm *kvm)
329{
330 return kvm->arch.pause_in_guest;
331}
332
333static inline bool kvm_cstate_in_guest(struct kvm *kvm)
334{
335 return kvm->arch.cstate_in_guest;
336}
337
338DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
339
340static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
341{
342 __this_cpu_write(current_vcpu, vcpu);
343}
344
345static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
346{
347 __this_cpu_write(current_vcpu, NULL);
348}
349
350
351static inline bool kvm_pat_valid(u64 data)
352{
353 if (data & 0xF8F8F8F8F8F8F8F8ull)
354 return false;
355
356 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
357}
358
359static inline bool kvm_dr7_valid(u64 data)
360{
361
362 return !(data >> 32);
363}
364static inline bool kvm_dr6_valid(u64 data)
365{
366
367 return !(data >> 32);
368}
369
370void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
371void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
372int kvm_spec_ctrl_test_value(u64 value);
373int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
374bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu);
375
376#define KVM_MSR_RET_INVALID 2
377
378#define __cr4_reserved_bits(__cpu_has, __c) \
379({ \
380 u64 __reserved_bits = CR4_RESERVED_BITS; \
381 \
382 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
383 __reserved_bits |= X86_CR4_OSXSAVE; \
384 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
385 __reserved_bits |= X86_CR4_SMEP; \
386 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
387 __reserved_bits |= X86_CR4_SMAP; \
388 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
389 __reserved_bits |= X86_CR4_FSGSBASE; \
390 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
391 __reserved_bits |= X86_CR4_PKE; \
392 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
393 __reserved_bits |= X86_CR4_LA57; \
394 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
395 __reserved_bits |= X86_CR4_UMIP; \
396 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
397 __reserved_bits |= X86_CR4_VMXE; \
398 __reserved_bits; \
399})
400
401#endif
402
