1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/gfp.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/device.h>
26#include <scsi/scsi.h>
27#include <scsi/scsi_host.h>
28#include <scsi/scsi_cmnd.h>
29#include <linux/libata.h>
30#include "sata_promise.h"
31
32#define DRV_NAME "sata_promise"
33#define DRV_VERSION "2.12"
34
35enum {
36 PDC_MAX_PORTS = 4,
37 PDC_MMIO_BAR = 3,
38 PDC_MAX_PRD = LIBATA_MAX_PRD - 1,
39
40
41 PDC_INT_SEQMASK = 0x40,
42 PDC_FLASH_CTL = 0x44,
43 PDC_PCI_CTL = 0x48,
44 PDC_SATA_PLUG_CSR = 0x6C,
45 PDC2_SATA_PLUG_CSR = 0x60,
46 PDC_TBG_MODE = 0x41C,
47 PDC_SLEW_CTL = 0x470,
48
49
50 PDC_FEATURE = 0x04,
51 PDC_SECTOR_COUNT = 0x08,
52 PDC_SECTOR_NUMBER = 0x0C,
53 PDC_CYLINDER_LOW = 0x10,
54 PDC_CYLINDER_HIGH = 0x14,
55 PDC_DEVICE = 0x18,
56 PDC_COMMAND = 0x1C,
57 PDC_ALTSTATUS = 0x38,
58 PDC_PKT_SUBMIT = 0x40,
59 PDC_GLOBAL_CTL = 0x48,
60 PDC_CTLSTAT = 0x60,
61
62
63 PDC_SATA_ERROR = 0x04,
64 PDC_PHYMODE4 = 0x14,
65 PDC_LINK_LAYER_ERRORS = 0x6C,
66 PDC_FPDMA_CTLSTAT = 0xD8,
67 PDC_INTERNAL_DEBUG_1 = 0xF8,
68 PDC_INTERNAL_DEBUG_2 = 0xFC,
69
70
71 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
72 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
73 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
74
75
76 PDC_PH_ERR = (1 << 8),
77 PDC_SH_ERR = (1 << 9),
78 PDC_DH_ERR = (1 << 10),
79 PDC2_HTO_ERR = (1 << 12),
80 PDC2_ATA_HBA_ERR = (1 << 13),
81 PDC2_ATA_DMA_CNT_ERR = (1 << 14),
82 PDC_OVERRUN_ERR = (1 << 19),
83 PDC_UNDERRUN_ERR = (1 << 20),
84 PDC_DRIVE_ERR = (1 << 21),
85 PDC_PCI_SYS_ERR = (1 << 22),
86 PDC1_PCI_PARITY_ERR = (1 << 23),
87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
89 PDC2_ATA_DMA_CNT_ERR,
90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
93 PDC1_ERR_MASK | PDC2_ERR_MASK,
94
95 board_2037x = 0,
96 board_2037x_pata = 1,
97 board_20319 = 2,
98 board_20619 = 3,
99 board_2057x = 4,
100 board_2057x_pata = 5,
101 board_40518 = 6,
102
103 PDC_HAS_PATA = (1 << 1),
104
105
106 PDC_SEQCNTRL_INT_MASK = (1 << 5),
107
108
109 PDC_FEATURE_ATAPI_PIO = 0x00,
110 PDC_FEATURE_ATAPI_DMA = 0x01,
111
112
113 PDC_DEVICE_SATA = 0xE0,
114
115
116 PDC_DMA_ENABLE = (1 << 7),
117 PDC_IRQ_DISABLE = (1 << 10),
118 PDC_RESET = (1 << 11),
119
120 PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING,
121
122
123 PDC_FLAG_GEN_II = (1 << 24),
124 PDC_FLAG_SATA_PATA = (1 << 25),
125 PDC_FLAG_4_PORTS = (1 << 26),
126};
127
128struct pdc_port_priv {
129 u8 *pkt;
130 dma_addr_t pkt_dma;
131};
132
133struct pdc_host_priv {
134 spinlock_t hard_reset_lock;
135};
136
137static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
138static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
139static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
140static int pdc_common_port_start(struct ata_port *ap);
141static int pdc_sata_port_start(struct ata_port *ap);
142static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc);
143static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
144static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
145static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
146static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
147static void pdc_irq_clear(struct ata_port *ap);
148static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
149static void pdc_freeze(struct ata_port *ap);
150static void pdc_sata_freeze(struct ata_port *ap);
151static void pdc_thaw(struct ata_port *ap);
152static void pdc_sata_thaw(struct ata_port *ap);
153static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
154 unsigned long deadline);
155static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
156 unsigned long deadline);
157static void pdc_error_handler(struct ata_port *ap);
158static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
159static int pdc_pata_cable_detect(struct ata_port *ap);
160
161static struct scsi_host_template pdc_ata_sht = {
162 ATA_BASE_SHT(DRV_NAME),
163 .sg_tablesize = PDC_MAX_PRD,
164 .dma_boundary = ATA_DMA_BOUNDARY,
165};
166
167static const struct ata_port_operations pdc_common_ops = {
168 .inherits = &ata_sff_port_ops,
169
170 .sff_tf_load = pdc_tf_load_mmio,
171 .sff_exec_command = pdc_exec_command_mmio,
172 .check_atapi_dma = pdc_check_atapi_dma,
173 .qc_prep = pdc_qc_prep,
174 .qc_issue = pdc_qc_issue,
175
176 .sff_irq_clear = pdc_irq_clear,
177 .lost_interrupt = ATA_OP_NULL,
178
179 .post_internal_cmd = pdc_post_internal_cmd,
180 .error_handler = pdc_error_handler,
181};
182
183static struct ata_port_operations pdc_sata_ops = {
184 .inherits = &pdc_common_ops,
185 .cable_detect = ata_cable_sata,
186 .freeze = pdc_sata_freeze,
187 .thaw = pdc_sata_thaw,
188 .scr_read = pdc_sata_scr_read,
189 .scr_write = pdc_sata_scr_write,
190 .port_start = pdc_sata_port_start,
191 .hardreset = pdc_sata_hardreset,
192};
193
194
195
196static struct ata_port_operations pdc_old_sata_ops = {
197 .inherits = &pdc_sata_ops,
198 .freeze = pdc_freeze,
199 .thaw = pdc_thaw,
200 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
201};
202
203static struct ata_port_operations pdc_pata_ops = {
204 .inherits = &pdc_common_ops,
205 .cable_detect = pdc_pata_cable_detect,
206 .freeze = pdc_freeze,
207 .thaw = pdc_thaw,
208 .port_start = pdc_common_port_start,
209 .softreset = pdc_pata_softreset,
210};
211
212static const struct ata_port_info pdc_port_info[] = {
213 [board_2037x] =
214 {
215 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
216 PDC_FLAG_SATA_PATA,
217 .pio_mask = ATA_PIO4,
218 .mwdma_mask = ATA_MWDMA2,
219 .udma_mask = ATA_UDMA6,
220 .port_ops = &pdc_old_sata_ops,
221 },
222
223 [board_2037x_pata] =
224 {
225 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
226 .pio_mask = ATA_PIO4,
227 .mwdma_mask = ATA_MWDMA2,
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &pdc_pata_ops,
230 },
231
232 [board_20319] =
233 {
234 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
235 PDC_FLAG_4_PORTS,
236 .pio_mask = ATA_PIO4,
237 .mwdma_mask = ATA_MWDMA2,
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &pdc_old_sata_ops,
240 },
241
242 [board_20619] =
243 {
244 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
245 PDC_FLAG_4_PORTS,
246 .pio_mask = ATA_PIO4,
247 .mwdma_mask = ATA_MWDMA2,
248 .udma_mask = ATA_UDMA6,
249 .port_ops = &pdc_pata_ops,
250 },
251
252 [board_2057x] =
253 {
254 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
255 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
256 .pio_mask = ATA_PIO4,
257 .mwdma_mask = ATA_MWDMA2,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &pdc_sata_ops,
260 },
261
262 [board_2057x_pata] =
263 {
264 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
265 PDC_FLAG_GEN_II,
266 .pio_mask = ATA_PIO4,
267 .mwdma_mask = ATA_MWDMA2,
268 .udma_mask = ATA_UDMA6,
269 .port_ops = &pdc_pata_ops,
270 },
271
272 [board_40518] =
273 {
274 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
275 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
276 .pio_mask = ATA_PIO4,
277 .mwdma_mask = ATA_MWDMA2,
278 .udma_mask = ATA_UDMA6,
279 .port_ops = &pdc_sata_ops,
280 },
281};
282
283static const struct pci_device_id pdc_ata_pci_tbl[] = {
284 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
285 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
286 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
289 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
290 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
294
295 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
296 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
297 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
298 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
299 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
300 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
301
302 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
303
304 { }
305};
306
307static struct pci_driver pdc_ata_pci_driver = {
308 .name = DRV_NAME,
309 .id_table = pdc_ata_pci_tbl,
310 .probe = pdc_ata_init_one,
311 .remove = ata_pci_remove_one,
312};
313
314static int pdc_common_port_start(struct ata_port *ap)
315{
316 struct device *dev = ap->host->dev;
317 struct pdc_port_priv *pp;
318 int rc;
319
320
321 rc = ata_bmdma_port_start(ap);
322 if (rc)
323 return rc;
324
325 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
326 if (!pp)
327 return -ENOMEM;
328
329 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
330 if (!pp->pkt)
331 return -ENOMEM;
332
333 ap->private_data = pp;
334
335 return 0;
336}
337
338static int pdc_sata_port_start(struct ata_port *ap)
339{
340 int rc;
341
342 rc = pdc_common_port_start(ap);
343 if (rc)
344 return rc;
345
346
347 if (ap->flags & PDC_FLAG_GEN_II) {
348 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
349 unsigned int tmp;
350
351 tmp = readl(sata_mmio + PDC_PHYMODE4);
352 tmp = (tmp & ~3) | 1;
353 writel(tmp, sata_mmio + PDC_PHYMODE4);
354 }
355
356 return 0;
357}
358
359static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
360{
361 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
362 u32 tmp;
363
364 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
365 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
366 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
367
368
369
370 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
371 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1);
372}
373
374static void pdc_fpdma_reset(struct ata_port *ap)
375{
376 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
377 u8 tmp;
378
379 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
380 tmp &= 0x7F;
381 tmp |= PDC_FPDMA_CTLSTAT_RESET;
382 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
383 readl(sata_mmio + PDC_FPDMA_CTLSTAT);
384 udelay(100);
385 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
386 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
387 readl(sata_mmio + PDC_FPDMA_CTLSTAT);
388
389 pdc_fpdma_clear_interrupt_flag(ap);
390}
391
392static void pdc_not_at_command_packet_phase(struct ata_port *ap)
393{
394 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
395 unsigned int i;
396 u32 tmp;
397
398
399 for (i = 0; i < 100; ++i) {
400 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
401 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
402 if ((tmp & 0xF) != 1)
403 break;
404 udelay(100);
405 }
406}
407
408static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
409{
410 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
411
412 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
413 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
414}
415
416static void pdc_reset_port(struct ata_port *ap)
417{
418 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
419 unsigned int i;
420 u32 tmp;
421
422 if (ap->flags & PDC_FLAG_GEN_II)
423 pdc_not_at_command_packet_phase(ap);
424
425 tmp = readl(ata_ctlstat_mmio);
426 tmp |= PDC_RESET;
427 writel(tmp, ata_ctlstat_mmio);
428
429 for (i = 11; i > 0; i--) {
430 tmp = readl(ata_ctlstat_mmio);
431 if (tmp & PDC_RESET)
432 break;
433
434 udelay(100);
435
436 tmp |= PDC_RESET;
437 writel(tmp, ata_ctlstat_mmio);
438 }
439
440 tmp &= ~PDC_RESET;
441 writel(tmp, ata_ctlstat_mmio);
442 readl(ata_ctlstat_mmio);
443
444 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
445 pdc_fpdma_reset(ap);
446 pdc_clear_internal_debug_record_error_register(ap);
447 }
448}
449
450static int pdc_pata_cable_detect(struct ata_port *ap)
451{
452 u8 tmp;
453 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
454
455 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
456 if (tmp & 0x01)
457 return ATA_CBL_PATA40;
458 return ATA_CBL_PATA80;
459}
460
461static int pdc_sata_scr_read(struct ata_link *link,
462 unsigned int sc_reg, u32 *val)
463{
464 if (sc_reg > SCR_CONTROL)
465 return -EINVAL;
466 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
467 return 0;
468}
469
470static int pdc_sata_scr_write(struct ata_link *link,
471 unsigned int sc_reg, u32 val)
472{
473 if (sc_reg > SCR_CONTROL)
474 return -EINVAL;
475 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
476 return 0;
477}
478
479static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
480{
481 struct ata_port *ap = qc->ap;
482 dma_addr_t sg_table = ap->bmdma_prd_dma;
483 unsigned int cdb_len = qc->dev->cdb_len;
484 u8 *cdb = qc->cdb;
485 struct pdc_port_priv *pp = ap->private_data;
486 u8 *buf = pp->pkt;
487 __le32 *buf32 = (__le32 *) buf;
488 unsigned int dev_sel, feature;
489
490
491
492
493 switch (qc->tf.protocol) {
494 case ATAPI_PROT_DMA:
495 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
496 buf32[0] = cpu_to_le32(PDC_PKT_READ);
497 else
498 buf32[0] = 0;
499 break;
500 case ATAPI_PROT_NODATA:
501 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
502 break;
503 default:
504 BUG();
505 break;
506 }
507 buf32[1] = cpu_to_le32(sg_table);
508 buf32[2] = 0;
509
510
511 if (sata_scr_valid(&ap->link))
512 dev_sel = PDC_DEVICE_SATA;
513 else
514 dev_sel = qc->tf.device;
515
516 buf[12] = (1 << 5) | ATA_REG_DEVICE;
517 buf[13] = dev_sel;
518 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
519 buf[15] = dev_sel;
520
521 buf[16] = (1 << 5) | ATA_REG_NSECT;
522 buf[17] = qc->tf.nsect;
523 buf[18] = (1 << 5) | ATA_REG_LBAL;
524 buf[19] = qc->tf.lbal;
525
526
527 if (qc->tf.protocol != ATAPI_PROT_DMA)
528 feature = PDC_FEATURE_ATAPI_PIO;
529 else
530 feature = PDC_FEATURE_ATAPI_DMA;
531
532 buf[20] = (1 << 5) | ATA_REG_FEATURE;
533 buf[21] = feature;
534 buf[22] = (1 << 5) | ATA_REG_BYTEL;
535 buf[23] = qc->tf.lbam;
536 buf[24] = (1 << 5) | ATA_REG_BYTEH;
537 buf[25] = qc->tf.lbah;
538
539
540 buf[26] = (1 << 5) | ATA_REG_CMD;
541 buf[27] = qc->tf.command;
542
543
544 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
545 buf[29] = dev_sel;
546
547
548 BUG_ON(cdb_len & ~0x1E);
549
550
551 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
552 memcpy(buf+31, cdb, cdb_len);
553}
554
555
556
557
558
559
560
561
562
563
564
565
566
567static void pdc_fill_sg(struct ata_queued_cmd *qc)
568{
569 struct ata_port *ap = qc->ap;
570 struct ata_bmdma_prd *prd = ap->bmdma_prd;
571 struct scatterlist *sg;
572 const u32 SG_COUNT_ASIC_BUG = 41*4;
573 unsigned int si, idx;
574 u32 len;
575
576 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
577 return;
578
579 idx = 0;
580 for_each_sg(qc->sg, sg, qc->n_elem, si) {
581 u32 addr, offset;
582 u32 sg_len;
583
584
585
586
587
588 addr = (u32) sg_dma_address(sg);
589 sg_len = sg_dma_len(sg);
590
591 while (sg_len) {
592 offset = addr & 0xffff;
593 len = sg_len;
594 if ((offset + sg_len) > 0x10000)
595 len = 0x10000 - offset;
596
597 prd[idx].addr = cpu_to_le32(addr);
598 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
599 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
600
601 idx++;
602 sg_len -= len;
603 addr += len;
604 }
605 }
606
607 len = le32_to_cpu(prd[idx - 1].flags_len);
608
609 if (len > SG_COUNT_ASIC_BUG) {
610 u32 addr;
611
612 VPRINTK("Splitting last PRD.\n");
613
614 addr = le32_to_cpu(prd[idx - 1].addr);
615 prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
616 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
617
618 addr = addr + len - SG_COUNT_ASIC_BUG;
619 len = SG_COUNT_ASIC_BUG;
620 prd[idx].addr = cpu_to_le32(addr);
621 prd[idx].flags_len = cpu_to_le32(len);
622 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
623
624 idx++;
625 }
626
627 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
628}
629
630static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc)
631{
632 struct pdc_port_priv *pp = qc->ap->private_data;
633 unsigned int i;
634
635 VPRINTK("ENTER\n");
636
637 switch (qc->tf.protocol) {
638 case ATA_PROT_DMA:
639 pdc_fill_sg(qc);
640 fallthrough;
641 case ATA_PROT_NODATA:
642 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
643 qc->dev->devno, pp->pkt);
644 if (qc->tf.flags & ATA_TFLAG_LBA48)
645 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
646 else
647 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
648 pdc_pkt_footer(&qc->tf, pp->pkt, i);
649 break;
650 case ATAPI_PROT_PIO:
651 pdc_fill_sg(qc);
652 break;
653 case ATAPI_PROT_DMA:
654 pdc_fill_sg(qc);
655 fallthrough;
656 case ATAPI_PROT_NODATA:
657 pdc_atapi_pkt(qc);
658 break;
659 default:
660 break;
661 }
662
663 return AC_ERR_OK;
664}
665
666static int pdc_is_sataii_tx4(unsigned long flags)
667{
668 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
669 return (flags & mask) == mask;
670}
671
672static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
673 int is_sataii_tx4)
674{
675 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
676 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
677}
678
679static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
680{
681 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
682}
683
684static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
685{
686 const struct ata_host *host = ap->host;
687 unsigned int nr_ports = pdc_sata_nr_ports(ap);
688 unsigned int i;
689
690 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
691 ;
692 BUG_ON(i >= nr_ports);
693 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
694}
695
696static void pdc_freeze(struct ata_port *ap)
697{
698 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
699 u32 tmp;
700
701 tmp = readl(ata_mmio + PDC_CTLSTAT);
702 tmp |= PDC_IRQ_DISABLE;
703 tmp &= ~PDC_DMA_ENABLE;
704 writel(tmp, ata_mmio + PDC_CTLSTAT);
705 readl(ata_mmio + PDC_CTLSTAT);
706}
707
708static void pdc_sata_freeze(struct ata_port *ap)
709{
710 struct ata_host *host = ap->host;
711 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
712 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
713 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
714 u32 hotplug_status;
715
716
717
718
719
720
721
722
723 hotplug_status = readl(host_mmio + hotplug_offset);
724 hotplug_status |= 0x11 << (ata_no + 16);
725 writel(hotplug_status, host_mmio + hotplug_offset);
726 readl(host_mmio + hotplug_offset);
727
728 pdc_freeze(ap);
729}
730
731static void pdc_thaw(struct ata_port *ap)
732{
733 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
734 u32 tmp;
735
736
737 readl(ata_mmio + PDC_COMMAND);
738
739
740 tmp = readl(ata_mmio + PDC_CTLSTAT);
741 tmp &= ~PDC_IRQ_DISABLE;
742 writel(tmp, ata_mmio + PDC_CTLSTAT);
743 readl(ata_mmio + PDC_CTLSTAT);
744}
745
746static void pdc_sata_thaw(struct ata_port *ap)
747{
748 struct ata_host *host = ap->host;
749 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
750 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
751 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
752 u32 hotplug_status;
753
754 pdc_thaw(ap);
755
756
757
758
759 hotplug_status = readl(host_mmio + hotplug_offset);
760 hotplug_status |= 0x11 << ata_no;
761 hotplug_status &= ~(0x11 << (ata_no + 16));
762 writel(hotplug_status, host_mmio + hotplug_offset);
763 readl(host_mmio + hotplug_offset);
764}
765
766static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
767 unsigned long deadline)
768{
769 pdc_reset_port(link->ap);
770 return ata_sff_softreset(link, class, deadline);
771}
772
773static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
774{
775 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
776 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
777
778
779 return (ata_mmio - host_mmio - 0x200) / 0x80;
780}
781
782static void pdc_hard_reset_port(struct ata_port *ap)
783{
784 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
785 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
786 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
787 struct pdc_host_priv *hpriv = ap->host->private_data;
788 u8 tmp;
789
790 spin_lock(&hpriv->hard_reset_lock);
791
792 tmp = readb(pcictl_b1_mmio);
793 tmp &= ~(0x10 << ata_no);
794 writeb(tmp, pcictl_b1_mmio);
795 readb(pcictl_b1_mmio);
796 udelay(100);
797 tmp |= (0x10 << ata_no);
798 writeb(tmp, pcictl_b1_mmio);
799 readb(pcictl_b1_mmio);
800
801 spin_unlock(&hpriv->hard_reset_lock);
802}
803
804static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
805 unsigned long deadline)
806{
807 if (link->ap->flags & PDC_FLAG_GEN_II)
808 pdc_not_at_command_packet_phase(link->ap);
809
810 pdc_hard_reset_port(link->ap);
811 pdc_reset_port(link->ap);
812
813
814
815
816
817 return sata_std_hardreset(link, class, deadline);
818}
819
820static void pdc_error_handler(struct ata_port *ap)
821{
822 if (!(ap->pflags & ATA_PFLAG_FROZEN))
823 pdc_reset_port(ap);
824
825 ata_sff_error_handler(ap);
826}
827
828static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
829{
830 struct ata_port *ap = qc->ap;
831
832
833 if (qc->flags & ATA_QCFLAG_FAILED)
834 pdc_reset_port(ap);
835}
836
837static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
838 u32 port_status, u32 err_mask)
839{
840 struct ata_eh_info *ehi = &ap->link.eh_info;
841 unsigned int ac_err_mask = 0;
842
843 ata_ehi_clear_desc(ehi);
844 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
845 port_status &= err_mask;
846
847 if (port_status & PDC_DRIVE_ERR)
848 ac_err_mask |= AC_ERR_DEV;
849 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
850 ac_err_mask |= AC_ERR_OTHER;
851 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
852 ac_err_mask |= AC_ERR_ATA_BUS;
853 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
854 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
855 ac_err_mask |= AC_ERR_HOST_BUS;
856
857 if (sata_scr_valid(&ap->link)) {
858 u32 serror;
859
860 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
861 ehi->serror |= serror;
862 }
863
864 qc->err_mask |= ac_err_mask;
865
866 pdc_reset_port(ap);
867
868 ata_port_abort(ap);
869}
870
871static unsigned int pdc_host_intr(struct ata_port *ap,
872 struct ata_queued_cmd *qc)
873{
874 unsigned int handled = 0;
875 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
876 u32 port_status, err_mask;
877
878 err_mask = PDC_ERR_MASK;
879 if (ap->flags & PDC_FLAG_GEN_II)
880 err_mask &= ~PDC1_ERR_MASK;
881 else
882 err_mask &= ~PDC2_ERR_MASK;
883 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
884 if (unlikely(port_status & err_mask)) {
885 pdc_error_intr(ap, qc, port_status, err_mask);
886 return 1;
887 }
888
889 switch (qc->tf.protocol) {
890 case ATA_PROT_DMA:
891 case ATA_PROT_NODATA:
892 case ATAPI_PROT_DMA:
893 case ATAPI_PROT_NODATA:
894 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
895 ata_qc_complete(qc);
896 handled = 1;
897 break;
898 default:
899 ap->stats.idle_irq++;
900 break;
901 }
902
903 return handled;
904}
905
906static void pdc_irq_clear(struct ata_port *ap)
907{
908 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
909
910 readl(ata_mmio + PDC_COMMAND);
911}
912
913static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
914{
915 struct ata_host *host = dev_instance;
916 struct ata_port *ap;
917 u32 mask = 0;
918 unsigned int i, tmp;
919 unsigned int handled = 0;
920 void __iomem *host_mmio;
921 unsigned int hotplug_offset, ata_no;
922 u32 hotplug_status;
923 int is_sataii_tx4;
924
925 VPRINTK("ENTER\n");
926
927 if (!host || !host->iomap[PDC_MMIO_BAR]) {
928 VPRINTK("QUICK EXIT\n");
929 return IRQ_NONE;
930 }
931
932 host_mmio = host->iomap[PDC_MMIO_BAR];
933
934 spin_lock(&host->lock);
935
936
937 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
938 hotplug_offset = PDC2_SATA_PLUG_CSR;
939 hotplug_status = readl(host_mmio + hotplug_offset);
940 if (hotplug_status & 0xff)
941 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
942 hotplug_status &= 0xff;
943 } else
944 hotplug_status = 0;
945
946
947 mask = readl(host_mmio + PDC_INT_SEQMASK);
948
949 if (mask == 0xffffffff && hotplug_status == 0) {
950 VPRINTK("QUICK EXIT 2\n");
951 goto done_irq;
952 }
953
954 mask &= 0xffff;
955 if (mask == 0 && hotplug_status == 0) {
956 VPRINTK("QUICK EXIT 3\n");
957 goto done_irq;
958 }
959
960 writel(mask, host_mmio + PDC_INT_SEQMASK);
961
962 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
963
964 for (i = 0; i < host->n_ports; i++) {
965 VPRINTK("port %u\n", i);
966 ap = host->ports[i];
967
968
969 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
970 tmp = hotplug_status & (0x11 << ata_no);
971 if (tmp) {
972 struct ata_eh_info *ehi = &ap->link.eh_info;
973 ata_ehi_clear_desc(ehi);
974 ata_ehi_hotplugged(ehi);
975 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
976 ata_port_freeze(ap);
977 ++handled;
978 continue;
979 }
980
981
982 tmp = mask & (1 << (i + 1));
983 if (tmp) {
984 struct ata_queued_cmd *qc;
985
986 qc = ata_qc_from_tag(ap, ap->link.active_tag);
987 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
988 handled += pdc_host_intr(ap, qc);
989 }
990 }
991
992 VPRINTK("EXIT\n");
993
994done_irq:
995 spin_unlock(&host->lock);
996 return IRQ_RETVAL(handled);
997}
998
999static void pdc_packet_start(struct ata_queued_cmd *qc)
1000{
1001 struct ata_port *ap = qc->ap;
1002 struct pdc_port_priv *pp = ap->private_data;
1003 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1004 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1005 unsigned int port_no = ap->port_no;
1006 u8 seq = (u8) (port_no + 1);
1007
1008 VPRINTK("ENTER, ap %p\n", ap);
1009
1010 writel(0x00000001, host_mmio + (seq * 4));
1011 readl(host_mmio + (seq * 4));
1012
1013 pp->pkt[2] = seq;
1014 wmb();
1015 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1016 readl(ata_mmio + PDC_PKT_SUBMIT);
1017}
1018
1019static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1020{
1021 switch (qc->tf.protocol) {
1022 case ATAPI_PROT_NODATA:
1023 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1024 break;
1025 fallthrough;
1026 case ATA_PROT_NODATA:
1027 if (qc->tf.flags & ATA_TFLAG_POLLING)
1028 break;
1029 fallthrough;
1030 case ATAPI_PROT_DMA:
1031 case ATA_PROT_DMA:
1032 pdc_packet_start(qc);
1033 return 0;
1034 default:
1035 break;
1036 }
1037 return ata_sff_qc_issue(qc);
1038}
1039
1040static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1041{
1042 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1043 ata_sff_tf_load(ap, tf);
1044}
1045
1046static void pdc_exec_command_mmio(struct ata_port *ap,
1047 const struct ata_taskfile *tf)
1048{
1049 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1050 ata_sff_exec_command(ap, tf);
1051}
1052
1053static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1054{
1055 u8 *scsicmd = qc->scsicmd->cmnd;
1056 int pio = 1;
1057
1058
1059 switch (scsicmd[0]) {
1060 case WRITE_12:
1061 case WRITE_10:
1062 case WRITE_6:
1063 case READ_12:
1064 case READ_10:
1065 case READ_6:
1066 case 0xad:
1067 case 0xbe:
1068 pio = 0;
1069 }
1070
1071 if (scsicmd[0] == WRITE_10) {
1072 unsigned int lba =
1073 (scsicmd[2] << 24) |
1074 (scsicmd[3] << 16) |
1075 (scsicmd[4] << 8) |
1076 scsicmd[5];
1077 if (lba >= 0xFFFF4FA2)
1078 pio = 1;
1079 }
1080 return pio;
1081}
1082
1083static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1084{
1085
1086 return 1;
1087}
1088
1089static void pdc_ata_setup_port(struct ata_port *ap,
1090 void __iomem *base, void __iomem *scr_addr)
1091{
1092 ap->ioaddr.cmd_addr = base;
1093 ap->ioaddr.data_addr = base;
1094 ap->ioaddr.feature_addr =
1095 ap->ioaddr.error_addr = base + 0x4;
1096 ap->ioaddr.nsect_addr = base + 0x8;
1097 ap->ioaddr.lbal_addr = base + 0xc;
1098 ap->ioaddr.lbam_addr = base + 0x10;
1099 ap->ioaddr.lbah_addr = base + 0x14;
1100 ap->ioaddr.device_addr = base + 0x18;
1101 ap->ioaddr.command_addr =
1102 ap->ioaddr.status_addr = base + 0x1c;
1103 ap->ioaddr.altstatus_addr =
1104 ap->ioaddr.ctl_addr = base + 0x38;
1105 ap->ioaddr.scr_addr = scr_addr;
1106}
1107
1108static void pdc_host_init(struct ata_host *host)
1109{
1110 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1111 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1112 int hotplug_offset;
1113 u32 tmp;
1114
1115 if (is_gen2)
1116 hotplug_offset = PDC2_SATA_PLUG_CSR;
1117 else
1118 hotplug_offset = PDC_SATA_PLUG_CSR;
1119
1120
1121
1122
1123
1124
1125
1126
1127 tmp = readl(host_mmio + PDC_FLASH_CTL);
1128 tmp |= 0x02000;
1129 if (!is_gen2)
1130 tmp |= 0x10000;
1131 writel(tmp, host_mmio + PDC_FLASH_CTL);
1132
1133
1134 tmp = readl(host_mmio + hotplug_offset);
1135 writel(tmp | 0xff, host_mmio + hotplug_offset);
1136
1137 tmp = readl(host_mmio + hotplug_offset);
1138 if (is_gen2)
1139 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1140 else
1141 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1142
1143
1144 if (is_gen2)
1145 return;
1146
1147
1148 tmp = readl(host_mmio + PDC_TBG_MODE);
1149 tmp &= ~0x30000;
1150 tmp |= 0x10000;
1151 writel(tmp, host_mmio + PDC_TBG_MODE);
1152
1153 readl(host_mmio + PDC_TBG_MODE);
1154 msleep(10);
1155
1156
1157 tmp = readl(host_mmio + PDC_SLEW_CTL);
1158 tmp &= 0xFFFFF03F;
1159 tmp |= 0x00000900;
1160 writel(tmp, host_mmio + PDC_SLEW_CTL);
1161}
1162
1163static int pdc_ata_init_one(struct pci_dev *pdev,
1164 const struct pci_device_id *ent)
1165{
1166 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1167 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1168 struct ata_host *host;
1169 struct pdc_host_priv *hpriv;
1170 void __iomem *host_mmio;
1171 int n_ports, i, rc;
1172 int is_sataii_tx4;
1173
1174 ata_print_version_once(&pdev->dev, DRV_VERSION);
1175
1176
1177 rc = pcim_enable_device(pdev);
1178 if (rc)
1179 return rc;
1180
1181 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1182 if (rc == -EBUSY)
1183 pcim_pin_device(pdev);
1184 if (rc)
1185 return rc;
1186 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1187
1188
1189 n_ports = 2;
1190 if (pi->flags & PDC_FLAG_4_PORTS)
1191 n_ports = 4;
1192 for (i = 0; i < n_ports; i++)
1193 ppi[i] = pi;
1194
1195 if (pi->flags & PDC_FLAG_SATA_PATA) {
1196 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1197 if (!(tmp & 0x80))
1198 ppi[n_ports++] = pi + 1;
1199 }
1200
1201 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1202 if (!host) {
1203 dev_err(&pdev->dev, "failed to allocate host\n");
1204 return -ENOMEM;
1205 }
1206 hpriv = devm_kzalloc(&pdev->dev, sizeof *hpriv, GFP_KERNEL);
1207 if (!hpriv)
1208 return -ENOMEM;
1209 spin_lock_init(&hpriv->hard_reset_lock);
1210 host->private_data = hpriv;
1211 host->iomap = pcim_iomap_table(pdev);
1212
1213 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1214 for (i = 0; i < host->n_ports; i++) {
1215 struct ata_port *ap = host->ports[i];
1216 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1217 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1218 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1219
1220 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1221
1222 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1223 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1224 }
1225
1226
1227 pdc_host_init(host);
1228
1229 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1230 if (rc)
1231 return rc;
1232
1233
1234 pci_set_master(pdev);
1235 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1236 &pdc_ata_sht);
1237}
1238
1239module_pci_driver(pdc_ata_pci_driver);
1240
1241MODULE_AUTHOR("Jeff Garzik");
1242MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1243MODULE_LICENSE("GPL");
1244MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1245MODULE_VERSION(DRV_VERSION);
1246
